[RISCV] Override TargetLowering::hasAndNot for Zbb.

[lebedev.ri]

Sadly still completely ignorant about RISC-V, won't have useful insights here.

[craig.topper]

llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll

1152–1153

This is a size regression, but the comment above it also says this isn't canonical form.

1418–1420

This also appears to be a size regression.

[jrtc27]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1115–1118

Might possibly make more sense to write as:

if (Subtarget.hasStdExtZbb() && isa<ConstantSDNode>(Y))
  return true;

return false;

depending on how this will be extended in future (e.g. with vector support?)

1118

I think your code size regressions come from this not using Y.getNode()? SDValue is never a ConstantSDNode, so for Zbb this always returns true.

[craig.topper]

Rebase after fixing DAGCombiner to not cause the size regressions.

[craig.topper]

Remove TODO that this patch addresses

[jrtc27]

I'm assuming in_constant_42_vary_invmask is still regressing just because you haven't yet rebased on top of the updated DAGCombine patch and not because something else is missing?

llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll

171

Do we still want a TODO for non-Zbb out* to use the shorter sequence that in* use? Currently out* have an extra instruction (two for i64-on-RV32).

[craig.topper]

Rebase

[craig.topper]

llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll

171

I guess that's the RISCV equivalent of https://reviews.llvm.org/D112754

I can add a TODO

[jrtc27]

llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll

171

Looks rather familiar... which I guess means it should live in DAGCombine, not X86ISelLowering, though care is needed to avoid circular combines...

[craig.topper]

Add TODO

llvm/lib/Target/RISCV/RISCVISelLowering.h

 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
public:
   bool isLegalICmpImmediate(int64_t Imm) const override;
   bool isLegalAddImmediate(int64_t Imm) const override;
   bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
   bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
   bool isZExtFree(SDValue Val, EVT VT2) const override;
   bool isSExtCheaperThanZExt(EVT SrcVT, EVT DstVT) const override;
   bool isCheapToSpeculateCttz() const override;
   bool isCheapToSpeculateCtlz() const override;
+  bool hasAndNot(SDValue Y) const override;
   bool shouldSinkOperands(Instruction *I,
                           SmallVectorImpl<Use *> &Ops) const override;
   bool isFPImmLegal(const APFloat &Imm, EVT VT,
                     bool ForCodeSize) const override;
 
   bool softPromoteHalfType() const override { return true; }
 
   /// Return the register type for a given MVT, ensuring vectors are treated

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 bool RISCVTargetLowering::isCheapToSpeculateCttz() const {
   return Subtarget.hasStdExtZbb();
 }
 
 bool RISCVTargetLowering::isCheapToSpeculateCtlz() const {
   return Subtarget.hasStdExtZbb();
 }
 
+bool RISCVTargetLowering::hasAndNot(SDValue Y) const {
+  EVT VT = Y.getValueType();
+
+  // FIXME: Support vectors once we have tests.
+  if (VT.isVector())
+    return false;
+
+  if (!Subtarget.hasStdExtZbb())
+    return false;
+
+  return !isa<ConstantSDNode>(Y);
+}
+
 /// Check if sinking \p I's operands to I's basic block is profitable, because
 /// the operands can be folded into a target instruction, e.g.
 /// splats of scalars can fold into vector instructions.
 bool RISCVTargetLowering::shouldSinkOperands(
     Instruction *I, SmallVectorImpl<Use *> &Ops) const {
   using namespace llvm::PatternMatch;
 
   if (!I->getType()->isVectorTy() || !Subtarget.hasVInstructions())

llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll

 ; RV64-NEXT:    ret
   %tmp.1 = icmp sgt i32 %a, -1
   %retval = select i1 %tmp.1, i32 512, i32 0
   ret i32 %retval
 }
 
 ; Compare if positive and select variable or zero.
 define i32 @pos_sel_variable_and_zero(i32 signext %a, i32 signext %b) {
-; CHECK-LABEL: pos_sel_variable_and_zero:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    bgez a0, .LBB6_2
-; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    mv a1, zero
-; CHECK-NEXT:  .LBB6_2:
-; CHECK-NEXT:    mv a0, a1
-; CHECK-NEXT:    ret
+; RV32I-LABEL: pos_sel_variable_and_zero:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    bgez a0, .LBB6_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a1, zero
+; RV32I-NEXT:  .LBB6_2:
+; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: pos_sel_variable_and_zero:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    bgez a0, .LBB6_2
+; RV64I-NEXT:  # %bb.1:
+; RV64I-NEXT:    mv a1, zero
+; RV64I-NEXT:  .LBB6_2:
+; RV64I-NEXT:    mv a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: pos_sel_variable_and_zero:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    srai a0, a0, 31
+; RV32ZBB-NEXT:    andn a0, a1, a0
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: pos_sel_variable_and_zero:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    srai a0, a0, 31
+; RV64ZBB-NEXT:    andn a0, a1, a0
+; RV64ZBB-NEXT:    ret
   %tmp.1 = icmp sgt i32 %a, -1
   %retval = select i1 %tmp.1, i32 %b, i32 0
   ret i32 %retval
 }
 
 ; Compare if not negative or zero and select the same variable as being
 ; compared: smax(a, 0).
 define i32 @not_neg_sel_same_variable(i32 signext %a) {

llvm/test/CodeGen/RISCV/unfold-masked-merge-scalar-variablemask.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 < %s \
 ; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32,RV32I
 ; RUN: llc -mtriple=riscv64 < %s \
 ; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64,RV64I
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb < %s \
 ; RUN:   | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZBB
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbb < %s \
 ; RUN:   | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZBB
 
+; TODO: Should we convert these to X ^ ((X ^ Y) & M) form when Zbb isn't
+; present?
+
 define i8 @out8(i8 %x, i8 %y, i8 %mask) {
 ; RV32I-LABEL: out8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    and a0, a0, a2
 ; RV32I-NEXT:    not a2, a2
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret
; RV64ZBB-NEXT:    ret
   %mx = and i64 %x, %mask
   %notmask = xor i64 %mask, -1
   %my = and i64 %y, %notmask
   %r = or i64 %mx, %my
   ret i64 %r
 }
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; TODO: These tests should produce the same output as the corresponding out* test.
+; These tests should produce the same output as the corresponding out* test
+; when the Zbb extension is enabled.
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 define i8 @in8(i8 %x, i8 %y, i8 %mask) {
-; CHECK-LABEL: in8:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    and a0, a0, a2
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in8:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    and a0, a0, a2
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in8:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    and a0, a0, a2
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in8:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    andn a1, a1, a2
+; RV32ZBB-NEXT:    and a0, a0, a2
+; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in8:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    andn a1, a1, a2
+; RV64ZBB-NEXT:    and a0, a0, a2
+; RV64ZBB-NEXT:    or a0, a0, a1
+; RV64ZBB-NEXT:    ret
   %n0 = xor i8 %x, %y
   %n1 = and i8 %n0, %mask
   %r = xor i8 %n1, %y
   ret i8 %r
 }
 
 define i16 @in16(i16 %x, i16 %y, i16 %mask) {
-; CHECK-LABEL: in16:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    and a0, a0, a2
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in16:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    and a0, a0, a2
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in16:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    and a0, a0, a2
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in16:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    andn a1, a1, a2
+; RV32ZBB-NEXT:    and a0, a0, a2
+; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in16:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    andn a1, a1, a2
+; RV64ZBB-NEXT:    and a0, a0, a2
+; RV64ZBB-NEXT:    or a0, a0, a1
+; RV64ZBB-NEXT:    ret
   %n0 = xor i16 %x, %y
   %n1 = and i16 %n0, %mask
   %r = xor i16 %n1, %y
   ret i16 %r
 }
 
 define i32 @in32(i32 %x, i32 %y, i32 %mask) {
-; CHECK-LABEL: in32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    and a0, a0, a2
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in32:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    and a0, a0, a2
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in32:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    and a0, a0, a2
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in32:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    andn a1, a1, a2
+; RV32ZBB-NEXT:    and a0, a0, a2
+; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in32:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    andn a1, a1, a2
+; RV64ZBB-NEXT:    and a0, a0, a2
+; RV64ZBB-NEXT:    or a0, a0, a1
+; RV64ZBB-NEXT:    ret
   %n0 = xor i32 %x, %y
   %n1 = and i32 %n0, %mask
   %r = xor i32 %n1, %y
   ret i32 %r
 }
 
 define i64 @in64(i64 %x, i64 %y, i64 %mask) {
-; RV32-LABEL: in64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    xor a0, a0, a2
-; RV32-NEXT:    xor a1, a1, a3
-; RV32-NEXT:    and a1, a1, a5
-; RV32-NEXT:    and a0, a0, a4
-; RV32-NEXT:    xor a0, a0, a2
-; RV32-NEXT:    xor a1, a1, a3
-; RV32-NEXT:    ret
+; RV32I-LABEL: in64:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    xor a0, a0, a2
+; RV32I-NEXT:    xor a1, a1, a3
+; RV32I-NEXT:    and a1, a1, a5
+; RV32I-NEXT:    and a0, a0, a4
+; RV32I-NEXT:    xor a0, a0, a2
+; RV32I-NEXT:    xor a1, a1, a3
+; RV32I-NEXT:    ret
 ;
-; RV64-LABEL: in64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    xor a0, a0, a1
-; RV64-NEXT:    and a0, a0, a2
-; RV64-NEXT:    xor a0, a0, a1
-; RV64-NEXT:    ret
+; RV64I-LABEL: in64:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    and a0, a0, a2
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in64:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    andn a2, a2, a4
+; RV32ZBB-NEXT:    and a0, a0, a4
+; RV32ZBB-NEXT:    or a0, a0, a2
+; RV32ZBB-NEXT:    andn a2, a3, a5
+; RV32ZBB-NEXT:    and a1, a1, a5
+; RV32ZBB-NEXT:    or a1, a1, a2
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in64:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    andn a1, a1, a2
+; RV64ZBB-NEXT:    and a0, a0, a2
+; RV64ZBB-NEXT:    or a0, a0, a1
+; RV64ZBB-NEXT:    ret
   %n0 = xor i64 %x, %y
   %n1 = and i64 %n0, %mask
   %r = xor i64 %n1, %y
   ret i64 %r
 }
 
 ; ============================================================================ ;
 ; Commutativity tests.
 ; ============================================================================ ;
 
 define i32 @in_commutativity_0_0_1(i32 %x, i32 %y, i32 %mask) {
-; CHECK-LABEL: in_commutativity_0_0_1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    and a0, a2, a0
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in_commutativity_0_0_1:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    and a0, a2, a0
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in_commutativity_0_0_1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    and a0, a2, a0
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in_commutativity_0_0_1:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    andn a1, a1, a2
+; RV32ZBB-NEXT:    and a0, a0, a2
+; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in_commutativity_0_0_1:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    andn a1, a1, a2
+; RV64ZBB-NEXT:    and a0, a0, a2
+; RV64ZBB-NEXT:    or a0, a0, a1
+; RV64ZBB-NEXT:    ret
   %n0 = xor i32 %x, %y
   %n1 = and i32 %mask, %n0 ; swapped
   %r = xor i32 %n1, %y
   ret i32 %r
 }
 
 define i32 @in_commutativity_0_1_0(i32 %x, i32 %y, i32 %mask) {
-; CHECK-LABEL: in_commutativity_0_1_0:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    and a0, a0, a2
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in_commutativity_0_1_0:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    and a0, a0, a2
+; RV32I-NEXT:    xor a0, a1, a0
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in_commutativity_0_1_0:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    and a0, a0, a2
+; RV64I-NEXT:    xor a0, a1, a0
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in_commutativity_0_1_0:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    andn a1, a1, a2
+; RV32ZBB-NEXT:    and a0, a0, a2
+; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in_commutativity_0_1_0:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    andn a1, a1, a2
+; RV64ZBB-NEXT:    and a0, a0, a2
+; RV64ZBB-NEXT:    or a0, a0, a1
+; RV64ZBB-NEXT:    ret
   %n0 = xor i32 %x, %y
   %n1 = and i32 %n0, %mask
   %r = xor i32 %y, %n1 ; swapped
   ret i32 %r
 }
 
 define i32 @in_commutativity_0_1_1(i32 %x, i32 %y, i32 %mask) {
-; CHECK-LABEL: in_commutativity_0_1_1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    and a0, a2, a0
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in_commutativity_0_1_1:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    and a0, a2, a0
+; RV32I-NEXT:    xor a0, a1, a0
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in_commutativity_0_1_1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    and a0, a2, a0
+; RV64I-NEXT:    xor a0, a1, a0
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in_commutativity_0_1_1:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    andn a1, a1, a2
+; RV32ZBB-NEXT:    and a0, a0, a2
+; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in_commutativity_0_1_1:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    andn a1, a1, a2
+; RV64ZBB-NEXT:    and a0, a0, a2
+; RV64ZBB-NEXT:    or a0, a0, a1
+; RV64ZBB-NEXT:    ret
   %n0 = xor i32 %x, %y
   %n1 = and i32 %mask, %n0 ; swapped
   %r = xor i32 %y, %n1 ; swapped
   ret i32 %r
 }
 
 define i32 @in_commutativity_1_0_0(i32 %x, i32 %y, i32 %mask) {
-; CHECK-LABEL: in_commutativity_1_0_0:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    xor a1, a0, a1
-; CHECK-NEXT:    and a1, a1, a2
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in_commutativity_1_0_0:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    xor a1, a0, a1
+; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    xor a0, a1, a0
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in_commutativity_1_0_0:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    xor a1, a0, a1
+; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    xor a0, a1, a0
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in_commutativity_1_0_0:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    andn a0, a0, a2
+; RV32ZBB-NEXT:    and a1, a1, a2
+; RV32ZBB-NEXT:    or a0, a1, a0
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in_commutativity_1_0_0:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    andn a0, a0, a2
+; RV64ZBB-NEXT:    and a1, a1, a2
+; RV64ZBB-NEXT:    or a0, a1, a0
+; RV64ZBB-NEXT:    ret
   %n0 = xor i32 %x, %y
   %n1 = and i32 %n0, %mask
   %r = xor i32 %n1, %x ; %x instead of %y
   ret i32 %r
 }
 
 define i32 @in_commutativity_1_0_1(i32 %x, i32 %y, i32 %mask) {
-; CHECK-LABEL: in_commutativity_1_0_1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    xor a1, a0, a1
-; CHECK-NEXT:    and a1, a2, a1
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in_commutativity_1_0_1:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    xor a1, a0, a1
+; RV32I-NEXT:    and a1, a2, a1
+; RV32I-NEXT:    xor a0, a1, a0
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in_commutativity_1_0_1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    xor a1, a0, a1
+; RV64I-NEXT:    and a1, a2, a1
+; RV64I-NEXT:    xor a0, a1, a0
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in_commutativity_1_0_1:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    andn a0, a0, a2
+; RV32ZBB-NEXT:    and a1, a1, a2
+; RV32ZBB-NEXT:    or a0, a1, a0
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in_commutativity_1_0_1:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    andn a0, a0, a2
+; RV64ZBB-NEXT:    and a1, a1, a2
+; RV64ZBB-NEXT:    or a0, a1, a0
+; RV64ZBB-NEXT:    ret
   %n0 = xor i32 %x, %y
   %n1 = and i32 %mask, %n0 ; swapped
   %r = xor i32 %n1, %x ; %x instead of %y
   ret i32 %r
 }
 
 define i32 @in_commutativity_1_1_0(i32 %x, i32 %y, i32 %mask) {
-; CHECK-LABEL: in_commutativity_1_1_0:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    xor a1, a0, a1
-; CHECK-NEXT:    and a1, a1, a2
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in_commutativity_1_1_0:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    xor a1, a0, a1
+; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in_commutativity_1_1_0:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    xor a1, a0, a1
+; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in_commutativity_1_1_0:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    andn a0, a0, a2
+; RV32ZBB-NEXT:    and a1, a1, a2
+; RV32ZBB-NEXT:    or a0, a1, a0
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in_commutativity_1_1_0:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    andn a0, a0, a2
+; RV64ZBB-NEXT:    and a1, a1, a2
+; RV64ZBB-NEXT:    or a0, a1, a0
+; RV64ZBB-NEXT:    ret
   %n0 = xor i32 %x, %y
   %n1 = and i32 %n0, %mask
   %r = xor i32 %x, %n1 ; swapped, %x instead of %y
   ret i32 %r
 }
 
 define i32 @in_commutativity_1_1_1(i32 %x, i32 %y, i32 %mask) {
-; CHECK-LABEL: in_commutativity_1_1_1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    xor a1, a0, a1
-; CHECK-NEXT:    and a1, a2, a1
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in_commutativity_1_1_1:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    xor a1, a0, a1
+; RV32I-NEXT:    and a1, a2, a1
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in_commutativity_1_1_1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    xor a1, a0, a1
+; RV64I-NEXT:    and a1, a2, a1
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in_commutativity_1_1_1:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    andn a0, a0, a2
+; RV32ZBB-NEXT:    and a1, a1, a2
+; RV32ZBB-NEXT:    or a0, a1, a0
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in_commutativity_1_1_1:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    andn a0, a0, a2
+; RV64ZBB-NEXT:    and a1, a1, a2
+; RV64ZBB-NEXT:    or a0, a1, a0
+; RV64ZBB-NEXT:    ret
   %n0 = xor i32 %x, %y
   %n1 = and i32 %mask, %n0 ; swapped
   %r = xor i32 %x, %n1 ; swapped, %x instead of %y
   ret i32 %r
 }
 
 ; ============================================================================ ;
 ; Y is an 'and' too.
 ; ============================================================================ ;
 
 define i32 @in_complex_y0(i32 %x, i32 %y_hi, i32 %y_low, i32 %mask) {
-; CHECK-LABEL: in_complex_y0:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    and a1, a1, a2
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    and a0, a0, a3
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in_complex_y0:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    and a0, a0, a3
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in_complex_y0:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    and a0, a0, a3
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in_complex_y0:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    and a1, a1, a2
+; RV32ZBB-NEXT:    and a0, a0, a3
+; RV32ZBB-NEXT:    andn a1, a1, a3
+; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in_complex_y0:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    and a1, a1, a2
+; RV64ZBB-NEXT:    and a0, a0, a3
+; RV64ZBB-NEXT:    andn a1, a1, a3
+; RV64ZBB-NEXT:    or a0, a0, a1
+; RV64ZBB-NEXT:    ret
   %y = and i32 %y_hi, %y_low
   %n0 = xor i32 %x, %y
   %n1 = and i32 %n0, %mask
   %r = xor i32 %n1, %y
   ret i32 %r
 }
 
 define i32 @in_complex_y1(i32 %x, i32 %y_hi, i32 %y_low, i32 %mask) {
-; CHECK-LABEL: in_complex_y1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    and a1, a1, a2
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    and a0, a0, a3
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in_complex_y1:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    and a0, a0, a3
+; RV32I-NEXT:    xor a0, a1, a0
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in_complex_y1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    and a0, a0, a3
+; RV64I-NEXT:    xor a0, a1, a0
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in_complex_y1:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    and a1, a1, a2
+; RV32ZBB-NEXT:    and a0, a0, a3
+; RV32ZBB-NEXT:    andn a1, a1, a3
+; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in_complex_y1:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    and a1, a1, a2
+; RV64ZBB-NEXT:    and a0, a0, a3
+; RV64ZBB-NEXT:    andn a1, a1, a3
+; RV64ZBB-NEXT:    or a0, a0, a1
+; RV64ZBB-NEXT:    ret
   %y = and i32 %y_hi, %y_low
   %n0 = xor i32 %x, %y
   %n1 = and i32 %n0, %mask
   %r = xor i32 %y, %n1
   ret i32 %r
 }
 
 ; ============================================================================ ;
 ; M is an 'xor' too.
 ; ============================================================================ ;
 
 define i32 @in_complex_m0(i32 %x, i32 %y, i32 %m_a, i32 %m_b) {
-; CHECK-LABEL: in_complex_m0:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    xor a2, a2, a3
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    and a0, a0, a2
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in_complex_m0:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    xor a2, a2, a3
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    and a0, a0, a2
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in_complex_m0:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    xor a2, a2, a3
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    and a0, a0, a2
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in_complex_m0:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    xor a2, a2, a3
+; RV32ZBB-NEXT:    andn a1, a1, a2
+; RV32ZBB-NEXT:    and a0, a0, a2
+; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in_complex_m0:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    xor a2, a2, a3
+; RV64ZBB-NEXT:    andn a1, a1, a2
+; RV64ZBB-NEXT:    and a0, a0, a2
+; RV64ZBB-NEXT:    or a0, a0, a1
+; RV64ZBB-NEXT:    ret
   %mask = xor i32 %m_a, %m_b
   %n0 = xor i32 %x, %y
   %n1 = and i32 %n0, %mask
   %r = xor i32 %n1, %y
   ret i32 %r
 }
 
 define i32 @in_complex_m1(i32 %x, i32 %y, i32 %m_a, i32 %m_b) {
-; CHECK-LABEL: in_complex_m1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    xor a2, a2, a3
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    and a0, a2, a0
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in_complex_m1:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    xor a2, a2, a3
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    and a0, a2, a0
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in_complex_m1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    xor a2, a2, a3
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    and a0, a2, a0
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in_complex_m1:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    xor a2, a2, a3
+; RV32ZBB-NEXT:    andn a1, a1, a2
+; RV32ZBB-NEXT:    and a0, a0, a2
+; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in_complex_m1:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    xor a2, a2, a3
+; RV64ZBB-NEXT:    andn a1, a1, a2
+; RV64ZBB-NEXT:    and a0, a0, a2
+; RV64ZBB-NEXT:    or a0, a0, a1
+; RV64ZBB-NEXT:    ret
   %mask = xor i32 %m_a, %m_b
   %n0 = xor i32 %x, %y
   %n1 = and i32 %mask, %n0
   %r = xor i32 %n1, %y
   ret i32 %r
 }
 
 ; ============================================================================ ;
 ; Both Y and M are complex.
 ; ============================================================================ ;
 
 define i32 @in_complex_y0_m0(i32 %x, i32 %y_hi, i32 %y_low, i32 %m_a, i32 %m_b) {
-; CHECK-LABEL: in_complex_y0_m0:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    and a1, a1, a2
-; CHECK-NEXT:    xor a2, a3, a4
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    and a0, a0, a2
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in_complex_y0_m0:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    xor a2, a3, a4
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    and a0, a0, a2
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in_complex_y0_m0:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    xor a2, a3, a4
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    and a0, a0, a2
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in_complex_y0_m0:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    and a1, a1, a2
+; RV32ZBB-NEXT:    xor a2, a3, a4
+; RV32ZBB-NEXT:    andn a1, a1, a2
+; RV32ZBB-NEXT:    and a0, a0, a2
+; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in_complex_y0_m0:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    and a1, a1, a2
+; RV64ZBB-NEXT:    xor a2, a3, a4
+; RV64ZBB-NEXT:    andn a1, a1, a2
+; RV64ZBB-NEXT:    and a0, a0, a2
+; RV64ZBB-NEXT:    or a0, a0, a1
+; RV64ZBB-NEXT:    ret
   %y = and i32 %y_hi, %y_low
   %mask = xor i32 %m_a, %m_b
   %n0 = xor i32 %x, %y
   %n1 = and i32 %n0, %mask
   %r = xor i32 %n1, %y
   ret i32 %r
 }
 
 define i32 @in_complex_y1_m0(i32 %x, i32 %y_hi, i32 %y_low, i32 %m_a, i32 %m_b) {
-; CHECK-LABEL: in_complex_y1_m0:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    and a1, a1, a2
-; CHECK-NEXT:    xor a2, a3, a4
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    and a0, a0, a2
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in_complex_y1_m0:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    xor a2, a3, a4
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    and a0, a0, a2
+; RV32I-NEXT:    xor a0, a1, a0
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in_complex_y1_m0:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    xor a2, a3, a4
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    and a0, a0, a2
+; RV64I-NEXT:    xor a0, a1, a0
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in_complex_y1_m0:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    and a1, a1, a2
+; RV32ZBB-NEXT:    xor a2, a3, a4
+; RV32ZBB-NEXT:    andn a1, a1, a2
+; RV32ZBB-NEXT:    and a0, a0, a2
+; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in_complex_y1_m0:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    and a1, a1, a2
+; RV64ZBB-NEXT:    xor a2, a3, a4
+; RV64ZBB-NEXT:    andn a1, a1, a2
+; RV64ZBB-NEXT:    and a0, a0, a2
+; RV64ZBB-NEXT:    or a0, a0, a1
+; RV64ZBB-NEXT:    ret
   %y = and i32 %y_hi, %y_low
   %mask = xor i32 %m_a, %m_b
   %n0 = xor i32 %x, %y
   %n1 = and i32 %n0, %mask
   %r = xor i32 %y, %n1
   ret i32 %r
 }
 
 define i32 @in_complex_y0_m1(i32 %x, i32 %y_hi, i32 %y_low, i32 %m_a, i32 %m_b) {
-; CHECK-LABEL: in_complex_y0_m1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    and a1, a1, a2
-; CHECK-NEXT:    xor a2, a3, a4
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    and a0, a2, a0
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in_complex_y0_m1:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    xor a2, a3, a4
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    and a0, a2, a0
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in_complex_y0_m1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    xor a2, a3, a4
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    and a0, a2, a0
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in_complex_y0_m1:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    and a1, a1, a2
+; RV32ZBB-NEXT:    xor a2, a3, a4
+; RV32ZBB-NEXT:    andn a1, a1, a2
+; RV32ZBB-NEXT:    and a0, a0, a2
+; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in_complex_y0_m1:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    and a1, a1, a2
+; RV64ZBB-NEXT:    xor a2, a3, a4
+; RV64ZBB-NEXT:    andn a1, a1, a2
+; RV64ZBB-NEXT:    and a0, a0, a2
+; RV64ZBB-NEXT:    or a0, a0, a1
+; RV64ZBB-NEXT:    ret
   %y = and i32 %y_hi, %y_low
   %mask = xor i32 %m_a, %m_b
   %n0 = xor i32 %x, %y
   %n1 = and i32 %mask, %n0
   %r = xor i32 %n1, %y
   ret i32 %r
 }
 
 define i32 @in_complex_y1_m1(i32 %x, i32 %y_hi, i32 %y_low, i32 %m_a, i32 %m_b) {
-; CHECK-LABEL: in_complex_y1_m1:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    and a1, a1, a2
-; CHECK-NEXT:    xor a2, a3, a4
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    and a0, a2, a0
-; CHECK-NEXT:    xor a0, a1, a0
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in_complex_y1_m1:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    xor a2, a3, a4
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    and a0, a2, a0
+; RV32I-NEXT:    xor a0, a1, a0
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in_complex_y1_m1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    xor a2, a3, a4
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    and a0, a2, a0
+; RV64I-NEXT:    xor a0, a1, a0
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in_complex_y1_m1:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    and a1, a1, a2
+; RV32ZBB-NEXT:    xor a2, a3, a4
+; RV32ZBB-NEXT:    andn a1, a1, a2
+; RV32ZBB-NEXT:    and a0, a0, a2
+; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in_complex_y1_m1:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    and a1, a1, a2
+; RV64ZBB-NEXT:    xor a2, a3, a4
+; RV64ZBB-NEXT:    andn a1, a1, a2
+; RV64ZBB-NEXT:    and a0, a0, a2
+; RV64ZBB-NEXT:    or a0, a0, a1
+; RV64ZBB-NEXT:    ret
   %y = and i32 %y_hi, %y_low
   %mask = xor i32 %m_a, %m_b
   %n0 = xor i32 %x, %y
   %n1 = and i32 %mask, %n0
   %r = xor i32 %y, %n1
   ret i32 %r
 }
 
; RV64ZBB-NEXT:    ret
   %notmask = xor i32 %mask, -1
   %mx = and i32 %mask, %x
   %my = and i32 %notmask, 42
   %r = or i32 %mx, %my
   ret i32 %r
 }
 
 define i32 @in_constant_varx_42(i32 %x, i32 %y, i32 %mask) {
-; CHECK-LABEL: in_constant_varx_42:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    xori a0, a0, 42
-; CHECK-NEXT:    and a0, a0, a2
-; CHECK-NEXT:    xori a0, a0, 42
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in_constant_varx_42:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    xori a0, a0, 42
+; RV32I-NEXT:    and a0, a0, a2
+; RV32I-NEXT:    xori a0, a0, 42
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in_constant_varx_42:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    xori a0, a0, 42
+; RV64I-NEXT:    and a0, a0, a2
+; RV64I-NEXT:    xori a0, a0, 42
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in_constant_varx_42:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    andn a0, a2, a0
+; RV32ZBB-NEXT:    ori a1, a2, 42
+; RV32ZBB-NEXT:    andn a0, a1, a0
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in_constant_varx_42:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    andn a0, a2, a0
+; RV64ZBB-NEXT:    ori a1, a2, 42
+; RV64ZBB-NEXT:    andn a0, a1, a0
+; RV64ZBB-NEXT:    ret
   %n0 = xor i32 %x, 42 ; %x
   %n1 = and i32 %n0, %mask
   %r = xor i32 %n1, 42
   ret i32 %r
 }
 
 ; This is not a canonical form. Testing for completeness only.
 define i32 @out_constant_varx_42_invmask(i32 %x, i32 %y, i32 %mask) {

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    not a1, a2
 ; RV64I-NEXT:    xori a0, a0, 42
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    xori a0, a0, 42
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: in_constant_varx_42_invmask:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    xori a0, a0, 42
 ; RV32ZBB-NEXT:    andn a0, a0, a2
-; RV32ZBB-NEXT:    xori a0, a0, 42
+; RV32ZBB-NEXT:    andi a1, a2, 42
+; RV32ZBB-NEXT:    or a0, a0, a1
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: in_constant_varx_42_invmask:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    xori a0, a0, 42
 ; RV64ZBB-NEXT:    andn a0, a0, a2
-; RV64ZBB-NEXT:    xori a0, a0, 42
+; RV64ZBB-NEXT:    andi a1, a2, 42
+; RV64ZBB-NEXT:    or a0, a0, a1
 ; RV64ZBB-NEXT:    ret
   %notmask = xor i32 %mask, -1
   %n0 = xor i32 %x, 42 ; %x
   %n1 = and i32 %n0, %notmask
   %r = xor i32 %n1, 42
   ret i32 %r
 }
 
; RV64ZBB-NEXT:    ret
   %notmask = xor i32 %mask, -1
   %mx = and i32 %mask, 42
   %my = and i32 %notmask, %y
   %r = or i32 %mx, %my
   ret i32 %r
 }
 
 define i32 @in_constant_42_vary(i32 %x, i32 %y, i32 %mask) {
-; CHECK-LABEL: in_constant_42_vary:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    xori a0, a1, 42
-; CHECK-NEXT:    and a0, a0, a2
-; CHECK-NEXT:    xor a0, a0, a1
-; CHECK-NEXT:    ret
+; RV32I-LABEL: in_constant_42_vary:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    xori a0, a1, 42
+; RV32I-NEXT:    and a0, a0, a2
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: in_constant_42_vary:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    xori a0, a1, 42
+; RV64I-NEXT:    and a0, a0, a2
+; RV64I-NEXT:    xor a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV32ZBB-LABEL: in_constant_42_vary:
+; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    andn a0, a1, a2
+; RV32ZBB-NEXT:    andi a1, a2, 42
+; RV32ZBB-NEXT:    or a0, a1, a0
+; RV32ZBB-NEXT:    ret
+;
+; RV64ZBB-LABEL: in_constant_42_vary:
+; RV64ZBB:       # %bb.0:
+; RV64ZBB-NEXT:    andn a0, a1, a2
+; RV64ZBB-NEXT:    andi a1, a2, 42
+; RV64ZBB-NEXT:    or a0, a1, a0
+; RV64ZBB-NEXT:    ret
   %n0 = xor i32 42, %y ; %x
   %n1 = and i32 %n0, %mask
   %r = xor i32 %n1, %y
   ret i32 %r
 }
 
 ; This is not a canonical form. Testing for completeness only.
 define i32 @out_constant_42_vary_invmask(i32 %x, i32 %y, i32 %mask) {

 ; RV64I-NEXT:    not a0, a2
 ; RV64I-NEXT:    xori a2, a1, 42
 ; RV64I-NEXT:    and a0, a2, a0
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: in_constant_42_vary_invmask:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    xori a0, a1, 42
-; RV32ZBB-NEXT:    andn a0, a0, a2
-; RV32ZBB-NEXT:    xor a0, a0, a1
+; RV32ZBB-NEXT:    andn a0, a2, a1
+; RV32ZBB-NEXT:    ori a1, a2, 42
+; RV32ZBB-NEXT:    andn a0, a1, a0
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: in_constant_42_vary_invmask:
 ; RV64ZBB:       # %bb.0:
-; RV64ZBB-NEXT:    xori a0, a1, 42
-; RV64ZBB-NEXT:    andn a0, a0, a2
-; RV64ZBB-NEXT:    xor a0, a0, a1
+; RV64ZBB-NEXT:    andn a0, a2, a1
+; RV64ZBB-NEXT:    ori a1, a2, 42
+; RV64ZBB-NEXT:    andn a0, a1, a0
 ; RV64ZBB-NEXT:    ret
   %notmask = xor i32 %mask, -1
   %n0 = xor i32 42, %y ; %x
   %n1 = and i32 %n0, %notmask
   %r = xor i32 %n1, %y
   ret i32 %r
 }