[RISCV] Add SiFive cores E and S series

[apivovarov]

Summary

Add SiFive cores E20, E21, E24, E34, S21, S54 and S76

gcc: https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/riscv-cores.def#L34

[craig.topper]

Are you planning to add more CPUs? I think I'd be willing to accept them all as one patch instead of one small patch for each CPU.

[apivovarov]

Another missing combination is:

• e24 and e34 (rocket, rv32imafc)

I can also add several cores which are similar to existing cores:

• e21 (same as existing e31 - rocket, rv32imac)
• s21 (same as existing s51 - rocket, rv64imac)
• s54 (same as existing u54 - rocket, rv64imafdc)
• s76 (same as existing u74 - SiFive7, rv64imafdc)

To match gcc cores definition - https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/riscv-cores.def#L34

[apivovarov]

Added SiFive cores E20, E21, E24, E34, S21, S54 and S76

[craig.topper]

llvm/include/llvm/Support/RISCVTargetParser.def

24

Should SIFIVE_E34 be SIFIVE_E24?

26

Should SIFIVE_U74 be SIFIVE_S76?

llvm/lib/Target/RISCV/RISCV.td

270

Can we sort these by leading digit, then by letter? That will keep most of the SiFive7Models together.

[craig.topper]

llvm/include/llvm/Support/RISCVTargetParser.def

24

This duplication should fail the build I think?

[apivovarov]

fix typos

[apivovarov]

llvm/lib/Target/RISCV/RISCV.td

270

Well, it is sorted by core_type + number in all other places in LLVM codebase (including error messages). GCC also sorts them as E-S-U. As well as sifive.com

[craig.topper]

clang/test/Misc/target-invalid-cpu-note.c

195

Why 2 spaces after commas here?

llvm/lib/Target/RISCV/RISCV.td

270

Ok. I was basing that request on our internal codebase where we have them sorted the other way. But it doesn't matter a lot to me.

[apivovarov]

main branch is unstable. pulling the hot fixes again....

[apivovarov]

fix double space issue. Fri...

[apivovarov]

Craig, I fixed all of the issue on Fri. Could you look at the patch again? Thank you

[craig.topper]

LGTM

clang/docs/ReleaseNotes.rst

 
 - ...
 
 Modified Compiler Flags
 -----------------------
 
 - Support has been added for the following processors (``-mcpu`` identifiers in parentheses):
 
+  - RISC-V SiFive E20 (``sifive-e20``).
   - RISC-V SiFive S51 (``sifive-s51``).
 
 Removed Compiler Flags
 -------------------------
 
 - ...
 
 New Pragmas in Clang

clang/test/Driver/riscv-cpus.c

 
 // RUN: %clang -target riscv32 -### -c %s 2>&1 -mtune=sifive-7-series | FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-32 %s
 // MTUNE-SIFIVE7-SERIES-32: "-tune-cpu" "sifive-7-rv32"
 
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mtune=sifive-7-series | FileCheck -check-prefix=MTUNE-SIFIVE7-SERIES-64 %s
 // MTUNE-SIFIVE7-SERIES-64: "-tune-cpu" "sifive-7-rv64"
 
 // mcpu with mabi option
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e20 -mabi=ilp32 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-E20 %s
+// MCPU-ABI-SIFIVE-E20: "-nostdsysteminc" "-target-cpu" "sifive-e20"
+// MCPU-ABI-SIFIVE-E20: "-target-feature" "+m" "-target-feature" "+c"
+// MCPU-ABI-SIFIVE-E20: "-target-abi" "ilp32"
+
+// mcpu with mabi option
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-s51 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S51 %s
 // MCPU-ABI-SIFIVE-S51: "-nostdsysteminc" "-target-cpu" "sifive-s51"
 // MCPU-ABI-SIFIVE-S51: "-target-feature" "+m" "-target-feature" "+a"
 // MCPU-ABI-SIFIVE-S51: "-target-feature" "+c" "-target-feature" "+64bit"
 // MCPU-ABI-SIFIVE-S51: "-target-abi" "lp64"
 
 // mcpu with default march
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck -check-prefix=MCPU-SIFIVE-U54 %s

clang/test/Misc/target-invalid-cpu-note.c

 // AVR-SAME: atxmega128d4, atxmega192a3, atxmega192a3u, atxmega192c3, atxmega192d3,
 // AVR-SAME: atxmega256a3, atxmega256a3u, atxmega256a3b, atxmega256a3bu, atxmega256c3,
 // AVR-SAME: atxmega256d3, atxmega384c3, atxmega384d3, atxmega128a1, atxmega128a1u,
 // AVR-SAME: atxmega128a4u, attiny4, attiny5, attiny9, attiny10, attiny20, attiny40,
 // AVR-SAME: attiny102, attiny104
 
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
-// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e31, sifive-e76
+// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e20, sifive-e31, sifive-e76
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
 // RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-7-rv64, sifive-s51, sifive-u54, sifive-u74
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e31, sifive-e76, generic, rocket, sifive-7-series
+// TUNE-RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-7-rv32, sifive-e20, sifive-e31, sifive-e76, generic, rocket, sifive-7-series
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
 // TUNE-RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-7-rv64, sifive-s51, sifive-u54, sifive-u74, generic, rocket, sifive-7-series

llvm/include/llvm/Support/RISCVTargetParser.def

 
 PROC(INVALID, {"invalid"}, FK_INVALID, {""})
 PROC(GENERIC_RV32, {"generic-rv32"}, FK_NONE, {""})
 PROC(GENERIC_RV64, {"generic-rv64"}, FK_64BIT, {""})
 PROC(ROCKET_RV32, {"rocket-rv32"}, FK_NONE, {""})
 PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {""})
 PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""})
 PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""})
+PROC(SIFIVE_E20, {"sifive-e20"}, FK_NONE, {"rv32imc"})
 PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
 PROC(SIFIVE_S51, {"sifive-s51"}, FK_64BIT, {"rv64imac"})
 PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
 PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})
 PROC(SIFIVE_U74, {"sifive-u74"}, FK_64BIT, {"rv64gc"})
 
 #undef PROC

llvm/lib/Target/RISCV/RISCV.td

 def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
 
 def : ProcessorModel<"rocket-rv32", RocketModel, []>;
 def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>;
 
 def : ProcessorModel<"sifive-7-rv32", SiFive7Model, []>;
 def : ProcessorModel<"sifive-7-rv64", SiFive7Model, [Feature64Bit]>;
 
+def : ProcessorModel<"sifive-e20", RocketModel, [FeatureStdExtM,
+                                                 FeatureStdExtC]>;
+
 def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM,
                                                  FeatureStdExtA,
                                                  FeatureStdExtC]>;
 
 def : ProcessorModel<"sifive-s51", RocketModel, [Feature64Bit,
                                                  FeatureStdExtM,
                                                  FeatureStdExtA,
                                                  FeatureStdExtC]>;
 
 def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
                                                  FeatureStdExtM,
                                                  FeatureStdExtA,
                                                  FeatureStdExtF,
                                                  FeatureStdExtD,
                                                  FeatureStdExtC]>;
 
 def : ProcessorModel<"sifive-e76", SiFive7Model, [FeatureStdExtM,
                                                   FeatureStdExtA,
                                                   FeatureStdExtF,
                                                   FeatureStdExtC]>;
 
 def : ProcessorModel<"sifive-u74", SiFive7Model, [Feature64Bit,
                                                   FeatureStdExtM,