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[RISCV] Add SiFive cores E and S series
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Authored by apivovarov on Sep 3 2021, 2:20 PM.

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apivovarov created this revision.Sep 3 2021, 2:20 PM
apivovarov requested review of this revision.Sep 3 2021, 2:20 PM
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apivovarov edited the summary of this revision. (Show Details)Sep 3 2021, 2:21 PM

Are you planning to add more CPUs? I think I'd be willing to accept them all as one patch instead of one small patch for each CPU.

Another missing combination is:

  • e24 and e34 (rocket, rv32imafc)

I can also add several cores which are similar to existing cores:

  • e21 (same as existing e31 - rocket, rv32imac)
  • s21 (same as existing s51 - rocket, rv64imac)
  • s54 (same as existing u54 - rocket, rv64imafdc)
  • s76 (same as existing u74 - SiFive7, rv64imafdc)

To match gcc cores definition - https://github.com/gcc-mirror/gcc/blob/master/gcc/config/riscv/riscv-cores.def#L34

apivovarov updated this revision to Diff 370683.Sep 3 2021, 5:11 PM
apivovarov retitled this revision from [RISCV] Add SiFive core E20 to [RISCV] Add SiFive cores E and S series.
apivovarov edited the summary of this revision. (Show Details)

Added SiFive cores E20, E21, E24, E34, S21, S54 and S76

craig.topper added inline comments.Sep 3 2021, 5:20 PM
llvm/include/llvm/Support/RISCVTargetParser.def
24

Should SIFIVE_E34 be SIFIVE_E24?

31

Should SIFIVE_U74 be SIFIVE_S76?

llvm/lib/Target/RISCV/RISCV.td
279

Can we sort these by leading digit, then by letter? That will keep most of the SiFive7Models together.

craig.topper added inline comments.Sep 3 2021, 5:31 PM
llvm/include/llvm/Support/RISCVTargetParser.def
24

This duplication should fail the build I think?

apivovarov marked 4 inline comments as done.Sep 3 2021, 6:28 PM
apivovarov added inline comments.
llvm/lib/Target/RISCV/RISCV.td
279

Well, it is sorted by core_type + number in all other places in LLVM codebase (including error messages). GCC also sorts them as E-S-U. As well as sifive.com

craig.topper added inline comments.Sep 3 2021, 6:47 PM
clang/test/Misc/target-invalid-cpu-note.c
199

Why 2 spaces after commas here?

llvm/lib/Target/RISCV/RISCV.td
279

Ok. I was basing that request on our internal codebase where we have them sorted the other way. But it doesn't matter a lot to me.

apivovarov updated this revision to Diff 370691.Sep 3 2021, 7:39 PM
apivovarov marked an inline comment as done.

main branch is unstable. pulling the hot fixes again....

apivovarov updated this revision to Diff 370692.Sep 3 2021, 7:42 PM

fix double space issue. Fri...

apivovarov marked an inline comment as done.Sep 3 2021, 7:50 PM

Craig, I fixed all of the issue on Fri. Could you look at the patch again? Thank you

This revision is now accepted and ready to land.Sep 8 2021, 10:39 PM
This revision was automatically updated to reflect the committed changes.