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[RISCV] Use DIVUW/REMUW/DIVW instructions for i8/i16/i32 udiv/urem/sdiv when LHS is constant.
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Authored by craig.topper on Jul 10 2021, 6:26 PM.

Details

Summary

We don't really have optimizations for division with a constant
LHS. If we don't use a W instruction we end up needing to sign
or zero extend the RHS to use the 64-bit instruction.

I had to sign_extend i32 constants on the LHS instead of using
any_extend which becomes zero_extend. If we don't do this, constants
that were originally negative become harder to materialize. I think
this problem exists for more of our W instruction cases. For example
(i32 (shl -1, X)), but we don't have lit tests. I'll work on that
as a follow up.

I also left a FIXME for enabling W instruction for RHS constants
under -Oz.

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Event Timeline

craig.topper created this revision.Jul 10 2021, 6:26 PM
craig.topper requested review of this revision.Jul 10 2021, 6:26 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 10 2021, 6:26 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
luismarques accepted this revision.Jul 13 2021, 1:55 AM

LGTM.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp
4876

Nit: missing words?

This revision is now accepted and ready to land.Jul 13 2021, 1:55 AM
This revision was landed with ongoing or failed builds.Jul 13 2021, 10:34 AM
This revision was automatically updated to reflect the committed changes.