[AArch64][SME] Add system registers and related instructions

[c-rhodes]

Summary

This patch adds the new system registers introduced in SME:

• ID_AA64SMFR0_EL1 (ro) SME feature identifier.
• SMCR_ELx (r/w) streaming mode control register for configuring effective SVE Streaming SVE Vector length when the PE is in Streaming SVE mode.
• SVCR (r/w) streaming vector control register, visible at all exception levels. Provides access to PSTATE.SM and PSTATE.ZA using MSR and MRS instructions.
• SMPRI_EL1 (r/w) streaming mode execution priority register.
• SMPRIMAP_EL2 (r/w) streaming mode priority mapping register.
• SMIDR_EL1 (ro) streaming mode identification register.
• TPIDR2_EL0 (r/w) for use by SME software to manage per-thread SME context.
• MPAMSM_EL1 (r/w) MPAM (v8.4) streaming mode register, for labelling memory accesses performed in streaming mode.

Also added in this patch are the SME mode change instructions.
Three MSR immediate instructions are implemented to set or clear
PSTATE.SM, PSTATE.ZA, or both respectively:

• MSR SVCRSM, #<imm1>
• MSR SVCRZA, #<imm1>
• MSR SVCRSMZA, #<imm1>

The following smstart/smstop aliases are also implemented for
convenience:

smstart    -> MSR SVCRSMZA, #1
smstart sm -> MSR SVCRSM,   #1
smstart za -> MSR SVCRZA,   #1

smstop     -> MSR SVCRSMZA, #0
smstop sm  -> MSR SVCRSM,   #0
smstop za  -> MSR SVCRZA,   #0

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06

[c-rhodes]

Changes:

• Add tests for smstart/smstop.
• Fix matching of "smstart za", fixes issue described here: https://reviews.llvm.org/D105570#inline-1005832. The matching code that gets generated for aliases:
  • def : InstAlias<"smstart za", (MSRpstatesvcrImm1 0b010, 0b1)>;
  • def : InstAlias<"smstop za", (MSRpstatesvcrImm1 0b010, 0b0)>;

expectes MCK_MPR but za gets parsed as a literal. The fix is to return match in validateTargetOperandClass if MCK_MPR is expected and the token is za.

[david-arm]

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

1379

nit: Maybe simpler to just write "InvalidSVCR" here, since you've explicitly written SVCR in the ParserMethod too?

llvm/test/MC/AArch64/SME/smstart.s

17

Can we have a negative test where the keyword is not sm or za and make sure we do something sensible?

[c-rhodes]

Add diagnostics tests for smstart/smstop.

[c-rhodes]

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

1379

nit: Maybe simpler to just write "InvalidSVCR" here, since you've explicitly written SVCR in the ParserMethod too?

# Name for diagnostic type is consistent with the other operands so I've kept it as it.

[david-arm]

LGTM! Thanks for the negative tests. :)

[RKSimon]

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

6726

@c-rhodes Coverity is warning that ExpectedVal is still uninitialized when we break here - but should this be "return Match_InvalidOperand;" anyhow?

[c-rhodes]

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

6726

@c-rhodes Coverity is warning that ExpectedVal is still uninitialized when we break here - but should this be "return Match_InvalidOperand;" anyhow?

Apologies for late reply, it should, thanks for spotting and fixing!

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

class MatrixTileListOperand<string RC, int EltSize, dag ops> : Operand<i32> {
   let MIOperandInfo = ops;
 }
 
 def MatrixTileList8  : MatrixTileListOperand<"MPR8",   8, (ops MPR8)>;
 def MatrixTileList16 : MatrixTileListOperand<"MPR16", 16, (ops MPR16)>;
 def MatrixTileList32 : MatrixTileListOperand<"MPR32", 32, (ops MPR32)>;
 def MatrixTileList64 : MatrixTileListOperand<"MPR64", 64, (ops MPR64)>;
 
+
+def SVCROperand : AsmOperandClass {
+  let Name = "SVCR";
+  let ParserMethod = "tryParseSVCR";
+  let DiagnosticType = "Invalid" # Name;
+}
+
+def svcr_op : Operand<i32> {
+  let ParserMatchClass = SVCROperand;
+  let PrintMethod = "printSVCROp";
+  let DecoderMethod = "DecodeSVCROp";
+  let MCOperandPredicate = [{
+    if (!MCOp.isImm())
+      return false;
+    return AArch64SVCR::lookupSVCRByEncoding(MCOp.getImm()) != nullptr;
+  }];
+}
+
 def MatrixIndexGPR32_12_15 : RegisterClass<"AArch64", [i32], 32, (sequence "W%u", 12, 15)>;
 def MatrixIndexGPR32Op12_15 : RegisterOperand<MatrixIndexGPR32_12_15> {
   let EncoderMethod = "encodeMatrixIndexGPR32";
 }

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

 defm EXTRACT_ZPMXI : sme_tile_to_vector<"mova">;
 
 //===----------------------------------------------------------------------===//
 // Zero instruction
 //===----------------------------------------------------------------------===//
 
 defm ZERO_M : sme_zero<"zero">;
 
+//===----------------------------------------------------------------------===//
+// Mode selection and state access instructions
+//===----------------------------------------------------------------------===//
+
+// SME defines three pstate fields to set or clear PSTATE.SM, PSTATE.ZA, or
+// both fields:
+//
+//   MSR SVCRSM, #<imm1>
+//   MSR SVCRZA, #<imm1>
+//   MSR SVCRSMZA, #<imm1>
+//
+// It's tricky to using the existing pstate operand defined in
+// AArch64SystemOperands.td since it only encodes 5 bits including op1;op2,
+// when these fields are also encoded in CRm[3:1].
+class MSRpstatesvcrImm0_1
+  : PstateWriteSimple<(ins svcr_op:$pstatefield, imm0_1:$imm), "msr",
+                      "\t$pstatefield, $imm">,
+    Sched<[WriteSys]> {
+  bits<3> pstatefield;
+  bit imm;
+  let Inst{18-16} = 0b011; // op1
+  let Inst{11-9} = pstatefield;
+  let Inst{8} = imm;
+  let Inst{7-5} = 0b011; // op2
+}
+
+def MSRpstatesvcrImm1 : MSRpstatesvcrImm0_1;
+def : InstAlias<"smstart",    (MSRpstatesvcrImm1 0b011, 0b1)>;
+def : InstAlias<"smstart sm", (MSRpstatesvcrImm1 0b001, 0b1)>;
+def : InstAlias<"smstart za", (MSRpstatesvcrImm1 0b010, 0b1)>;
+
+def : InstAlias<"smstop",     (MSRpstatesvcrImm1 0b011, 0b0)>;
+def : InstAlias<"smstop sm",  (MSRpstatesvcrImm1 0b001, 0b0)>;
+def : InstAlias<"smstop za",  (MSRpstatesvcrImm1 0b010, 0b0)>;
+
 } // End let Predicates = [HasSME]

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 // v8.5a Spectre Mitigation
 let Requires = [{ {AArch64::FeatureSSBS} }] in
 def : PState<"SSBS",    0b11001>;
 // v8.5a Memory Tagging Extension
 let Requires = [{ {AArch64::FeatureMTE} }] in
 def : PState<"TCO",     0b11100>;
 
 //===----------------------------------------------------------------------===//
+// SVCR instruction options.
+//===----------------------------------------------------------------------===//
+
+class SVCR<string name, bits<3> encoding> : SearchableTable {
+  let SearchableFields = ["Name", "Encoding"];
+  let EnumValueField = "Encoding";
+
+  string Name = name;
+  bits<3> Encoding;
+  let Encoding = encoding;
+  code Requires = [{ {} }];
+}
+
+let Requires = [{ {AArch64::FeatureSME} }] in {
+def : SVCR<"SVCRSM",   0b001>;
+def : SVCR<"SVCRZA",   0b010>;
+def : SVCR<"SVCRSMZA", 0b011>;
+}
+
+//===----------------------------------------------------------------------===//
 // PSB instruction options.
 //===----------------------------------------------------------------------===//
 
 class PSB<string name, bits<5> encoding> : SearchableTable {
   let SearchableFields = ["Name", "Encoding"];
   let EnumValueField = "Encoding";
 
   string Name = name;

 
 // v9a Realm Management Extension registers
 let Requires = [{ {AArch64::FeatureRME} }] in {
 def : RWSysReg<"MFAR_EL3",  0b11, 0b110, 0b0110, 0b0000, 0b101>;
 def : RWSysReg<"GPCCR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b110>;
 def : RWSysReg<"GPTBR_EL3", 0b11, 0b110, 0b0010, 0b0001, 0b100>;
 }
 
+// v9-a Scalable Matrix Extension (SME) registers
+//                                 Op0   Op1    CRn     CRm     Op2
+let Requires = [{ {AArch64::FeatureSME} }] in {
+def : ROSysReg<"ID_AA64SMFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b101>;
+}
+
 //===----------------------
 // Write-only regs
 //===----------------------
 
 //                                 Op0    Op1     CRn     CRm    Op2
 def : WOSysReg<"DBGDTRTX_EL0",       0b10, 0b011, 0b0000, 0b0101, 0b000>;
 def : WOSysReg<"OSLAR_EL1",          0b10, 0b000, 0b0001, 0b0000, 0b100>;
 def : WOSysReg<"PMSWINC_EL0",        0b11, 0b011, 0b1001, 0b1100, 0b100>;

 // Statistical Profiling Extension system register
 let Requires = [{ {AArch64::FeatureSPE_EEF} }] in
 def : RWSysReg<"PMSNEVFR_EL1",      0b11, 0b000, 0b1001, 0b1001, 0b001>;
 
 // Cyclone specific system registers
 //                                 Op0    Op1     CRn     CRm    Op2
 let Requires = [{ {AArch64::ProcAppleA7} }] in
 def : RWSysReg<"CPM_IOACC_CTL_EL3", 0b11, 0b111, 0b1111, 0b0010, 0b000>;
+
+// Scalable Matrix Extension (SME)
+//                                 Op0   Op1    CRn     CRm     Op2
+let Requires = [{ {AArch64::FeatureSME} }] in {
+def : RWSysReg<"SMCR_EL1",         0b11, 0b000, 0b0001, 0b0010, 0b110>;
+def : RWSysReg<"SMCR_EL2",         0b11, 0b100, 0b0001, 0b0010, 0b110>;
+def : RWSysReg<"SMCR_EL3",         0b11, 0b110, 0b0001, 0b0010, 0b110>;
+def : RWSysReg<"SMCR_EL12",        0b11, 0b101, 0b0001, 0b0010, 0b110>;
+def : RWSysReg<"SVCR",             0b11, 0b011, 0b0100, 0b0010, 0b010>;
+def : RWSysReg<"SMPRI_EL1",        0b11, 0b000, 0b0001, 0b0010, 0b100>;
+def : RWSysReg<"SMPRIMAP_EL2",     0b11, 0b100, 0b0001, 0b0010, 0b101>;
+def : ROSysReg<"SMIDR_EL1",        0b11, 0b001, 0b0000, 0b0000, 0b110>;
+def : RWSysReg<"TPIDR2_EL0",       0b11, 0b011, 0b1101, 0b0000, 0b101>;
+} // HasSME
+
+// v8.4a MPAM and SME registers
+//                              Op0   Op1    CRn     CRm     Op2
+let Requires = [{ {AArch64::FeatureMPAM, AArch64::FeatureSME} }] in {
+def : RWSysReg<"MPAMSM_EL1",    0b11, 0b000, 0b1010, 0b0101, 0b011>;
+} // HasMPAM, HasSME

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

 #include "AArch64GenAsmMatcher.inc"
 
   /// }
 
   OperandMatchResultTy tryParseScalarRegister(unsigned &Reg);
   OperandMatchResultTy tryParseVectorRegister(unsigned &Reg, StringRef &Kind,
                                               RegKind MatchKind);
   OperandMatchResultTy tryParseMatrixRegister(OperandVector &Operands);
+  OperandMatchResultTy tryParseSVCR(OperandVector &Operands);
   OperandMatchResultTy tryParseOptionalShiftExtend(OperandVector &Operands);
   OperandMatchResultTy tryParseBarrierOperand(OperandVector &Operands);
   OperandMatchResultTy tryParseBarriernXSOperand(OperandVector &Operands);
   OperandMatchResultTy tryParseMRSSystemRegister(OperandVector &Operands);
   OperandMatchResultTy tryParseSysReg(OperandVector &Operands);
   OperandMatchResultTy tryParseSysCROperand(OperandVector &Operands);
   template <bool IsSVEPrefetch = false>
   OperandMatchResultTy tryParsePrefetch(OperandVector &Operands);

 private:
   enum KindTy {
     k_Immediate,
     k_ShiftedImm,
     k_CondCode,
     k_Register,
     k_MatrixRegister,
     k_MatrixTileList,
+    k_SVCR,
     k_VectorList,
     k_VectorIndex,
     k_Token,
     k_SysReg,
     k_SysCR,
     k_Prefetch,
     k_ShiftExtend,
     k_FPImm,
struct MatrixRegOp {
     MatrixKind Kind;
   };
 
   struct MatrixTileListOp {
     unsigned RegMask = 0;
     unsigned ElementWidth;
   };
 
+  struct SVCROp {
+    const char *Data;
+    unsigned Length;
+    unsigned PStateField;
+  };
+
   struct VectorListOp {
     unsigned RegNum;
     unsigned Count;
     unsigned NumElements;
     unsigned ElementWidth;
     RegKind  RegisterKind;
   };
 
struct BTIHintOp {
     unsigned Val;
   };
 
   union {
     struct TokOp Tok;
     struct RegOp Reg;
     struct MatrixRegOp MatrixReg;
     struct MatrixTileListOp MatrixTileList;
+    struct SVCROp SVCR;
     struct VectorListOp VectorList;
     struct VectorIndexOp VectorIndex;
     struct ImmOp Imm;
     struct ShiftedImmOp ShiftedImm;
     struct CondCodeOp CondCode;
     struct FPImmOp FPImm;
     struct BarrierOp Barrier;
     struct SysRegOp SysReg;
case k_Register:
       Reg = o.Reg;
       break;
     case k_MatrixRegister:
       MatrixReg = o.MatrixReg;
       break;
     case k_MatrixTileList:
       MatrixTileList = o.MatrixTileList;
       break;
+    case k_SVCR:
+      SVCR = o.SVCR;
+      break;
     case k_VectorList:
       VectorList = o.VectorList;
       break;
     case k_VectorIndex:
       VectorIndex = o.VectorIndex;
       break;
     case k_SysReg:
       SysReg = o.SysReg;
unsigned getMatrixTileListRegMask() const {
     return MatrixTileList.RegMask;
   }
 
   unsigned getMatrixTileListElementWidth() const {
     assert(isMatrixTileList() && "Invalid access!");
     return MatrixTileList.ElementWidth;
   }
 
+  StringRef getSVCR() const {
+    assert(Kind == k_SVCR && "Invalid access!");
+    return StringRef(SVCR.Data, SVCR.Length);
+  }
+
   RegConstraintEqualityTy getRegEqualityTy() const {
     assert(Kind == k_Register && "Invalid access!");
     return Reg.EqualityTy;
   }
 
   unsigned getVectorListStart() const {
     assert(Kind == k_VectorList && "Invalid access!");
     return VectorList.RegNum;
return (SysReg.PStateField == AArch64PState::PAN ||
             SysReg.PStateField == AArch64PState::SSBS);
   }
 
   bool isSystemPStateFieldWithImm0_15() const {
     if (!isSysReg() || isSystemPStateFieldWithImm0_1()) return false;
     return SysReg.PStateField != -1U;
   }
 
+  bool isSVCR() const {
+    if (Kind != k_SVCR)
+      return false;
+    return SVCR.PStateField != -1U;
+  }
+
   bool isReg() const override {
     return Kind == k_Register;
   }
 
   bool isScalarReg() const {
     return Kind == k_Register && Reg.Kind == RegKind::Scalar;
   }
 

   }
 
   void addSystemPStateFieldWithImm0_1Operands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
 
     Inst.addOperand(MCOperand::createImm(SysReg.PStateField));
   }
 
+  void addSVCROperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+
+    Inst.addOperand(MCOperand::createImm(SVCR.PStateField));
+  }
+
   void addSystemPStateFieldWithImm0_15Operands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
 
     Inst.addOperand(MCOperand::createImm(SysReg.PStateField));
   }
 
   void addSysCROperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
CreateMatrixRegister(unsigned RegNum, unsigned ElementWidth, MatrixKind Kind,
     Op->MatrixReg.ElementWidth = ElementWidth;
     Op->MatrixReg.Kind = Kind;
     Op->StartLoc = S;
     Op->EndLoc = E;
     return Op;
   }
 
   static std::unique_ptr<AArch64Operand>
+  CreateSVCR(uint32_t PStateField, StringRef Str, SMLoc S, MCContext &Ctx) {
+    auto Op = std::make_unique<AArch64Operand>(k_SVCR, Ctx);
+    Op->SVCR.PStateField = PStateField;
+    Op->SVCR.Data = Str.data();
+    Op->SVCR.Length = Str.size();
+    Op->StartLoc = S;
+    Op->EndLoc = S;
+    return Op;
+  }
+
+  static std::unique_ptr<AArch64Operand>
   CreateShiftExtend(AArch64_AM::ShiftExtendType ShOp, unsigned Val,
                     bool HasExplicitAmount, SMLoc S, SMLoc E, MCContext &Ctx) {
     auto Op = std::make_unique<AArch64Operand>(k_ShiftExtend, Ctx);
     Op->ShiftExtend.Type = ShOp;
     Op->ShiftExtend.Amount = Val;
     Op->ShiftExtend.HasExplicitAmount = HasExplicitAmount;
     Op->StartLoc = S;
     Op->EndLoc = E;
void AArch64Operand::print(raw_ostream &OS) const {
   case k_MatrixTileList: {
     OS << "<matrixlist ";
     unsigned RegMask = getMatrixTileListRegMask();
     unsigned MaxBits = 8;
     for (unsigned I = MaxBits; I > 0; --I)
       OS << ((RegMask & (1 << (I - 1))) >> (I - 1));
     break;
   }
+  case k_SVCR: {
+    OS << getSVCR();
+    break;
+  }
   case k_Register:
     OS << "<register " << getReg() << ">";
     if (!getShiftExtendAmount() && !hasShiftExtendAmount())
       break;
     LLVM_FALLTHROUGH;
   case k_ShiftExtend:
     OS << "<" << AArch64_AM::getShiftExtendName(getShiftExtendType()) << " #"
        << getShiftExtendAmount();
bool AArch64AsmParser::parseCondCode(OperandVector &Operands,
   }
 
   Operands.push_back(
       AArch64Operand::CreateCondCode(CC, S, getLoc(), getContext()));
   return false;
 }
 
 OperandMatchResultTy
+AArch64AsmParser::tryParseSVCR(OperandVector &Operands) {
+  MCAsmParser &Parser = getParser();
+  const AsmToken &Tok = Parser.getTok();
+  SMLoc S = getLoc();
+
+  if (Tok.isNot(AsmToken::Identifier)) {
+    TokError("invalid operand for instruction");
+    return MatchOperand_ParseFail;
+  }
+
+  unsigned PStateImm = -1;
+  const auto *SVCR = AArch64SVCR::lookupSVCRByName(Tok.getString());
+  if (SVCR && SVCR->haveFeatures(getSTI().getFeatureBits()))
+    PStateImm = SVCR->Encoding;
+
+  Operands.push_back(
+      AArch64Operand::CreateSVCR(PStateImm, Tok.getString(), S, getContext()));
+  Parser.Lex(); // Eat identifier token.
+  return MatchOperand_Success;
+}
+
+OperandMatchResultTy
 AArch64AsmParser::tryParseMatrixRegister(OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
   const AsmToken &Tok = Parser.getTok();
   SMLoc S = getLoc();
 
   StringRef Name = Tok.getString();
 
   if (Name.equals_insensitive("za")) {

 OperandMatchResultTy
 AArch64AsmParser::tryParseSysReg(OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
   const AsmToken &Tok = Parser.getTok();
 
   if (Tok.isNot(AsmToken::Identifier))
     return MatchOperand_NoMatch;
 
+  if (AArch64SVCR::lookupSVCRByName(Tok.getString()))
+    return MatchOperand_NoMatch;
+
   int MRSReg, MSRReg;
   auto SysReg = AArch64SysReg::lookupSysRegByName(Tok.getString());
   if (SysReg && SysReg->haveFeatures(getSTI().getFeatureBits())) {
     MRSReg = SysReg->Readable ? SysReg->Encoding : -1;
     MSRReg = SysReg->Writeable ? SysReg->Encoding : -1;
   } else
     MRSReg = MSRReg = AArch64SysReg::parseGenericRegister(Tok.getString());
 
bool AArch64AsmParser::parseOptionalMulOperand(OperandVector &Operands) {
   return Error(getLoc(), "expected 'vl' or '#<imm>'");
 }
 
 bool AArch64AsmParser::parseKeywordOperand(OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
   auto Tok = Parser.getTok();
   if (Tok.isNot(AsmToken::Identifier))
     return true;
-  Operands.push_back(AArch64Operand::CreateToken(Tok.getString(), false,
-                                                 Tok.getLoc(), getContext()));
+
+  auto Keyword = Tok.getString();
+  Keyword = StringSwitch<StringRef>(Keyword.lower())
+                .Case("sm", "sm")
+                .Case("za", "za")
+                .Default(Keyword);
+  Operands.push_back(
+      AArch64Operand::CreateToken(Keyword, false, Tok.getLoc(), getContext()));
+
   Parser.Lex();
   return false;
 }
 
 /// parseOperand - Parse a arm instruction operand.  For now this parses the
 /// operand regardless of the mnemonic.
 bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
                                   bool invertCondCode) {
case AsmToken::Identifier: {
     if (!parseRegister(Operands))
       return false;
 
     // See if this is a "mul vl" decoration or "mul #<int>" operand used
     // by SVE instructions.
     if (!parseOptionalMulOperand(Operands))
       return false;
 
+    // If this is an "smstart" or "smstop" instruction, parse its special
+    // keyword operand as an identifier.
+    if (Mnemonic == "smstart" || Mnemonic == "smstop")
+      return parseKeywordOperand(Operands);
+
     // This could be an optional "shift" or "extend" operand.
     OperandMatchResultTy GotShift = tryParseOptionalShiftExtend(Operands);
     // We can only continue if no tokens were eaten.
     if (GotShift != MatchOperand_NoMatch)
       return GotShift;
 
     // If this is a two-word mnemonic, parse its special keyword
     // operand as an identifier.
case Match_InvalidSVEIndexRange0_7:
     return Error(Loc, "vector lane must be an integer in range [0, 7].");
   case Match_InvalidSVEIndexRange0_3:
     return Error(Loc, "vector lane must be an integer in range [0, 3].");
   case Match_InvalidLabel:
     return Error(Loc, "expected label or encodable integer pc offset");
   case Match_MRS:
     return Error(Loc, "expected readable system register");
   case Match_MSR:
+  case Match_InvalidSVCR:
     return Error(Loc, "expected writable system register or pstate");
   case Match_InvalidComplexRotationEven:
     return Error(Loc, "complex rotation must be 0, 90, 180 or 270.");
   case Match_InvalidComplexRotationOdd:
     return Error(Loc, "complex rotation must be 90 or 270.");
   case Match_MnemonicFail: {
     std::string Suggestion = AArch64MnemonicSpellCheck(
         ((AArch64Operand &)*Operands[0]).getToken(),
bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidMatrixTileVectorH32:
   case Match_InvalidMatrixTileVectorH64:
   case Match_InvalidMatrixTileVectorH128:
   case Match_InvalidMatrixTileVectorV8:
   case Match_InvalidMatrixTileVectorV16:
   case Match_InvalidMatrixTileVectorV32:
   case Match_InvalidMatrixTileVectorV64:
   case Match_InvalidMatrixTileVectorV128:
+  case Match_InvalidSVCR:
   case Match_MSR:
   case Match_MRS: {
     if (ErrorInfo >= Operands.size())
       return Error(IDLoc, "too few operands for instruction", SMRange(IDLoc, (*Operands.back()).getEndLoc()));
     // Any time we get here, there's nothing fancy to do. Just get the
     // operand SMLoc and display the diagnostic.
     SMLoc ErrorLoc = ((AArch64Operand &)*Operands[ErrorInfo]).getStartLoc();
     if (ErrorLoc == SMLoc())
case MCK__HASH_6:
     ExpectedVal = 6;
     break;
   case MCK__HASH_64:
     ExpectedVal = 64;
     break;
   case MCK__HASH_8:
     ExpectedVal = 8;
     break;
+  case MCK_MPR:
+    // If the Kind is a token for the MPR register class which has the "za"
+    // register (SME accumulator array), check if the asm is a literal "za"
+    // token. This is for the "smstart za" alias that defines the register
+    // as a literal token.
+    if (Op.isTokenEqual("za"))
+      return Match_Success;
+    break;
   }
   if (!Op.isImm())
     return Match_InvalidOperand;
   const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
   if (!CE)
     return Match_InvalidOperand;
   if (CE->getValue() == ExpectedVal)
     return Match_Success;

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

 template<int Bits>
 static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm,
                                uint64_t Address, const void *Decoder);
 template <int ElementWidth>
 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm,
                                      uint64_t Addr, const void *Decoder);
 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
                                        uint64_t Addr, const void *Decoder);
+static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
+                                 const void *Decoder);
 
 static bool Check(DecodeStatus &Out, DecodeStatus In) {
   switch (In) {
     case MCDisassembler::Success:
       // Out stays the same.
       return true;
     case MCDisassembler::SoftFail:
       Out = In;

 }
 
 // Decode uimm4 ranged from 1-16.
 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
                                        uint64_t Addr, const void *Decoder) {
   Inst.addOperand(MCOperand::createImm(Imm + 1));
   return Success;
 }
+
+static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
+                                 const void *Decoder) {
+  if (AArch64SVCR::lookupSVCRByEncoding(Imm)) {
+    Inst.addOperand(MCOperand::createImm(Imm));
+    return Success;
+  }
+  return Fail;
+}

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.h

protected:
   template <bool IsVertical>
   void printMatrixTileVector(const MCInst *MI, unsigned OpNum,
                              const MCSubtargetInfo &STI, raw_ostream &O);
   void printMatrixTile(const MCInst *MI, unsigned OpNum,
                        const MCSubtargetInfo &STI, raw_ostream &O);
   template <int EltSize>
   void printMatrix(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
                    raw_ostream &O);
+  void printSVCROp(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI,
+                   raw_ostream &O);
   template <char = 0>
   void printSVERegOp(const MCInst *MI, unsigned OpNum,
                     const MCSubtargetInfo &STI, raw_ostream &O);
   void printGPR64as32(const MCInst *MI, unsigned OpNum,
                       const MCSubtargetInfo &STI, raw_ostream &O);
   void printGPR64x8(const MCInst *MI, unsigned OpNum,
                     const MCSubtargetInfo &STI, raw_ostream &O);
   template <int Width>

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

 void AArch64InstPrinter::printMatrixTile(const MCInst *MI, unsigned OpNum,
                                          const MCSubtargetInfo &STI,
                                          raw_ostream &O) {
   const MCOperand &RegOp = MI->getOperand(OpNum);
   assert(RegOp.isReg() && "Unexpected operand type!");
   O << getRegisterName(RegOp.getReg());
 }
 
+void AArch64InstPrinter::printSVCROp(const MCInst *MI, unsigned OpNum,
+                                     const MCSubtargetInfo &STI,
+                                     raw_ostream &O) {
+  const MCOperand &MO = MI->getOperand(OpNum);
+  assert(MO.isImm() && "Unexpected operand type!");
+  unsigned svcrop = MO.getImm();
+  const auto *SVCR = AArch64SVCR::lookupSVCRByEncoding(svcrop);
+  assert(SVCR && "Unexpected SVCR operand!");
+  O << SVCR->Name;
+}
+
 void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
                                       const MCSubtargetInfo &STI,
                                       raw_ostream &O) {
   const MCOperand &Op = MI->getOperand(OpNo);
   if (Op.isReg()) {
     unsigned Reg = Op.getReg();
     O << getRegisterName(Reg);
   } else if (Op.isImm()) {

llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h

 struct SysAliasImm : SysAlias {
   uint16_t ImmValue;
   constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
       : SysAlias(N, E), ImmValue(I) {}
   constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F)
       : SysAlias(N, E, F), ImmValue(I) {}
 };
 
+namespace AArch64SVCR {
+  struct SVCR : SysAlias{
+    using SysAlias::SysAlias;
+  };
+  #define GET_SVCR_DECL
+  #include "AArch64GenSystemOperands.inc"
+}
+
 namespace AArch64AT{
   struct AT : SysAlias {
     using SysAlias::SysAlias;
   };
   #define GET_AT_DECL
   #include "AArch64GenSystemOperands.inc"
 }
 

llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp

 }
 
 namespace llvm {
   namespace AArch64TLBI {
 #define GET_TLBITable_IMPL
 #include "AArch64GenSystemOperands.inc"
   }
 }
+
+namespace llvm {
+  namespace AArch64SVCR {
+#define GET_SVCR_IMPL
+#include "AArch64GenSystemOperands.inc"
+  }
+}

llvm/test/MC/AArch64/SME/smstart-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid keyword
+
+smstart foo
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smstart foo
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME/smstart.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+smstart
+// CHECK-INST: smstart
+// CHECK-ENCODING: [0x7f,0x47,0x03,0xd5]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 7f 47 03 d5   msr   S0_3_C4_C7_3, xzr
+
+smstart sm
+// CHECK-INST: smstart sm
+// CHECK-ENCODING: [0x7f,0x43,0x03,0xd5]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 7f 43 03 d5   msr   S0_3_C4_C3_3, xzr
+
+smstart za
+// CHECK-INST: smstart za
+// CHECK-ENCODING: [0x7f,0x45,0x03,0xd5]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 7f 45 03 d5   msr   S0_3_C4_C5_3, xzr
+
+smstart SM
+// CHECK-INST: smstart sm
+// CHECK-ENCODING: [0x7f,0x43,0x03,0xd5]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 7f 43 03 d5   msr   S0_3_C4_C3_3, xzr
+
+smstart ZA
+// CHECK-INST: smstart za
+// CHECK-ENCODING: [0x7f,0x45,0x03,0xd5]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 7f 45 03 d5   msr   S0_3_C4_C5_3, xzr

llvm/test/MC/AArch64/SME/smstop-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme 2>&1 < %s| FileCheck %s
+
+// ------------------------------------------------------------------------- //
+// Invalid keyword
+
+smstop foo
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: smstop foo
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME/smstop.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+smstop
+// CHECK-INST: smstop
+// CHECK-ENCODING: [0x7f,0x46,0x03,0xd5]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 7f 46 03 d5   msr   S0_3_C4_C6_3, xzr
+
+smstop sm
+// CHECK-INST: smstop sm
+// CHECK-ENCODING: [0x7f,0x42,0x03,0xd5]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 7f 42 03 d5   msr   S0_3_C4_C2_3, xzr
+
+smstop za
+// CHECK-INST: smstop za
+// CHECK-ENCODING: [0x7f,0x44,0x03,0xd5]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 7f 44 03 d5   msr   S0_3_C4_C4_3, xzr
+
+smstop SM
+// CHECK-INST: smstop sm
+// CHECK-ENCODING: [0x7f,0x42,0x03,0xd5]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 7f 42 03 d5   msr   S0_3_C4_C2_3, xzr
+
+smstop ZA
+// CHECK-INST: smstop za
+// CHECK-ENCODING: [0x7f,0x44,0x03,0xd5]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 7f 44 03 d5   msr   S0_3_C4_C4_3, xzr

llvm/test/MC/AArch64/SME/system-regs-diagnostics.s

+// RUN: not llvm-mc -triple aarch64 -mattr=+sme -show-encoding < %s 2>&1 | FileCheck %s
+
+
+// --------------------------------------------------------------------------//
+// Check read-only
+
+msr ID_AA64SMFR0_EL1, x3
+// CHECK: error: expected writable system register or pstate
+// CHECK-NEXT: msr ID_AA64SMFR0_EL1, x3
+
+msr SMIDR_EL1, x3
+// CHECK: error: expected writable system register or pstate
+// CHECK-NEXT: msr SMIDR_EL1, x3
+
+// --------------------------------------------------------------------------//
+// Check MSR SVCR immediate is in range [0, 1]
+
+msr SVCRSM, #-1
+// CHECK: error: immediate must be an integer in range [0, 1].
+// CHECK-NEXT: msr SVCRSM, #-1
+
+msr SVCRZA, #2
+// CHECK: error: immediate must be an integer in range [0, 1].
+// CHECK-NEXT: msr SVCRZA, #2
+
+msr SVCRSMZA, #4
+// CHECK: error: immediate must be an integer in range [0, 1].
+// CHECK-NEXT: msr SVCRSMZA, #4

llvm/test/MC/AArch64/SME/system-regs-mpam.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme,+mpam < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+mpam < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme,+mpam < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme,+mpam - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme,+mpam < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme,+mpam < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme,+mpam < %s \
+// RUN:        | llvm-objdump -d --mattr=+mpam - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+// --------------------------------------------------------------------------//
+// read
+
+mrs x3, MPAMSM_EL1
+// CHECK-INST: mrs x3, MPAMSM_EL1
+// CHECK-ENCODING: [0x63,0xa5,0x38,0xd5]
+// CHECK-ERROR: expected readable system register
+// CHECK-UNKNOWN: 63 a5 38 d5   mrs   x3, S3_0_C10_C5_3
+
+// --------------------------------------------------------------------------//
+// write
+
+msr MPAMSM_EL1, x3
+// CHECK-INST: msr MPAMSM_EL1, x3
+// CHECK-ENCODING: [0x63,0xa5,0x18,0xd5]
+// CHECK-ERROR: expected writable system register or pstate
+// CHECK-UNKNOWN: 63 a5 18 d5   msr   S3_0_C10_C5_3, x3

llvm/test/MC/AArch64/SME/system-regs.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+// --------------------------------------------------------------------------//
+// read
+
+mrs x3, ID_AA64SMFR0_EL1
+// CHECK-INST: mrs x3, ID_AA64SMFR0_EL1
+// CHECK-ENCODING: [0xa3,0x04,0x38,0xd5]
+// CHECK-ERROR: expected readable system register
+// CHECK-UNKNOWN: a3 04 38 d5   mrs   x3, S3_0_C0_C4_5
+
+mrs x3, SMCR_EL1
+// CHECK-INST: mrs x3, SMCR_EL1
+// CHECK-ENCODING: [0xc3,0x12,0x38,0xd5]
+// CHECK-ERROR: expected readable system register
+// CHECK-UNKNOWN: c3 12 38 d5   mrs   x3, S3_0_C1_C2_6
+
+mrs x3, SMCR_EL2
+// CHECK-INST: mrs x3, SMCR_EL2
+// CHECK-ENCODING: [0xc3,0x12,0x3c,0xd5]
+// CHECK-ERROR: expected readable system register
+// CHECK-UNKNOWN: c3 12 3c d5   mrs   x3, S3_4_C1_C2_6
+
+mrs x3, SMCR_EL3
+// CHECK-INST: mrs x3, SMCR_EL3
+// CHECK-ENCODING: [0xc3,0x12,0x3e,0xd5]
+// CHECK-ERROR: expected readable system register
+// CHECK-UNKNOWN: c3 12 3e d5   mrs   x3, S3_6_C1_C2_6
+
+mrs x3, SMCR_EL12
+// CHECK-INST: mrs x3, SMCR_EL12
+// CHECK-ENCODING: [0xc3,0x12,0x3d,0xd5]
+// CHECK-ERROR: expected readable system register
+// CHECK-UNKNOWN: c3 12 3d d5   mrs   x3, S3_5_C1_C2_6
+
+mrs x3, SVCR
+// CHECK-INST: mrs x3, SVCR
+// CHECK-ENCODING: [0x43,0x42,0x3b,0xd5]
+// CHECK-ERROR: expected readable system register
+// CHECK-UNKNOWN: 43 42 3b d5   mrs   x3, S3_3_C4_C2_2
+
+mrs x3, SMPRI_EL1
+// CHECK-INST: mrs x3, SMPRI_EL1
+// CHECK-ENCODING: [0x83,0x12,0x38,0xd5]
+// CHECK-ERROR: expected readable system register
+// CHECK-UNKNOWN: 83 12 38 d5   mrs   x3, S3_0_C1_C2_4
+
+mrs x3, SMPRIMAP_EL2
+// CHECK-INST: mrs x3, SMPRIMAP_EL2
+// CHECK-ENCODING: [0xa3,0x12,0x3c,0xd5]
+// CHECK-ERROR: expected readable system register
+// CHECK-UNKNOWN: a3 12 3c d5   mrs   x3, S3_4_C1_C2_5
+
+mrs x3, SMIDR_EL1
+// CHECK-INST: mrs x3, SMIDR_EL1
+// CHECK-ENCODING: [0xc3,0x00,0x39,0xd5]
+// CHECK-ERROR: expected readable system register
+// CHECK-UNKNOWN: c3 00 39 d5   mrs   x3, S3_1_C0_C0_6
+
+mrs x3, TPIDR2_EL0
+// CHECK-INST: mrs x3, TPIDR2_EL0
+// CHECK-ENCODING: [0xa3,0xd0,0x3b,0xd5]
+// CHECK-ERROR: expected readable system register
+// CHECK-UNKNOWN: a3 d0 3b d5   mrs   x3, S3_3_C13_C0_5
+
+// --------------------------------------------------------------------------//
+// write
+
+msr SMCR_EL1, x3
+// CHECK-INST: msr SMCR_EL1, x3
+// CHECK-ENCODING: [0xc3,0x12,0x18,0xd5]
+// CHECK-ERROR: expected writable system register or pstate
+// CHECK-UNKNOWN: c3 12 18 d5   msr   S3_0_C1_C2_6, x3
+
+msr SMCR_EL2, x3
+// CHECK-INST: msr SMCR_EL2, x3
+// CHECK-ENCODING: [0xc3,0x12,0x1c,0xd5]
+// CHECK-ERROR: expected writable system register or pstate
+// CHECK-UNKNOWN: c3 12 1c d5   msr   S3_4_C1_C2_6, x3
+
+msr SMCR_EL3, x3
+// CHECK-INST: msr SMCR_EL3, x3
+// CHECK-ENCODING: [0xc3,0x12,0x1e,0xd5]
+// CHECK-ERROR: expected writable system register or pstate
+// CHECK-UNKNOWN: c3 12 1e d5   msr   S3_6_C1_C2_6, x3
+
+msr SMCR_EL12, x3
+// CHECK-INST: msr SMCR_EL12, x3
+// CHECK-ENCODING: [0xc3,0x12,0x1d,0xd5]
+// CHECK-ERROR: expected writable system register or pstate
+// CHECK-UNKNOWN: c3 12 1d d5   msr   S3_5_C1_C2_6, x3
+
+msr SVCR, x3
+// CHECK-INST: msr SVCR, x3
+// CHECK-ENCODING: [0x43,0x42,0x1b,0xd5]
+// CHECK-ERROR: expected writable system register or pstate
+// CHECK-UNKNOWN: 43 42 1b d5   msr   S3_3_C4_C2_2, x3
+
+msr SMPRI_EL1, x3
+// CHECK-INST: msr SMPRI_EL1, x3
+// CHECK-ENCODING: [0x83,0x12,0x18,0xd5]
+// CHECK-ERROR: expected writable system register or pstate
+// CHECK-UNKNOWN: 83 12 18 d5   msr   S3_0_C1_C2_4, x3
+
+msr SMPRIMAP_EL2, x3
+// CHECK-INST: msr SMPRIMAP_EL2, x3
+// CHECK-ENCODING: [0xa3,0x12,0x1c,0xd5]
+// CHECK-ERROR: expected writable system register or pstate
+// CHECK-UNKNOWN: a3 12 1c d5   msr   S3_4_C1_C2_5, x3
+
+msr SVCRSM, #0
+// CHECK-INST: smstop sm
+// CHECK-ENCODING: [0x7f,0x42,0x03,0xd5]
+// CHECK-ERROR: expected writable system register or pstate
+// CHECK-UNKNOWN: 7f 42 03 d5   msr   S0_3_C4_C2_3, xzr
+
+msr SVCRSM, #1
+// CHECK-INST: smstart
+// CHECK-ENCODING: [0x7f,0x43,0x03,0xd5]
+// CHECK-ERROR: expected writable system register or pstate
+// CHECK-UNKNOWN: 7f 43 03 d5   msr   S0_3_C4_C3_3, xzr
+
+msr SVCRZA, #0
+// CHECK-INST: smstop za
+// CHECK-ENCODING: [0x7f,0x44,0x03,0xd5]
+// CHECK-ERROR: expected writable system register or pstate
+// CHECK-UNKNOWN: 7f 44 03 d5   msr   S0_3_C4_C4_3, xzr
+
+msr SVCRZA, #1
+// CHECK-INST: smstart za
+// CHECK-ENCODING: [0x7f,0x45,0x03,0xd5]
+// CHECK-ERROR: expected writable system register or pstate
+// CHECK-UNKNOWN: 7f 45 03 d5   msr   S0_3_C4_C5_3, xzr
+
+msr SVCRSMZA, #0
+// CHECK-INST: smstop
+// CHECK-ENCODING: [0x7f,0x46,0x03,0xd5]
+// CHECK-ERROR: expected writable system register or pstate
+// CHECK-UNKNOWN: 7f 46 03 d5   msr   S0_3_C4_C6_3, xzr
+
+msr SVCRSMZA, #1
+// CHECK-INST: smstart
+// CHECK-ENCODING: [0x7f,0x47,0x03,0xd5]
+// CHECK-ERROR: expected writable system register or pstate
+// CHECK-UNKNOWN: 7f 47 03 d5   msr   S0_3_C4_C7_3, xzr
+
+msr TPIDR2_EL0, x3
+// CHECK-INST: msr TPIDR2_EL0, x3
+// CHECK-ENCODING: [0xa3,0xd0,0x1b,0xd5]
+// CHECK-ERROR: expected writable system register or pstate
+// CHECK-UNKNOWN: a3 d0 1b d5   msr   S3_3_C13_C0_5, x3