[RISCV] Teach RISCVMatInt about cases where it can use LUI+SLLI to replace LUI+ADDI+SLLI for large constants.

[craig.topper]

Summary

If we need to shift left anyway we might be able to take advantage
of LUI implicitly shifting its immediate left by 12 to cover part
of the shift. This allows us to use more bits of the LUI immediate
to avoid an ADDI.

I believe this is the same or similar to one of the optimizations
from D79492.

[craig.topper]

llvm/test/CodeGen/RISCV/add-before-shl.ll

60

As noted in D79492 this is a regression for the C extension as lui a1, 4095 isn't compressible, but the lui 1 and addiw -1 were.

The cost model used by isDesirableToCommuteWithShift doesn't understand compressed instructions.

llvm/test/CodeGen/RISCV/rv64zbp.ll

3621

This is a regression. We lose out on coincidental CSE of part of the materialization of two similar constants 0x00F000F000F000F0 and 0x0F000F000F000F00. They have the same number of 1s but are shifted 4 bits relative to each other.

[arcbbb]

LGTM

[craig.topper]

@luismarques were you able to find the change you were looking at to fix the add-before-shl.ll regression?

[luismarques]

In D105417#2874534, @craig.topper wrote:

@luismarques were you able to find the change you were looking at to fix the add-before-shl.ll regression?

I just checked that I indeed have a commit where that isn't an issue, but it's not a localized fix for that regression. I was computing the cost of instruction sequences and backing off if they were more "costly" (based on instruction count and length). I was working part-time these last two weeks, so I didn't get around to properly dig that work up, refresh it and share it, but I'll try to do it by ~Sunday.

[luismarques]

In D105417#2874534, @craig.topper wrote:

@luismarques were you able to find the change you were looking at to fix the add-before-shl.ll regression?

You can find it in D106318. If you find it useful just take it. Or let me know if you want me to elaborate more on some of the unexercised implementation details.

BTW, ignore my previous comment about it not being a localized fixed for the isDesirableToCommuteWithShift-related regression. When I wrote that I missed that (1) we did end up adopting a backtracking approach and that (2) the proposed cost function only needs to be used in getIntMatCost to address the regression, anyway.

[craig.topper]

Use portions of D106318. I added a new flag to the cost function so that the call site in RISCVTargetTransformInfo for immediate cost isn't affected. This new cost model only seems useful for comparing two sequences, but that's not what immediate cost is doing.

I eft out the optsize since that wasn't needed for the current regression.
And I left out the parts for choosing different alternatives for the same constant
as it wasn't directly related to the goal of this change either.

[craig.topper]

llvm/test/CodeGen/RISCV/add-before-shl.ll

5–6

I added new RVC RUN lines so we can see that the code with compression enabled isn't affected.

[luismarques]

You added RVC RUN lines to a test because you spotted an issue there *before* the changes were gated by HasRVC. The next time around, how will we detect such changes, without adding RVC RUN lines to more test files? Doesn't that mean that we should add RVC RUN lines in other potentially problematic test files (e.g. rv64zb*.ll)? Or are we confident that more targeted tests will always detect all such issues...?

Other than that, LGTM. Thanks.

llvm/test/CodeGen/RISCV/add-before-shl.ll

5–9

Nit: wrap before column 80.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h

 InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures);
 
 // Helper to estimate the number of instructions required to materialise the
 // given immediate value into a register. This estimate does not account for
 // `Val` possibly fitting into an immediate, and so may over-estimate.
 //
 // This will attempt to produce instructions to materialise `Val` as an
 // `Size`-bit immediate.
+//
+// If CompressionCost is true it will use a different cost calculation if RVC is
+// enabled. This should be used to compare two different sequences to determine
+// which is more compressible.
 int getIntMatCost(const APInt &Val, unsigned Size,
-                  const FeatureBitset &ActiveFeatures);
+                  const FeatureBitset &ActiveFeatures,
+                  bool CompressionCost = false);
 } // namespace RISCVMatInt
 } // namespace llvm
 #endif

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

 //===- RISCVMatInt.cpp - Immediate materialisation -------------*- C++ -*--===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCVMatInt.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
 #include "llvm/ADT/APInt.h"
 #include "llvm/Support/MathExtras.h"
 using namespace llvm;
 
+static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC) {
+  if (!HasRVC)
+    return Res.size();
+
+  int Cost = 0;
+  for (auto Instr : Res) {
+    bool Compressed;
+    switch (Instr.Opc) {
+    default: llvm_unreachable("Unexpected opcode");
+    case RISCV::SLLI:
+    case RISCV::SRLI:
+      Compressed = true;
+      break;
+    case RISCV::ADDI:
+    case RISCV::ADDIW:
+    case RISCV::LUI:
+      Compressed = isInt<6>(Instr.Imm);
+      break;
+    case RISCV::ADDUW:
+      Compressed = false;
+      break;
+    }
+    // Two RVC instructions take the same space as one RVI instruction, but
+    // can take longer to execute than the single RVI instruction. Thus, we
+    // consider that two RVC instruction are slightly more costly than one
+    // RVI instruction. For longer sequences of RVC instructions the space
+    // savings can be worth it, though. The costs below try to model that.
+    if (!Compressed)
+      Cost += 100; // Baseline cost of one RVI instruction: 100%.
+    else
+      Cost += 70; // 70% cost of baseline.
+  }
+  return Cost;
+}
+
 // Recursively generate a sequence for materializing an integer.
 static void generateInstSeqImpl(int64_t Val,
                                 const FeatureBitset &ActiveFeatures,
                                 RISCVMatInt::InstSeq &Res) {
   bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit];
 
   if (isInt<32>(Val)) {
     // Depending on the active bits in the immediate Value v, the following
static void generateInstSeqImpl(int64_t Val,
   // fits into 32 bits. The emission of the shifts and additions is subsequently
   // performed when the recursion returns.
 
   int64_t Lo12 = SignExtend64<12>(Val);
   int64_t Hi52 = ((uint64_t)Val + 0x800ull) >> 12;
   int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52);
   Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount);
 
+  // If the remaining bits don't fit in 12 bits, we might be able to reduce the
+  // shift amount in order to use LUI which will zero the lower 12 bits.
+  if (ShiftAmount > 12 && !isInt<12>(Hi52) && isInt<32>((uint64_t)Hi52 << 12)) {
+    // Reduce the shift amount and add zeros to the LSBs so it will match LUI.
+    ShiftAmount -= 12;
+    Hi52 = (uint64_t)Hi52 << 12;
+  }
+
   generateInstSeqImpl(Hi52, ActiveFeatures, Res);
 
   Res.push_back(RISCVMatInt::Inst(RISCV::SLLI, ShiftAmount));
   if (Lo12)
     Res.push_back(RISCVMatInt::Inst(RISCV::ADDI, Lo12));
 }
 
 namespace llvm {
if (LeadingZeros == 32 && ActiveFeatures[RISCV::FeatureExtZba]) {
       }
     }
   }
 
   return Res;
 }
 
 int getIntMatCost(const APInt &Val, unsigned Size,
-                  const FeatureBitset &ActiveFeatures) {
+                  const FeatureBitset &ActiveFeatures,
+                  bool CompressionCost) {
   bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit];
+  bool HasRVC = CompressionCost && ActiveFeatures[RISCV::FeatureStdExtC];
   int PlatRegSize = IsRV64 ? 64 : 32;
 
   // Split the constant into platform register sized chunks, and calculate cost
   // of each chunk.
   int Cost = 0;
   for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) {
     APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize);
     InstSeq MatSeq = generateInstSeq(Chunk.getSExtValue(), ActiveFeatures);
-    Cost += MatSeq.size();
+    Cost += getInstSeqCost(MatSeq, HasRVC);
   }
   return std::max(1, Cost);
 }
 } // namespace RISCVMatInt
 } // namespace llvm

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (C1 && C2) {
       // combine should be prevented.
       if (C1Int.getMinSignedBits() <= 64 &&
           isLegalAddImmediate(C1Int.getSExtValue()))
         return false;
 
       // Neither constant will fit into an immediate, so find materialisation
       // costs.
       int C1Cost = RISCVMatInt::getIntMatCost(C1Int, Ty.getSizeInBits(),
-                                              Subtarget.getFeatureBits());
+                                              Subtarget.getFeatureBits(),
+                                              /*CompressionCost*/true);
       int ShiftedC1Cost = RISCVMatInt::getIntMatCost(
-          ShiftedC1Int, Ty.getSizeInBits(), Subtarget.getFeatureBits());
+          ShiftedC1Int, Ty.getSizeInBits(), Subtarget.getFeatureBits(),
+          /*CompressionCost*/true);
 
       // Materialising `c1` is cheaper than materialising `c1 << c2`, so the
       // combine should be prevented.
       if (C1Cost < ShiftedC1Cost)
         return false;
     }
   }
   return true;

llvm/test/CodeGen/RISCV/add-before-shl.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs --riscv-no-aliases < %s \
 ; RUN:   | FileCheck -check-prefixes=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs --riscv-no-aliases < %s \
 ; RUN:   | FileCheck -check-prefixes=RV64I %s
 ; RUN: llc -mtriple=riscv32 -mattr=+c -verify-machineinstrs --riscv-no-aliases \
 ; RUN:   < %s | FileCheck -check-prefixes=RV32C %s
 ; RUN: llc -mtriple=riscv64 -mattr=+c -verify-machineinstrs --riscv-no-aliases \
 ; RUN:   < %s | FileCheck -check-prefixes=RV64C %s
 
 ; These test that constant adds are not moved after shifts by DAGCombine,
 ; if the constant is cheaper to materialise before it has been shifted.
 
 define signext i32 @add_small_const(i32 signext %a) nounwind {
 ; RV32I-LABEL: add_small_const:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a0, a0, 1

 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    lui a1, 65520
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    srai a0, a0, 16
 ; RV32I-NEXT:    jalr zero, 0(ra)
 ;
 ; RV64I-LABEL: add_large_const:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 1
-; RV64I-NEXT:    addiw a1, a1, -1
-; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    slli a0, a0, 48
+; RV64I-NEXT:    lui a1, 4095
+; RV64I-NEXT:    slli a1, a1, 36
+; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    srai a0, a0, 48
 ; RV64I-NEXT:    jalr zero, 0(ra)
 ;
 ; RV32C-LABEL: add_large_const:
 ; RV32C:       # %bb.0:
 ; RV32C-NEXT:    c.slli a0, 16
 ; RV32C-NEXT:    lui a1, 65520
 ; RV32C-NEXT:    c.add a0, a1

 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    lui a1, 524272
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    srai a0, a0, 16
 ; RV32I-NEXT:    jalr zero, 0(ra)
 ;
 ; RV64I-LABEL: add_huge_const:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 8
-; RV64I-NEXT:    addiw a1, a1, -1
-; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    slli a0, a0, 48
+; RV64I-NEXT:    lui a1, 32767
+; RV64I-NEXT:    slli a1, a1, 36
+; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    srai a0, a0, 48
 ; RV64I-NEXT:    jalr zero, 0(ra)
 ;
 ; RV32C-LABEL: add_huge_const:
 ; RV32C:       # %bb.0:
 ; RV32C-NEXT:    c.slli a0, 16
 ; RV32C-NEXT:    lui a1, 524272
 ; RV32C-NEXT:    c.add a0, a1

 ; RV64I-NEXT:    slli a0, a0, 3
 ; RV64I-NEXT:    addi a2, zero, 1
 ; RV64I-NEXT:    slli a2, a2, 51
 ; RV64I-NEXT:    add a1, a1, a2
 ; RV64I-NEXT:    jalr zero, 0(ra)
 ;
 ; RV32C-LABEL: add_wide_operand:
 ; RV32C:       # %bb.0:
-; RV32C-NEXT:    c.lw a2, 0(a1)
-; RV32C-NEXT:    c.lw a3, 4(a1)
-; RV32C-NEXT:    lw a6, 12(a1)
+; RV32C-NEXT:    c.lw a2, 4(a1)
+; RV32C-NEXT:    c.lw a3, 12(a1)
+; RV32C-NEXT:    c.lw a4, 0(a1)
 ; RV32C-NEXT:    c.lw a1, 8(a1)
-; RV32C-NEXT:    srli a5, a2, 29
-; RV32C-NEXT:    slli a4, a3, 3
-; RV32C-NEXT:    c.or a4, a5
-; RV32C-NEXT:    c.srli a3, 29
-; RV32C-NEXT:    slli a5, a1, 3
+; RV32C-NEXT:    c.lui a5, 16
+; RV32C-NEXT:    c.add a3, a5
+; RV32C-NEXT:    c.slli a3, 3
+; RV32C-NEXT:    srli a5, a1, 29
+; RV32C-NEXT:    or a6, a3, a5
+; RV32C-NEXT:    srli a5, a4, 29
+; RV32C-NEXT:    slli a3, a2, 3
 ; RV32C-NEXT:    c.or a3, a5
-; RV32C-NEXT:    c.srli a1, 29
-; RV32C-NEXT:    slli a5, a6, 3
-; RV32C-NEXT:    c.or a1, a5
-; RV32C-NEXT:    c.slli a2, 3
-; RV32C-NEXT:    lui a5, 128
-; RV32C-NEXT:    c.add a1, a5
+; RV32C-NEXT:    c.srli a2, 29
+; RV32C-NEXT:    c.slli a1, 3
+; RV32C-NEXT:    c.or a1, a2
+; RV32C-NEXT:    slli a2, a4, 3
 ; RV32C-NEXT:    c.sw a2, 0(a0)
-; RV32C-NEXT:    c.sw a3, 8(a0)
-; RV32C-NEXT:    c.sw a4, 4(a0)
-; RV32C-NEXT:    c.sw a1, 12(a0)
+; RV32C-NEXT:    c.sw a1, 8(a0)
+; RV32C-NEXT:    c.sw a3, 4(a0)
+; RV32C-NEXT:    sw a6, 12(a0)
 ; RV32C-NEXT:    c.jr ra
 ;
 ; RV64C-LABEL: add_wide_operand:
 ; RV64C:       # %bb.0:
 ; RV64C-NEXT:    srli a2, a0, 61
 ; RV64C-NEXT:    c.slli a1, 3
 ; RV64C-NEXT:    c.or a1, a2
 ; RV64C-NEXT:    c.slli a0, 3
 ; RV64C-NEXT:    c.li a2, 1
 ; RV64C-NEXT:    c.slli a2, 51
 ; RV64C-NEXT:    c.add a1, a2
 ; RV64C-NEXT:    c.jr ra
   %1 = add i128 %a, 5192296858534827628530496329220096
   %2 = shl i128 %1, 3
   ret i128 %2
 }

llvm/test/CodeGen/RISCV/double-mem.ll

 ; RV32IFD-NEXT:    fsd ft0, 8(sp)
 ; RV32IFD-NEXT:    lw a0, 8(sp)
 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fld_fsd_constant:
 ; RV64IFD:       # %bb.0:
-; RV64IFD-NEXT:    lui a1, 56
-; RV64IFD-NEXT:    addiw a1, a1, -1353
-; RV64IFD-NEXT:    slli a1, a1, 14
+; RV64IFD-NEXT:    lui a1, 228023
+; RV64IFD-NEXT:    slli a1, a1, 2
 ; RV64IFD-NEXT:    fld ft0, -273(a1)
 ; RV64IFD-NEXT:    fmv.d.x ft1, a0
 ; RV64IFD-NEXT:    fadd.d ft0, ft1, ft0
 ; RV64IFD-NEXT:    fmv.x.d a0, ft0
 ; RV64IFD-NEXT:    fsd ft0, -273(a1)
 ; RV64IFD-NEXT:    ret
   %1 = inttoptr i32 3735928559 to double*
   %2 = load volatile double, double* %1

llvm/test/CodeGen/RISCV/float-mem.ll

 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV32IF-NEXT:    fmv.x.w a0, ft0
 ; RV32IF-NEXT:    fsw ft0, -273(a1)
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: flw_fsw_constant:
 ; RV64IF:       # %bb.0:
-; RV64IF-NEXT:    lui a1, 56
-; RV64IF-NEXT:    addiw a1, a1, -1353
-; RV64IF-NEXT:    slli a1, a1, 14
+; RV64IF-NEXT:    lui a1, 228023
+; RV64IF-NEXT:    slli a1, a1, 2
 ; RV64IF-NEXT:    flw ft0, -273(a1)
 ; RV64IF-NEXT:    fmv.w.x ft1, a0
 ; RV64IF-NEXT:    fadd.s ft0, ft1, ft0
 ; RV64IF-NEXT:    fmv.x.w a0, ft0
 ; RV64IF-NEXT:    fsw ft0, -273(a1)
 ; RV64IF-NEXT:    ret
   %1 = inttoptr i32 3735928559 to float*
   %2 = load volatile float, float* %1

llvm/test/CodeGen/RISCV/half-mem.ll

 ; RV32IZFH-NEXT:    lui a0, 912092
 ; RV32IZFH-NEXT:    flh ft0, -273(a0)
 ; RV32IZFH-NEXT:    fadd.h fa0, fa0, ft0
 ; RV32IZFH-NEXT:    fsh fa0, -273(a0)
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: flh_fsh_constant:
 ; RV64IZFH:       # %bb.0:
-; RV64IZFH-NEXT:    lui a0, 56
-; RV64IZFH-NEXT:    addiw a0, a0, -1353
-; RV64IZFH-NEXT:    slli a0, a0, 14
+; RV64IZFH-NEXT:    lui a0, 228023
+; RV64IZFH-NEXT:    slli a0, a0, 2
 ; RV64IZFH-NEXT:    flh ft0, -273(a0)
 ; RV64IZFH-NEXT:    fadd.h fa0, fa0, ft0
 ; RV64IZFH-NEXT:    fsh fa0, -273(a0)
 ; RV64IZFH-NEXT:    ret
   %1 = inttoptr i32 3735928559 to half*
   %2 = load volatile half, half* %1
   %3 = fadd half %a, %2
   store half %3, half* %1

llvm/test/CodeGen/RISCV/imm.ll

 ; RV32I-LABEL: imm_left_shifted_lui_1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a0, 524290
 ; RV32I-NEXT:    mv a1, zero
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_left_shifted_lui_1:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a0, 64
-; RV64I-NEXT:    addiw a0, a0, 1
-; RV64I-NEXT:    slli a0, a0, 13
+; RV64I-NEXT:    lui a0, 262145
+; RV64I-NEXT:    slli a0, a0, 1
 ; RV64I-NEXT:    ret
   ret i64 2147491840 ; 0x8000_2000
 }
 
 define i64 @imm_left_shifted_lui_2() nounwind {
 ; RV32I-LABEL: imm_left_shifted_lui_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a0, 4
 ; RV32I-NEXT:    addi a1, zero, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_left_shifted_lui_2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a0, 64
-; RV64I-NEXT:    addiw a0, a0, 1
-; RV64I-NEXT:    slli a0, a0, 14
+; RV64I-NEXT:    lui a0, 262145
+; RV64I-NEXT:    slli a0, a0, 2
 ; RV64I-NEXT:    ret
   ret i64 4294983680 ; 0x1_0000_4000
 }
 
 define i64 @imm_left_shifted_lui_3() nounwind {
 ; RV32I-LABEL: imm_left_shifted_lui_3:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a0, 1
 ; RV32I-NEXT:    addi a1, a0, 1
 ; RV32I-NEXT:    mv a0, zero
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_left_shifted_lui_3:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addiw a0, a0, 1
-; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    lui a0, 4097
+; RV64I-NEXT:    slli a0, a0, 20
 ; RV64I-NEXT:    ret
   ret i64 17596481011712 ; 0x1001_0000_0000
 }
 
 ; Various cases where extraneous ADDIs can be inserted where a (right shifted)
 ; LUI suffices, or where multiple ADDIs can be used instead of a single LUI.
 
 define i64 @imm_right_shifted_lui_1() nounwind {

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a0, 1048575
 ; RV32I-NEXT:    addi a0, a0, 1
 ; RV32I-NEXT:    addi a1, zero, 255
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_right_shifted_lui_2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a0, 65536
-; RV64I-NEXT:    addiw a0, a0, -1
+; RV64I-NEXT:    lui a0, 1044481
 ; RV64I-NEXT:    slli a0, a0, 12
-; RV64I-NEXT:    addi a0, a0, 1
+; RV64I-NEXT:    srli a0, a0, 24
 ; RV64I-NEXT:    ret
   ret i64 1099511623681 ; 0xFF_FFFF_F001
 }
 
 ; We can materialize the upper bits with a single (shifted) LUI, but that option
 ; can be missed due to the lower bits, which aren't just 1s or just 0s.
 
 define i64 @imm_decoupled_lui_addi() nounwind {
 ; RV32I-LABEL: imm_decoupled_lui_addi:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a0, zero, -3
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_decoupled_lui_addi:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a0, 1
-; RV64I-NEXT:    addiw a0, a0, 1
-; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    lui a0, 4097
+; RV64I-NEXT:    slli a0, a0, 20
 ; RV64I-NEXT:    addi a0, a0, -3
 ; RV64I-NEXT:    ret
   ret i64 17596481011709 ; 0x1000_FFFF_FFFD
 }
 
 ; This constant can be materialized for RV64 with LUI+SRLI+XORI.
 
 define i64 @imm_end_xori_1() nounwind {

llvm/test/CodeGen/RISCV/rv64-large-stack.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s | FileCheck %s
 ;
 ; The test case check that RV64 could handle the stack adjustment offset exceed
 ; 32-bit.
 
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    addi sp, sp, -2032
 ; CHECK-NEXT:    sd ra, 2024(sp) # 8-byte Folded Spill
-; CHECK-NEXT:    lui a0, 95
-; CHECK-NEXT:    addiw a0, a0, 1505
-; CHECK-NEXT:    slli a0, a0, 13
+; CHECK-NEXT:    lui a0, 390625
+; CHECK-NEXT:    slli a0, a0, 1
 ; CHECK-NEXT:    addi a0, a0, -2000
 ; CHECK-NEXT:    sub sp, sp, a0
 ; CHECK-NEXT:    addi a0, sp, 16
 ; CHECK-NEXT:    call baz@plt
-; CHECK-NEXT:    lui a0, 95
-; CHECK-NEXT:    addiw a0, a0, 1505
-; CHECK-NEXT:    slli a0, a0, 13
+; CHECK-NEXT:    lui a0, 390625
+; CHECK-NEXT:    slli a0, a0, 1
 ; CHECK-NEXT:    addi a0, a0, -2000
 ; CHECK-NEXT:    add sp, sp, a0
 ; CHECK-NEXT:    ld ra, 2024(sp) # 8-byte Folded Reload
 ; CHECK-NEXT:    addi sp, sp, 2032
 ; CHECK-NEXT:    ret
 entry:
   %w = alloca [100000000 x { fp128, fp128 }], align 16
   %arraydecay = getelementptr inbounds [100000000 x { fp128, fp128 }], [100000000 x { fp128, fp128 }]* %w, i64 0, i64 0
   call void @baz({ fp128, fp128 }* nonnull %arraydecay)
   ret void
 }
 
 declare void @baz({ fp128, fp128 }*)

llvm/test/CodeGen/RISCV/rv64zbp.ll

; RV64IBP-NEXT:    ret
   %or = or i32 %rot, %a
   ret i32 %or
 }
 
 define i64 @gorc16_i64(i64 %a) nounwind {
 ; RV64I-LABEL: gorc16_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a0, 16
-; RV64I-NEXT:    lui a2, 1048560
-; RV64I-NEXT:    addiw a2, a2, 1
-; RV64I-NEXT:    slli a3, a2, 16
+; RV64I-NEXT:    lui a2, 983041
+; RV64I-NEXT:    slli a3, a2, 4
 ; RV64I-NEXT:    addi a3, a3, -1
 ; RV64I-NEXT:    slli a3, a3, 16
 ; RV64I-NEXT:    and a1, a1, a3
 ; RV64I-NEXT:    srli a3, a0, 16
-; RV64I-NEXT:    slli a2, a2, 32
+; RV64I-NEXT:    slli a2, a2, 20
 ; RV64I-NEXT:    addi a2, a2, -1
 ; RV64I-NEXT:    srli a2, a2, 16
 ; RV64I-NEXT:    and a2, a3, a2
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: gorc16_i64:
; RV64IBP-NEXT:    ret
   %or = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 16)
   ret i32 %or
 }
 
 define i64 @grev16_i64(i64 %a) nounwind {
 ; RV64I-LABEL: grev16_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a0, 16
-; RV64I-NEXT:    lui a2, 1048560
-; RV64I-NEXT:    addiw a2, a2, 1
-; RV64I-NEXT:    slli a3, a2, 16
+; RV64I-NEXT:    lui a2, 983041
+; RV64I-NEXT:    slli a3, a2, 4
 ; RV64I-NEXT:    addi a3, a3, -1
 ; RV64I-NEXT:    slli a3, a3, 16
 ; RV64I-NEXT:    and a1, a1, a3
 ; RV64I-NEXT:    srli a0, a0, 16
-; RV64I-NEXT:    slli a2, a2, 32
+; RV64I-NEXT:    slli a2, a2, 20
 ; RV64I-NEXT:    addi a2, a2, -1
 ; RV64I-NEXT:    srli a2, a2, 16
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: grev16_i64:
 ; RV64IB:       # %bb.0:

 ; RV64I-NEXT:    slli a1, a1, 12
 ; RV64I-NEXT:    addi a1, a1, 241
 ; RV64I-NEXT:    slli a1, a1, 12
 ; RV64I-NEXT:    addi a1, a1, -241
 ; RV64I-NEXT:    slli a1, a1, 14
 ; RV64I-NEXT:    addi a1, a1, 963
 ; RV64I-NEXT:    and a1, a0, a1
 ; RV64I-NEXT:    slli a2, a0, 2
-; RV64I-NEXT:    lui a3, 48
-; RV64I-NEXT:    addiw a3, a3, 771
-; RV64I-NEXT:    slli a3, a3, 16
+; RV64I-NEXT:    lui a3, 197379
+; RV64I-NEXT:    slli a3, a3, 4
 ; RV64I-NEXT:    addi a3, a3, 771
 ; RV64I-NEXT:    slli a4, a3, 16
 ; RV64I-NEXT:    addi a4, a4, 771
 ; RV64I-NEXT:    slli a4, a4, 12
 ; RV64I-NEXT:    addi a4, a4, 48
 ; RV64I-NEXT:    and a2, a2, a4
 ; RV64I-NEXT:    or a1, a1, a2
 ; RV64I-NEXT:    srli a0, a0, 2
; RV64IBP-NEXT:    ret
   %or = or i32 %and2, %and
   %or3 = or i32 %or, %and1
   ret i32 %or3
 }
 
 define i64 @shfl4_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: shfl4_i64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 1048560
-; RV64I-NEXT:    addiw a1, a1, 255
-; RV64I-NEXT:    slli a1, a1, 16
+; RV64I-NEXT:    lui a1, 983295
+; RV64I-NEXT:    slli a1, a1, 4
 ; RV64I-NEXT:    addi a1, a1, 255
 ; RV64I-NEXT:    slli a1, a1, 16
 ; RV64I-NEXT:    addi a1, a1, 255
 ; RV64I-NEXT:    slli a1, a1, 12
 ; RV64I-NEXT:    addi a1, a1, 15
 ; RV64I-NEXT:    and a1, a0, a1
 ; RV64I-NEXT:    slli a2, a0, 4
+; RV64I-NEXT:    lui a3, 983055
+; RV64I-NEXT:    slli a3, a3, 4
+; RV64I-NEXT:    addi a3, a3, 15
+; RV64I-NEXT:    slli a3, a3, 16
+; RV64I-NEXT:    addi a3, a3, 15
+; RV64I-NEXT:    slli a3, a3, 12
+; RV64I-NEXT:    srli a3, a3, 4
+; RV64I-NEXT:    and a2, a2, a3
+; RV64I-NEXT:    srli a0, a0, 4
 ; RV64I-NEXT:    lui a3, 240
 ; RV64I-NEXT:    addiw a3, a3, 15
 ; RV64I-NEXT:    slli a3, a3, 16
 ; RV64I-NEXT:    addi a3, a3, 15
-; RV64I-NEXT:    slli a4, a3, 12
-; RV64I-NEXT:    addi a4, a4, 1
-; RV64I-NEXT:    slli a4, a4, 12
-; RV64I-NEXT:    addi a4, a4, -256
-; RV64I-NEXT:    and a2, a2, a4
-; RV64I-NEXT:    srli a0, a0, 4
 ; RV64I-NEXT:    slli a3, a3, 20
 ; RV64I-NEXT:    addi a3, a3, 240
 ; RV64I-NEXT:    and a0, a0, a3
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: shfl4_i64:
; RV64IBP-NEXT:    ret
   %or = or i32 %and, %and2
   %or3 = or i32 %or, %and1
   ret i32 %or3
 }
 
 define i64 @shfl8_i64(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: shfl8_i64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    lui a1, 1048560
-; RV64I-NEXT:    addiw a1, a1, 1
-; RV64I-NEXT:    slli a1, a1, 16
+; RV64I-NEXT:    lui a1, 983041
+; RV64I-NEXT:    slli a1, a1, 4
 ; RV64I-NEXT:    addi a1, a1, -1
 ; RV64I-NEXT:    slli a1, a1, 24
 ; RV64I-NEXT:    addi a1, a1, 255
 ; RV64I-NEXT:    and a1, a0, a1
 ; RV64I-NEXT:    slli a2, a0, 8
 ; RV64I-NEXT:    addi a3, zero, 255
 ; RV64I-NEXT:    slli a4, a3, 32
 ; RV64I-NEXT:    addi a4, a4, 255

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, -1
 ; RV64I-NEXT:    slli a1, a1, 32
 ; RV64I-NEXT:    addi a1, a1, 1
 ; RV64I-NEXT:    slli a1, a1, 16
 ; RV64I-NEXT:    addi a1, a1, -1
 ; RV64I-NEXT:    and a1, a0, a1
 ; RV64I-NEXT:    slli a2, a0, 16
-; RV64I-NEXT:    lui a3, 16
-; RV64I-NEXT:    addiw a3, a3, -1
-; RV64I-NEXT:    slli a4, a3, 32
+; RV64I-NEXT:    lui a3, 65535
+; RV64I-NEXT:    slli a4, a3, 20
 ; RV64I-NEXT:    and a2, a2, a4
 ; RV64I-NEXT:    or a1, a2, a1
 ; RV64I-NEXT:    srli a0, a0, 16
-; RV64I-NEXT:    slli a2, a3, 16
+; RV64I-NEXT:    slli a2, a3, 4
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: shfl16:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    zip16 a0, a0
 ; RV64IB-NEXT:    ret

llvm/test/CodeGen/RISCV/rvv/constant-folding.ll

 ; RV32-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
 ; RV32-NEXT:    vnsrl.wi v8, v25, 0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: fixedlen:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
 ; RV64-NEXT:    vsrl.vi v25, v8, 16
-; RV64-NEXT:    lui a0, 32
-; RV64-NEXT:    addiw a0, a0, -1
-; RV64-NEXT:    slli a0, a0, 15
+; RV64-NEXT:    lui a0, 131071
+; RV64-NEXT:    slli a0, a0, 3
 ; RV64-NEXT:    vand.vx v25, v25, a0
 ; RV64-NEXT:    vsetvli zero, zero, e16, mf4, ta, mu
 ; RV64-NEXT:    vnsrl.wi v8, v25, 0
 ; RV64-NEXT:    ret
   %v41 = insertelement <2 x i32> undef, i32 16, i32 0
   %v42 = shufflevector <2 x i32> %v41, <2 x i32> undef, <2 x i32> zeroinitializer
   %v43 = lshr <2 x i32> %x, %v42
   %v44 = trunc <2 x i32> %v43 to <2 x i16>

llvm/test/CodeGen/RISCV/urem-lkk.ll

 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    addi sp, sp, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IM-LABEL: fold_urem_positive_even:
 ; RV64IM:       # %bb.0:
 ; RV64IM-NEXT:    slli a1, a0, 32
 ; RV64IM-NEXT:    srli a1, a1, 32
-; RV64IM-NEXT:    lui a2, 62
-; RV64IM-NEXT:    addiw a2, a2, -711
-; RV64IM-NEXT:    slli a2, a2, 14
+; RV64IM-NEXT:    lui a2, 253241
+; RV64IM-NEXT:    slli a2, a2, 2
 ; RV64IM-NEXT:    addi a2, a2, -61
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    srli a1, a1, 42
 ; RV64IM-NEXT:    addi a2, zero, 1060
 ; RV64IM-NEXT:    mul a1, a1, a2
 ; RV64IM-NEXT:    subw a0, a0, a1
 ; RV64IM-NEXT:    ret
   %1 = urem i32 %x, 1060

llvm/test/MC/RISCV/rv64i-aliases-valid.s

 # CHECK-EXPAND-NEXT: addi t4, t4, -947
 # CHECK-EXPAND-NEXT: slli t4, t4, 12
 # CHECK-EXPAND-NEXT: addi t4, t4, 1511
 # CHECK-EXPAND-NEXT: slli t4, t4, 13
 # CHECK-EXPAND-NEXT: addi t4, t4, -272
 li t4, 0x123456789abcdef0
 # CHECK-EXPAND: addi t5, zero, -1
 li t5, 0xFFFFFFFFFFFFFFFF
-# CHECK-EXPAND: lui t6, 64
-# CHECK-EXPAND-NEXT: addiw t6, t6, 1
-# CHECK-EXPAND-NEXT: slli t6, t6, 13
+# CHECK-EXPAND: lui t6, 262145
+# CHECK-EXPAND-NEXT: slli t6, t6, 1
 li t6, 0x80002000
-# CHECK-EXPAND: lui t0, 64
-# CHECK-EXPAND-NEXT: addiw t0, t0, 1
-# CHECK-EXPAND-NEXT: slli t0, t0, 14
+# CHECK-EXPAND: lui t0, 262145
+# CHECK-EXPAND-NEXT: slli t0, t0, 2
 li x5, 0x100004000
-# CHECK-EXPAND: lui t1, 1
-# CHECK-EXPAND-NEXT: addiw t1, t1, 1
-# CHECK-EXPAND-NEXT: slli t1, t1, 32
+# CHECK-EXPAND: lui t1, 4097
+# CHECK-EXPAND-NEXT: slli t1, t1, 20
 li x6, 0x100100000000
 # CHECK-EXPAND: lui t2, 983056
 # CHECK-EXPAND-NEXT: srli t2, t2, 16
 li x7, 0xFFFFFFFFF001
-# CHECK-EXPAND: lui s0, 65536
-# CHECK-EXPAND-NEXT: addiw s0, s0, -1
+# CHECK-EXPAND: lui s0, 1044481
 # CHECK-EXPAND-NEXT: slli s0, s0, 12
-# CHECK-EXPAND-NEXT: addi s0, s0, 1
+# CHECK-EXPAND-NEXT: srli s0, s0, 24
 li x8, 0xFFFFFFF001
-# CHECK-EXPAND: lui s1, 1
-# CHECK-EXPAND-NEXT: addiw s1, s1, 1
-# CHECK-EXPAND-NEXT: slli s1, s1, 32
+# CHECK-EXPAND: lui s1, 4097
+# CHECK-EXPAND-NEXT: slli s1, s1, 20
 # CHECK-EXPAND-NEXT: addi s1, s1, -3
 li x9, 0x1000FFFFFFFD
 # CHECK-EXPAND: addi a0, zero, -1
 # CHECK-EXPAND-NEXT: slli a0, a0, 36
 # CHECK-EXPAND-NEXT: addi a0, a0, 1
 # CHECK-EXPAND-NEXT: slli a0, a0, 25
 # CHECK-EXPAND-NEXT: addi a0, a0, -1
 li x10, 0xE000000001FFFFFF