[RISCV] Support machine constraint "S"

[MaskRay]

Summary

Similar to D46745, "S" represents an absolute symbolic operand, which
can be used to specify the access models, e.g.

extern int var;
void *addr_via_asm() {
  void *ret;
  asm("lui %0, %%hi(%1)\naddi %0,%0,%%lo(%1)" : "=r"(ret) : "S"(&var));
  return ret;
}

'S' is documented in trunk GCC: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101275

[jrtc27]

Hm, AArch64 handles ExternalSymbolSDNode too, but I don't see how you could ever end up with one...

llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll

8

These should be stripped

9

#1 doesn't exist

25

Label isn't needed

26

for consistency

54

Don't need the comment

55

Ditto

[MaskRay]

scrub labels/comments

llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll

25

Omitting the entry label is allowed but having a label is canonical. Without it %0 needs to be %1.

[jrtc27]

llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll

25

TIL

[MaskRay]

In D105254#2851889, @jrtc27 wrote:

Hm, AArch64 handles ExternalSymbolSDNode too, but I don't see how you could ever end up with one...

It can't and the code path is untested. I already deleted it from aarch64.

[luismarques]

Makes sense. Let's wait for the GCC Bugzilla feedback.

[luismarques]

In D105254#2852489, @luismarques wrote:

Makes sense. Let's wait for the GCC Bugzilla feedback.

With 'S' now documented on the GNU side, I think this can be merged.

Would we keep this constraint forever regardless of how discussions of [1] might evolve?

[1] https://github.com/riscv/riscv-elf-psabi-doc/issues/197

[MaskRay]

In D105254#2871278, @luismarques wrote:

In D105254#2852489, @luismarques wrote:

Makes sense. Let's wait for the GCC Bugzilla feedback.

With 'S' now documented on the GNU side, I think this can be merged.

Would we keep this constraint forever regardless of how discussions of [1] might evolve?

[1] https://github.com/riscv/riscv-elf-psabi-doc/issues/197

'S' will be kept forever, independent of issue/197. 'S' is useful on its own, for explicitly specifying the access modes by inline asm (I can image that the Linux kernel will use 'S' someday).
This will be useful even if we have an __attribute__ customizing the mode for regular C/C++ code: inline asm needs a way to access the symbol anyway.

[kito-cheng]

RISC-V GCC site has update the document for 'S'.
https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=18a463bb666cc8f3421589e7641ec617acb84741

[jrtc27]

llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll

28

Not needed

clang/lib/Basic/Targets/RISCV.cpp

bool RISCVTargetInfo::validateAsmConstraint(
   case 'f':
     // A floating-point register.
     Info.setAllowsRegister();
     return true;
   case 'A':
     // An address that is held in a general-purpose register.
     Info.setAllowsMemory();
     return true;
+  case 'S': // A symbolic address
+    Info.setAllowsRegister();
+    return true;
   case 'v':
     // A vector register.
     if (Name[1] == 'r' || Name[1] == 'm') {
       Info.setAllowsRegister();
       Name += 1;
       return true;
     }
     return false;

clang/test/CodeGen/RISCV/riscv-inline-asm.c

// CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
   asm volatile ("" :: "f"(d));
 }
 
 void test_A(int *p) {
 // CHECK-LABEL: define{{.*}} void @test_A(i32* %p)
 // CHECK: call void asm sideeffect "", "*A"(i32* %p)
   asm volatile("" :: "A"(*p));
 }
+
+void test_S() {
+// CHECK-LABEL: define{{.*}} void @test_S()
+// CHECK: call void asm sideeffect "", "S"(float* nonnull @f)
+  asm volatile("" :: "S"(&f));
+}

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Constraint.size() == 1) {
     case 'v':
       return C_RegisterClass;
     case 'I':
     case 'J':
     case 'K':
       return C_Immediate;
     case 'A':
       return C_Memory;
+    case 'S': // A symbolic address
+      return C_Other;
     }
   }
   return TargetLowering::getConstraintType(Constraint);
 }
 
 std::pair<unsigned, const TargetRegisterClass *>
 RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                                   StringRef Constraint,
case 'K':
       // Validate & create a 5-bit unsigned immediate operand.
       if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
         uint64_t CVal = C->getZExtValue();
         if (isUInt<5>(CVal))
           Ops.push_back(
               DAG.getTargetConstant(CVal, SDLoc(Op), Subtarget.getXLenVT()));
       }
       return;
+    case 'S':
+      if (const auto *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
+        Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(Op),
+                                                 GA->getValueType(0)));
+      } else if (const auto *BA = dyn_cast<BlockAddressSDNode>(Op)) {
+        Ops.push_back(DAG.getTargetBlockAddress(BA->getBlockAddress(),
+                                                BA->getValueType(0)));
+      }
+      return;
     default:
       break;
     }
   }
   TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
 }
 
 Instruction *RISCVTargetLowering::emitLeadingFence(IRBuilderBase &Builder,

llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s --check-prefix=RV32
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s --check-prefix=RV64
+
+@var = external dso_local global i32, align 4
+
+define dso_local i8* @constraint_S() {
+; RV32-LABEL: constraint_S:
+; RV32:       # %bb.0:
+; RV32-NEXT:    #APP
+; RV32-NEXT:    lui a0, %hi(var)
+; RV32-NEXT:    addi a0, a0, %lo(var)
+; RV32-NEXT:    #NO_APP
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: constraint_S:
+; RV64:       # %bb.0:
+; RV64-NEXT:    #APP
+; RV64-NEXT:    lui a0, %hi(var)
+; RV64-NEXT:    addi a0, a0, %lo(var)
+; RV64-NEXT:    #NO_APP
+; RV64-NEXT:    ret
+  %ret = tail call i8* asm "lui $0, %hi($1)\0Aaddi $0, $0, %lo($1)", "=r,S"(i32* nonnull @var)
+  ret i8* %ret
+}
+
+; Function Attrs: nofree nosync nounwind readnone
+define dso_local i8* @constraint_S_label() {
+; RV32-LABEL: constraint_S_label:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:  .Ltmp0: # Block address taken
+; RV32-NEXT:  # %bb.1: # %L1
+; RV32-NEXT:    #APP
+; RV32-NEXT:    lui a0, %hi(.Ltmp0)
+; RV32-NEXT:    addi a0, a0, %lo(.Ltmp0)
+; RV32-NEXT:    #NO_APP
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: constraint_S_label:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:  .Ltmp0: # Block address taken
+; RV64-NEXT:  # %bb.1: # %L1
+; RV64-NEXT:    #APP
+; RV64-NEXT:    lui a0, %hi(.Ltmp0)
+; RV64-NEXT:    addi a0, a0, %lo(.Ltmp0)
+; RV64-NEXT:    #NO_APP
+; RV64-NEXT:    ret
+entry:
+  br label %L1
+
+L1:
+  %ret = tail call i8* asm "lui $0, %hi($1)\0Aaddi $0, $0, %lo($1)", "=r,S"(i8* blockaddress(@constraint_S_label, %L1))
+  ret i8* %ret
+}