[GlobalISel] NFC: Change LLT::vector to take ElementCount.

[sdesmalen]

Summary

This also adds new interfaces for the fixed- and scalable case:

• LLT::fixed_vector
• LLT::scalable_vector

The strategy for migrating to the new interfaces was as follows:

• If the new LLT is a (modified) clone of another LLT, taking the same number of elements, then use LLT::vector(OtherTy.getElementCount()) or if the number of elements is halfed/doubled, it uses .divideCoefficientBy(2) or operator*. That is because there is no reason to specifically restrict the types to 'fixed_vector'.
• If the algorithm works on the number of elements (as unsigned), then just use fixed_vector. This will need to be fixed up in the future when modifying the algorithm to also work for scalable vectors, and will need then need additional tests to confirm the behaviour works the same for scalable vectors.
• If the test used the '/*Scalable=*/true` flag of LLT::vector, then this is replaced by LLT::scalable_vector.

[arsenm]

llvm/include/llvm/Support/LowLevelTypeImpl.h

100

Is there actually a context where you would use this which would need a scalable vector?

[sdesmalen]

llvm/include/llvm/Support/LowLevelTypeImpl.h

100

The context would be where the algorithm that uses scalarOrVector is agnostic of whether the type is fixed or scalable and just passes an ElementCount.
As an example: LLT::divide(int Factor) would return v2i64 for v4i64.divide(2), nxv2i64 for nxv4i64.divide(2), but i64 for v2i64.divide(2). And instead of having to write if conditional code, it can work on ElementCount directly (see its implementation in D104452)

[aemerson]

Thanks for doing this. Adding scalable vector support for GISel is an important step in the effort to bring feature parity with SelectionDAG in the long term, especially on AArch64.

The rationale for the changes makes sense to me. LGTM.

llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h

return actionIf(
         [=](const LegalityQuery &Query) {
           LLT VecTy = Query.Types[TypeIdx];
           return VecTy.isVector() && VecTy.getElementType() == EltTy &&
                  VecTy.getNumElements() < MinElements;
         },
         [=](const LegalityQuery &Query) {
           LLT VecTy = Query.Types[TypeIdx];
           return std::make_pair(
-              TypeIdx, LLT::vector(MinElements, VecTy.getElementType()));
+              TypeIdx, LLT::fixed_vector(MinElements, VecTy.getElementType()));
         });
   }
   /// Limit the number of elements in EltTy vectors to at most MaxElements.
   LegalizeRuleSet &clampMaxNumElements(unsigned TypeIdx, const LLT EltTy,
                                        unsigned MaxElements) {
     // Mark the type index as covered:
     typeIdx(TypeIdx);
     return actionIf(

llvm/include/llvm/Support/LowLevelTypeImpl.h

public:
   /// Get a low-level pointer in the given address space.
   static LLT pointer(unsigned AddressSpace, unsigned SizeInBits) {
     assert(SizeInBits > 0 && "invalid pointer size");
     return LLT{/*isPointer=*/true, /*isVector=*/false,
                ElementCount::getFixed(0), SizeInBits, AddressSpace};
   }
 
   /// Get a low-level vector of some number of elements and element width.
-  /// \p NumElements must be at least 2.
-  static LLT vector(uint16_t NumElements, unsigned ScalarSizeInBits,
-                    bool Scalable = false) {
-    assert(((!Scalable && NumElements > 1) || NumElements > 0) &&
-           "invalid number of vector elements");
+  static LLT vector(ElementCount EC, unsigned ScalarSizeInBits) {
+    assert(!EC.isScalar() && "invalid number of vector elements");
     assert(ScalarSizeInBits > 0 && "invalid vector element size");
-    return LLT{/*isPointer=*/false, /*isVector=*/true,
-               ElementCount::get(NumElements, Scalable), ScalarSizeInBits,
+    return LLT{/*isPointer=*/false, /*isVector=*/true, EC, ScalarSizeInBits,
                /*AddressSpace=*/0};
   }
 
   /// Get a low-level vector of some number of elements and element type.
-  static LLT vector(uint16_t NumElements, LLT ScalarTy, bool Scalable = false) {
-    assert(((!Scalable && NumElements > 1) || NumElements > 0) &&
-           "invalid number of vector elements");
+  static LLT vector(ElementCount EC, LLT ScalarTy) {
+    assert(!EC.isScalar() && "invalid number of vector elements");
     assert(!ScalarTy.isVector() && "invalid vector element type");
-    return LLT{ScalarTy.isPointer(), /*isVector=*/true,
-               ElementCount::get(NumElements, Scalable),
+    return LLT{ScalarTy.isPointer(), /*isVector=*/true, EC,
                ScalarTy.getSizeInBits(),
                ScalarTy.isPointer() ? ScalarTy.getAddressSpace() : 0};
   }
 
+  /// Get a low-level fixed-width vector of some number of elements and element
+  /// width.
+  static LLT fixed_vector(unsigned NumElements, unsigned ScalarSizeInBits) {
+    return vector(ElementCount::getFixed(NumElements), ScalarSizeInBits);
+  }
+
+  /// Get a low-level fixed-width vector of some number of elements and element
+  /// type.
+  static LLT fixed_vector(unsigned NumElements, LLT ScalarTy) {
+    return vector(ElementCount::getFixed(NumElements), ScalarTy);
+  }
+
+  /// Get a low-level scalable vector of some number of elements and element
+  /// width.
+  static LLT scalable_vector(unsigned MinNumElements,
+                             unsigned ScalarSizeInBits) {
+    return vector(ElementCount::getScalable(MinNumElements), ScalarSizeInBits);
+  }
+
+  /// Get a low-level scalable vector of some number of elements and element
+  /// type.
+  static LLT scalable_vector(unsigned MinNumElements, LLT ScalarTy) {
+    return vector(ElementCount::getScalable(MinNumElements), ScalarTy);
+  }
+
   static LLT scalarOrVector(uint16_t NumElements, LLT ScalarTy) {
-    return NumElements == 1 ? ScalarTy : LLT::vector(NumElements, ScalarTy);
+    // FIXME: Migrate interface to use ElementCount
+    return NumElements == 1 ? ScalarTy
+                            : LLT::fixed_vector(NumElements, ScalarTy);
   }
 
   static LLT scalarOrVector(uint16_t NumElements, unsigned ScalarSize) {
     return scalarOrVector(NumElements, LLT::scalar(ScalarSize));
   }
 
   explicit LLT(bool isPointer, bool isVector, ElementCount EC,
                unsigned SizeInBits, unsigned AddressSpace) {
public:
 
   LLT getScalarType() const {
     return isVector() ? getElementType() : *this;
   }
 
   /// If this type is a vector, return a vector with the same number of elements
   /// but the new element type. Otherwise, return the new element type.
   LLT changeElementType(LLT NewEltTy) const {
-    return isVector() ? LLT::vector(getElementCount().getKnownMinValue(),
-                                    NewEltTy, isScalable())
-                      : NewEltTy;
+    return isVector() ? LLT::vector(getElementCount(), NewEltTy) : NewEltTy;
   }
 
   /// If this type is a vector, return a vector with the same number of elements
   /// but the new element size. Otherwise, return the new element type. Invalid
   /// for pointer types. For pointer types, use changeElementType.
   LLT changeElementSize(unsigned NewEltSize) const {
     assert(!getScalarType().isPointer() &&
            "invalid to directly change element size for pointers");
-    return isVector() ? LLT::vector(getElementCount().getKnownMinValue(),
-                                    NewEltSize, isScalable())
+    return isVector() ? LLT::vector(getElementCount(), NewEltSize)
                       : LLT::scalar(NewEltSize);
   }
 
   /// Return a vector or scalar with the same element type and the new number of
   /// elements.
   LLT changeNumElements(unsigned NewNumElts) const {
     assert((!isVector() || !isScalable()) &&
            "Cannot use changeNumElements on a scalable vector");

llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

for (int I = 0, NumElts = LLTy.getNumElements(); I != NumElts; ++I) {
       EltMerges.push_back(Merge.getReg(0));
       Regs = Regs.drop_front(PartsPerElt);
     }
 
     B.buildBuildVector(OrigRegs[0], EltMerges);
   } else {
     // Vector was split, and elements promoted to a wider type.
     // FIXME: Should handle floating point promotions.
-    LLT BVType = LLT::vector(LLTy.getNumElements(), PartLLT);
+    LLT BVType = LLT::fixed_vector(LLTy.getNumElements(), PartLLT);
     auto BV = B.buildBuildVector(BVType, Regs);
     B.buildTrunc(OrigRegs[0], BV);
   }
 }
 
 /// Create a sequence of instructions to expand the value in \p SrcReg (of type
 /// \p SrcTy) to the types in \p DstRegs (of type \p PartTy). \p ExtendOp should
 /// contain the type of scalar value extension if necessary.

llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

bool IRTranslator::translateGetElementPtr(const User &U,
   unsigned VectorWidth = 0;
   if (auto *VT = dyn_cast<VectorType>(U.getType()))
     VectorWidth = cast<FixedVectorType>(VT)->getNumElements();
 
   // We might need to splat the base pointer into a vector if the offsets
   // are vectors.
   if (VectorWidth && !PtrTy.isVector()) {
     BaseReg =
-        MIRBuilder.buildSplatVector(LLT::vector(VectorWidth, PtrTy), BaseReg)
+        MIRBuilder
+            .buildSplatVector(LLT::fixed_vector(VectorWidth, PtrTy), BaseReg)
             .getReg(0);
     PtrIRTy = FixedVectorType::get(PtrIRTy, VectorWidth);
     PtrTy = getLLTForType(*PtrIRTy, *DL);
     OffsetIRTy = DL->getIntPtrType(PtrIRTy);
     OffsetTy = getLLTForType(*OffsetIRTy, *DL);
   }
 
   int64_t Offset = 0;

llvm/lib/CodeGen/GlobalISel/LegacyLegalizerInfo.cpp

LegacyLegalizerInfo::findVectorLegalAction(const InstrAspect &Aspect) const {
   if (TypeIdx >= ScalarInVectorActions[OpcodeIdx].size())
     return {NotFound, Aspect.Type};
   const SizeAndActionsVec &ElemSizeVec =
       ScalarInVectorActions[OpcodeIdx][TypeIdx];
 
   LLT IntermediateType;
   auto ElementSizeAndAction =
       findAction(ElemSizeVec, Aspect.Type.getScalarSizeInBits());
-  IntermediateType =
-      LLT::vector(Aspect.Type.getNumElements(), ElementSizeAndAction.first);
+  IntermediateType = LLT::fixed_vector(Aspect.Type.getNumElements(),
+                                       ElementSizeAndAction.first);
   if (ElementSizeAndAction.second != Legal)
     return {ElementSizeAndAction.second, IntermediateType};
 
   auto i = NumElements2Actions[OpcodeIdx].find(
       IntermediateType.getScalarSizeInBits());
   if (i == NumElements2Actions[OpcodeIdx].end()) {
     return {NotFound, IntermediateType};
   }
   const SizeAndActionsVec &NumElementsVec = (*i).second[TypeIdx];
   auto NumElementsAndAction =
       findAction(NumElementsVec, IntermediateType.getNumElements());
   return {NumElementsAndAction.second,
-          LLT::vector(NumElementsAndAction.first,
+          LLT::fixed_vector(NumElementsAndAction.first,
                             IntermediateType.getScalarSizeInBits())};
 }
 
 unsigned LegacyLegalizerInfo::getOpcodeIdxForOpcode(unsigned Opcode) const {
   assert(Opcode >= FirstOp && Opcode <= LastOp && "Unsupported opcode");
   return Opcode - FirstOp;
 }
 
 

llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp

 }
 
 LegalizeMutation LegalizeMutations::moreElementsToNextPow2(unsigned TypeIdx,
                                                            unsigned Min) {
   return [=](const LegalityQuery &Query) {
     const LLT VecTy = Query.Types[TypeIdx];
     unsigned NewNumElements =
         std::max(1u << Log2_32_Ceil(VecTy.getNumElements()), Min);
-    return std::make_pair(TypeIdx,
-                          LLT::vector(NewNumElements, VecTy.getElementType()));
+    return std::make_pair(
+        TypeIdx, LLT::fixed_vector(NewNumElements, VecTy.getElementType()));
   };
 }
 
 LegalizeMutation LegalizeMutations::scalarize(unsigned TypeIdx) {
   return [=](const LegalityQuery &Query) {
     return std::make_pair(TypeIdx, Query.Types[TypeIdx].getElementType());
   };
 }

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

case TargetOpcode::G_IMPLICIT_DEF: {
     // G_ANYEXT(G_IMPLICIT_DEF). Cast result to vector if needed.
     // FIXME: Although this would also be legal for the general case, it causes
     //  a lot of regressions in the emitted code (superfluous COPYs, artifact
     //  combines not being hit). This seems to be a problem related to the
     //  artifact combiner.
     if (SizeOp0 % NarrowSize != 0) {
       LLT ImplicitTy = NarrowTy;
       if (DstTy.isVector())
-        ImplicitTy = LLT::vector(DstTy.getNumElements(), ImplicitTy);
+        ImplicitTy = LLT::vector(DstTy.getElementCount(), ImplicitTy);
 
       Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0);
       MIRBuilder.buildAnyExt(DstReg, ImplicitReg);
 
       MI.eraseFromParent();
       return Legalized;
     }
 
case TargetOpcode::G_PHI: {
     return Legalized;
   }
   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
     if (TypeIdx == 0) {
       Register VecReg = MI.getOperand(1).getReg();
       LLT VecTy = MRI.getType(VecReg);
       Observer.changingInstr(MI);
 
-      widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
-                                     WideTy.getSizeInBits()),
-                     1, TargetOpcode::G_SEXT);
+      widenScalarSrc(
+          MI, LLT::vector(VecTy.getElementCount(), WideTy.getSizeInBits()), 1,
+          TargetOpcode::G_SEXT);
 
       widenScalarDst(MI, WideTy, 0);
       Observer.changedInstr(MI);
       return Legalized;
     }
 
     if (TypeIdx != 2)
       return UnableToLegalize;
     Observer.changingInstr(MI);
     // TODO: Probably should be zext
     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
     Observer.changedInstr(MI);
     return Legalized;
   }
   case TargetOpcode::G_INSERT_VECTOR_ELT: {
     if (TypeIdx == 1) {
       Observer.changingInstr(MI);
 
       Register VecReg = MI.getOperand(1).getReg();
       LLT VecTy = MRI.getType(VecReg);
-      LLT WideVecTy = LLT::vector(VecTy.getNumElements(), WideTy);
+      LLT WideVecTy = LLT::vector(VecTy.getElementCount(), WideTy);
 
       widenScalarSrc(MI, WideVecTy, 1, TargetOpcode::G_ANYEXT);
       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
       widenScalarDst(MI, WideVecTy, 0);
       Observer.changedInstr(MI);
       return Legalized;
     }
 
if (DstTy.isVector()) {
         // %1:_(<4 x s8>) = G_BITCAST %0:_(<2 x s16>)
         //
         // =>
         //
         // %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0
         // %3:_(<2 x s8>) = G_BITCAST %2
         // %4:_(<2 x s8>) = G_BITCAST %3
         // %1:_(<4 x s16>) = G_CONCAT_VECTORS %3, %4
-        DstCastTy = LLT::vector(NumDstElt / NumSrcElt, DstEltTy);
+        DstCastTy = LLT::fixed_vector(NumDstElt / NumSrcElt, DstEltTy);
         SrcPartTy = SrcEltTy;
       } else if (NumSrcElt > NumDstElt) { // Source element type is smaller.
         //
         // %1:_(<2 x s16>) = G_BITCAST %0:_(<4 x s8>)
         //
         // =>
         //
         // %2:_(<2 x s8>), %3:_(<2 x s8>) = G_UNMERGE_VALUES %0
         // %3:_(s16) = G_BITCAST %2
         // %4:_(s16) = G_BITCAST %3
         // %1:_(<2 x s16>) = G_BUILD_VECTOR %3, %4
-        SrcPartTy = LLT::vector(NumSrcElt / NumDstElt, SrcEltTy);
+        SrcPartTy = LLT::fixed_vector(NumSrcElt / NumDstElt, SrcEltTy);
         DstCastTy = DstEltTy;
       }
 
       getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcPartTy);
       for (Register &SrcReg : SrcRegs)
         SrcReg = MIRBuilder.buildBitcast(DstCastTy, SrcReg).getReg(0);
     } else
       getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcEltTy);
LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
   unsigned NumParts;
 
   if (NarrowTy.isVector()) {
     // Uneven breakdown not handled.
     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
       return UnableToLegalize;
 
-    NarrowTy1 = LLT::vector(NarrowTy.getNumElements(), SrcTy.getElementType());
+    NarrowTy1 = LLT::vector(NarrowTy.getElementCount(), SrcTy.getElementType());
   } else {
     NumParts = DstTy.getNumElements();
     NarrowTy1 = SrcTy.getElementType();
   }
 
   SmallVector<Register, 4> SrcRegs, DstRegs;
   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
 
LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
   LLT NarrowTy0, NarrowTy1;
 
   if (TypeIdx == 0) {
     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
     unsigned OldElts = DstTy.getNumElements();
 
     NarrowTy0 = NarrowTy;
     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
-    NarrowTy1 = NarrowTy.isVector() ?
-      LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
-      SrcTy.getElementType();
+    NarrowTy1 = NarrowTy.isVector() ? LLT::vector(NarrowTy.getElementCount(),
+                                                  SrcTy.getScalarSizeInBits())
+                                    : SrcTy.getElementType();
 
   } else {
     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
     unsigned OldElts = SrcTy.getNumElements();
 
     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
       NarrowTy.getNumElements();
-    NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
-                            DstTy.getScalarSizeInBits());
+    NarrowTy0 =
+        LLT::vector(NarrowTy.getElementCount(), DstTy.getScalarSizeInBits());
     NarrowTy1 = NarrowTy;
   }
 
   // FIXME: Don't know how to handle the situation where the small vectors
   // aren't all the same size yet.
   if (NarrowTy1.isVector() &&
       NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
     return UnableToLegalize;
if (TypeIdx == 0) {
 
     NumParts = Size / NarrowSize;
 
     // Need to break down the condition type
     if (CondTy.isVector()) {
       if (CondTy.getNumElements() == NumParts)
         NarrowTy1 = CondTy.getElementType();
       else
-        NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts,
-                                CondTy.getScalarSizeInBits());
+        NarrowTy1 =
+            LLT::vector(CondTy.getElementCount().divideCoefficientBy(NumParts),
     }
   } else {
     NumParts = CondTy.getNumElements();
     if (NarrowTy.isVector()) {
       // TODO: Handle uneven breakdown.
       if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements())
         return UnableToLegalize;
 

llvm/lib/CodeGen/GlobalISel/Utils.cpp

if (OrigTy.isVector()) {
 
     if (TargetTy.isVector()) {
       const LLT TargetElt = TargetTy.getElementType();
 
       if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
         int GCDElts = greatestCommonDivisor(OrigTy.getNumElements(),
                                             TargetTy.getNumElements());
         // Prefer the original element type.
-        int Mul = OrigTy.getNumElements() * TargetTy.getNumElements();
-        return LLT::vector(Mul / GCDElts, OrigTy.getElementType());
+        ElementCount Mul = OrigTy.getElementCount() * TargetTy.getNumElements();
+        return LLT::vector(Mul.divideCoefficientBy(GCDElts),
+                           OrigTy.getElementType());
       }
     } else {
       if (OrigElt.getSizeInBits() == TargetSize)
         return OrigTy;
     }
 
     unsigned LCMSize = getLCMSize(OrigSize, TargetSize);
-    return LLT::vector(LCMSize / OrigElt.getSizeInBits(), OrigElt);
+    return LLT::fixed_vector(LCMSize / OrigElt.getSizeInBits(), OrigElt);
   }
 
   if (TargetTy.isVector()) {
     unsigned LCMSize = getLCMSize(OrigSize, TargetSize);
-    return LLT::vector(LCMSize / OrigSize, OrigTy);
+    return LLT::fixed_vector(LCMSize / OrigSize, OrigTy);
   }
 
   unsigned LCMSize = getLCMSize(OrigSize, TargetSize);
 
   // Preserve pointer types.
   if (LCMSize == OrigSize)
     return OrigTy;
   if (LCMSize == TargetSize)
if (OrigTy.isVector()) {
     unsigned GCD = greatestCommonDivisor(OrigSize, TargetSize);
     if (GCD == OrigElt.getSizeInBits())
       return OrigElt;
 
     // If we can't produce the original element type, we have to use a smaller
     // scalar.
     if (GCD < OrigElt.getSizeInBits())
       return LLT::scalar(GCD);
-    return LLT::vector(GCD / OrigElt.getSizeInBits(), OrigElt);
+    return LLT::fixed_vector(GCD / OrigElt.getSizeInBits(), OrigElt);
   }
 
   if (TargetTy.isVector()) {
     // Try to preserve the original element type.
     LLT TargetElt = TargetTy.getElementType();
     if (TargetElt.getSizeInBits() == OrigSize)
       return OrigTy;
   }

llvm/lib/CodeGen/LowLevelType.cpp

 using namespace llvm;
 
 LLT llvm::getLLTForType(Type &Ty, const DataLayout &DL) {
   if (auto VTy = dyn_cast<VectorType>(&Ty)) {
     auto EC = VTy->getElementCount();
     LLT ScalarTy = getLLTForType(*VTy->getElementType(), DL);
     if (EC.isScalar())
       return ScalarTy;
-    return LLT::vector(EC.getKnownMinValue(), ScalarTy, EC.isScalable());
+    return LLT::vector(EC, ScalarTy);
   }
 
   if (auto PTy = dyn_cast<PointerType>(&Ty)) {
     unsigned AddrSpace = PTy->getAddressSpace();
     return LLT::pointer(AddrSpace, DL.getPointerSizeInBits(AddrSpace));
   }
 
   if (Ty.isSized()) {
return MVT::getVectorVT(
       MVT::getIntegerVT(Ty.getElementType().getSizeInBits()),
       Ty.getNumElements());
 }
 
 LLT llvm::getLLTForMVT(MVT Ty) {
   if (!Ty.isVector())
     return LLT::scalar(Ty.getSizeInBits());
 
-  return LLT::vector(Ty.getVectorNumElements(),
+  return LLT::vector(Ty.getVectorElementCount(),
                      Ty.getVectorElementType().getSizeInBits());
 }
 
 const llvm::fltSemantics &llvm::getFltSemanticForLLT(LLT Ty) {
   assert(Ty.isScalar() && "Expected a scalar type.");
   switch (Ty.getSizeInBits()) {
   case 16:
     return APFloat::IEEEhalf();

llvm/lib/CodeGen/MIRParser/MIParser.cpp

bool MIParser::parseLowLevelType(StringRef::iterator Loc, LLT &Ty) {
   } else
     return error(Loc, "expected <M x sN> or <M x pA> for vector type");
   lex();
 
   if (Token.isNot(MIToken::greater))
     return error(Loc, "expected <M x sN> or <M x pA> for vector type");
   lex();
 
-  Ty = LLT::vector(NumElements, Ty);
+  Ty = LLT::fixed_vector(NumElements, Ty);
   return false;
 }
 
 bool MIParser::parseTypedImmediateOperand(MachineOperand &Dest) {
   assert(Token.is(MIToken::Identifier));
   StringRef TypeStr = Token.range();
   if (TypeStr.front() != 'i' && TypeStr.front() != 's' &&
       TypeStr.front() != 'p')

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

*Fast = !Subtarget->isMisaligned128StoreSlow() ||
 
             // Code that uses clang vector extensions can mark that it
             // wants unaligned accesses to be treated as fast by
             // underspecifying alignment to be 1 or 2.
             Alignment <= 2 ||
 
             // Disregard v2i64. Memcpy lowering produces those and splitting
             // them regresses performance on micro-benchmarks and olden/bh.
-            Ty == LLT::vector(2, 64);
+            Ty == LLT::fixed_vector(2, 64);
   }
   return true;
 }
 
 FastISel *
 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
                                       const TargetLibraryInfo *libInfo) const {
   return AArch64::createFastISel(funcInfo, libInfo);
auto AlignmentIsAcceptable = [&](EVT VT, Align AlignCheck) {
     bool Fast;
     return allowsMisalignedMemoryAccesses(VT, 0, Align(1),
                                           MachineMemOperand::MONone, &Fast) &&
            Fast;
   };
 
   if (CanUseNEON && Op.isMemset() && !IsSmallMemset &&
       AlignmentIsAcceptable(MVT::v2i64, Align(16)))
-    return LLT::vector(2, 64);
+    return LLT::fixed_vector(2, 64);
   if (CanUseFP && !IsSmallMemset && AlignmentIsAcceptable(MVT::f128, Align(16)))
     return LLT::scalar(128);
   if (Op.size() >= 8 && AlignmentIsAcceptable(MVT::i64, Align(8)))
     return LLT::scalar(64);
   if (Op.size() >= 4 && AlignmentIsAcceptable(MVT::i32, Align(4)))
     return LLT::scalar(32);
   return LLT();
 }

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

bool AArch64InstructionSelector::selectVectorSHL(MachineInstr &I,
   if (!Ty.isVector())
     return false;
 
   // Check if we have a vector of constants on RHS that we can select as the
   // immediate form.
   Optional<int64_t> ImmVal = getVectorSHLImm(Ty, Src2Reg, MRI);
 
   unsigned Opc = 0;
-  if (Ty == LLT::vector(2, 64)) {
+  if (Ty == LLT::fixed_vector(2, 64)) {
     Opc = ImmVal ? AArch64::SHLv2i64_shift : AArch64::USHLv2i64;
-  } else if (Ty == LLT::vector(4, 32)) {
+  } else if (Ty == LLT::fixed_vector(4, 32)) {
     Opc = ImmVal ? AArch64::SHLv4i32_shift : AArch64::USHLv4i32;
-  } else if (Ty == LLT::vector(2, 32)) {
+  } else if (Ty == LLT::fixed_vector(2, 32)) {
     Opc = ImmVal ? AArch64::SHLv2i32_shift : AArch64::USHLv2i32;
-  } else if (Ty == LLT::vector(4, 16)) {
+  } else if (Ty == LLT::fixed_vector(4, 16)) {
     Opc = ImmVal ? AArch64::SHLv4i16_shift : AArch64::USHLv4i16;
-  } else if (Ty == LLT::vector(8, 16)) {
+  } else if (Ty == LLT::fixed_vector(8, 16)) {
     Opc = ImmVal ? AArch64::SHLv8i16_shift : AArch64::USHLv8i16;
-  } else if (Ty == LLT::vector(16, 8)) {
+  } else if (Ty == LLT::fixed_vector(16, 8)) {
     Opc = ImmVal ? AArch64::SHLv16i8_shift : AArch64::USHLv16i8;
-  } else if (Ty == LLT::vector(8, 8)) {
+  } else if (Ty == LLT::fixed_vector(8, 8)) {
     Opc = ImmVal ? AArch64::SHLv8i8_shift : AArch64::USHLv8i8;
   } else {
     LLVM_DEBUG(dbgs() << "Unhandled G_SHL type");
     return false;
   }
 
   auto Shl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg});
   if (ImmVal)
bool AArch64InstructionSelector::selectVectorAshrLshr(
   // There is not a shift right register instruction, but the shift left
   // register instruction takes a signed value, where negative numbers specify a
   // right shift.
 
   unsigned Opc = 0;
   unsigned NegOpc = 0;
   const TargetRegisterClass *RC =
       getRegClassForTypeOnBank(Ty, RBI.getRegBank(AArch64::FPRRegBankID), RBI);
-  if (Ty == LLT::vector(2, 64)) {
+  if (Ty == LLT::fixed_vector(2, 64)) {
     Opc = IsASHR ? AArch64::SSHLv2i64 : AArch64::USHLv2i64;
     NegOpc = AArch64::NEGv2i64;
-  } else if (Ty == LLT::vector(4, 32)) {
+  } else if (Ty == LLT::fixed_vector(4, 32)) {
     Opc = IsASHR ? AArch64::SSHLv4i32 : AArch64::USHLv4i32;
     NegOpc = AArch64::NEGv4i32;
-  } else if (Ty == LLT::vector(2, 32)) {
+  } else if (Ty == LLT::fixed_vector(2, 32)) {
     Opc = IsASHR ? AArch64::SSHLv2i32 : AArch64::USHLv2i32;
     NegOpc = AArch64::NEGv2i32;
-  } else if (Ty == LLT::vector(4, 16)) {
+  } else if (Ty == LLT::fixed_vector(4, 16)) {
     Opc = IsASHR ? AArch64::SSHLv4i16 : AArch64::USHLv4i16;
     NegOpc = AArch64::NEGv4i16;
-  } else if (Ty == LLT::vector(8, 16)) {
+  } else if (Ty == LLT::fixed_vector(8, 16)) {
     Opc = IsASHR ? AArch64::SSHLv8i16 : AArch64::USHLv8i16;
     NegOpc = AArch64::NEGv8i16;
-  } else if (Ty == LLT::vector(16, 8)) {
+  } else if (Ty == LLT::fixed_vector(16, 8)) {
     Opc = IsASHR ? AArch64::SSHLv16i8 : AArch64::USHLv16i8;
     NegOpc = AArch64::NEGv16i8;
-  } else if (Ty == LLT::vector(8, 8)) {
+  } else if (Ty == LLT::fixed_vector(8, 8)) {
     Opc = IsASHR ? AArch64::SSHLv8i8 : AArch64::USHLv8i8;
     NegOpc = AArch64::NEGv8i8;
   } else {
     LLVM_DEBUG(dbgs() << "Unhandled G_ASHR type");
     return false;
   }
 
   auto Neg = MIB.buildInstr(NegOpc, {RC}, {Src2Reg});
bool AArch64InstructionSelector::convertPtrAddToAdd(
     MachineInstr &I, MachineRegisterInfo &MRI) {
   assert(I.getOpcode() == TargetOpcode::G_PTR_ADD && "Expected G_PTR_ADD");
   Register DstReg = I.getOperand(0).getReg();
   Register AddOp1Reg = I.getOperand(1).getReg();
   const LLT PtrTy = MRI.getType(DstReg);
   if (PtrTy.getAddressSpace() != 0)
     return false;
 
-  const LLT CastPtrTy = PtrTy.isVector() ? LLT::vector(2, 64) : LLT::scalar(64);
+  const LLT CastPtrTy =
+      PtrTy.isVector() ? LLT::fixed_vector(2, 64) : LLT::scalar(64);
   auto PtrToInt = MIB.buildPtrToInt(CastPtrTy, AddOp1Reg);
   // Set regbanks on the registers.
   if (PtrTy.isVector())
     MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(AArch64::FPRRegBankID));
   else
     MRI.setRegBank(PtrToInt.getReg(0), RBI.getRegBank(AArch64::GPRRegBankID));
 
   // Now turn the %dst(p0) = G_PTR_ADD %base, off into:
if (DstRB.getID() == AArch64::GPRRegBankID) {
         LLVM_DEBUG(
             dbgs() << "Unhandled mismatched classes in G_TRUNC/G_PTRTOINT\n");
         return false;
       }
 
       I.setDesc(TII.get(TargetOpcode::COPY));
       return true;
     } else if (DstRB.getID() == AArch64::FPRRegBankID) {
-      if (DstTy == LLT::vector(4, 16) && SrcTy == LLT::vector(4, 32)) {
+      if (DstTy == LLT::fixed_vector(4, 16) &&
+          SrcTy == LLT::fixed_vector(4, 32)) {
         I.setDesc(TII.get(AArch64::XTNv4i16));
         constrainSelectedInstRegOperands(I, TII, TRI, RBI);
         return true;
       }
 
       if (!SrcTy.isVector() && SrcTy.getSizeInBits() == 128) {
         MachineInstr *Extract = emitExtractVectorElt(
             DstReg, DstRB, LLT::scalar(DstTy.getSizeInBits()), SrcReg, 0, MIB);
case AArch64::G_DUP: {
     // imported patterns. Do it manually here. Avoiding generating s16 gpr is
     // difficult because at RBS we may end up pessimizing the fpr case if we
     // decided to add an anyextend to fix this. Manual selection is the most
     // robust solution for now.
     if (RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI)->getID() !=
         AArch64::GPRRegBankID)
       return false; // We expect the fpr regbank case to be imported.
     LLT VecTy = MRI.getType(I.getOperand(0).getReg());
-    if (VecTy == LLT::vector(8, 8))
+    if (VecTy == LLT::fixed_vector(8, 8))
       I.setDesc(TII.get(AArch64::DUPv8i8gpr));
-    else if (VecTy == LLT::vector(16, 8))
+    else if (VecTy == LLT::fixed_vector(16, 8))
       I.setDesc(TII.get(AArch64::DUPv16i8gpr));
-    else if (VecTy == LLT::vector(4, 16))
+    else if (VecTy == LLT::fixed_vector(4, 16))
       I.setDesc(TII.get(AArch64::DUPv4i16gpr));
-    else if (VecTy == LLT::vector(8, 16))
+    else if (VecTy == LLT::fixed_vector(8, 16))
       I.setDesc(TII.get(AArch64::DUPv8i16gpr));
     else
       return false;
     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
   }
   case TargetOpcode::G_INTRINSIC_TRUNC:
     return selectIntrinsicTrunc(I, MRI);
   case TargetOpcode::G_INTRINSIC_ROUND:

 
 bool AArch64InstructionSelector::selectReduction(MachineInstr &I,
                                                  MachineRegisterInfo &MRI) {
   Register VecReg = I.getOperand(1).getReg();
   LLT VecTy = MRI.getType(VecReg);
   if (I.getOpcode() == TargetOpcode::G_VECREDUCE_ADD) {
     // For <2 x i32> ADDPv2i32 generates an FPR64 value, so we need to emit
     // a subregister copy afterwards.
-    if (VecTy == LLT::vector(2, 32)) {
+    if (VecTy == LLT::fixed_vector(2, 32)) {
       Register DstReg = I.getOperand(0).getReg();
       auto AddP = MIB.buildInstr(AArch64::ADDPv2i32, {&AArch64::FPR64RegClass},
                                  {VecReg, VecReg});
       auto Copy = MIB.buildInstr(TargetOpcode::COPY, {DstReg}, {})
                       .addReg(AddP.getReg(0), 0, AArch64::ssub)
                       .getReg(0);
       RBI.constrainGenericRegister(Copy, AArch64::FPR32RegClass, MRI);
       I.eraseFromParent();
       return constrainSelectedInstRegOperands(*AddP, TII, TRI, RBI);
     }
 
     unsigned Opc = 0;
-    if (VecTy == LLT::vector(16, 8))
+    if (VecTy == LLT::fixed_vector(16, 8))
       Opc = AArch64::ADDVv16i8v;
-    else if (VecTy == LLT::vector(8, 16))
+    else if (VecTy == LLT::fixed_vector(8, 16))
       Opc = AArch64::ADDVv8i16v;
-    else if (VecTy == LLT::vector(4, 32))
+    else if (VecTy == LLT::fixed_vector(4, 32))
       Opc = AArch64::ADDVv4i32v;
-    else if (VecTy == LLT::vector(2, 64))
+    else if (VecTy == LLT::fixed_vector(2, 64))
       Opc = AArch64::ADDPv2i64p;
     else {
       LLVM_DEBUG(dbgs() << "Unhandled type for add reduction");
       return false;
     }
     I.setDesc(TII.get(Opc));
     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
   }
 
   if (I.getOpcode() == TargetOpcode::G_VECREDUCE_FADD) {
     unsigned Opc = 0;
-    if (VecTy == LLT::vector(2, 32))
+    if (VecTy == LLT::fixed_vector(2, 32))
       Opc = AArch64::FADDPv2i32p;
-    else if (VecTy == LLT::vector(2, 64))
+    else if (VecTy == LLT::fixed_vector(2, 64))
       Opc = AArch64::FADDPv2i64p;
     else {
       LLVM_DEBUG(dbgs() << "Unhandled type for fadd reduction");
       return false;
     }
     I.setDesc(TII.get(Opc));
     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
   }

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
   const LLT s1 = LLT::scalar(1);
   const LLT s8 = LLT::scalar(8);
   const LLT s16 = LLT::scalar(16);
   const LLT s32 = LLT::scalar(32);
   const LLT s64 = LLT::scalar(64);
   const LLT s128 = LLT::scalar(128);
   const LLT s256 = LLT::scalar(256);
   const LLT s512 = LLT::scalar(512);
-  const LLT v16s8 = LLT::vector(16, 8);
-  const LLT v8s8 = LLT::vector(8, 8);
-  const LLT v4s8 = LLT::vector(4, 8);
-  const LLT v8s16 = LLT::vector(8, 16);
-  const LLT v4s16 = LLT::vector(4, 16);
-  const LLT v2s16 = LLT::vector(2, 16);
-  const LLT v2s32 = LLT::vector(2, 32);
-  const LLT v4s32 = LLT::vector(4, 32);
-  const LLT v2s64 = LLT::vector(2, 64);
-  const LLT v2p0 = LLT::vector(2, p0);
+  const LLT v16s8 = LLT::fixed_vector(16, 8);
+  const LLT v8s8 = LLT::fixed_vector(8, 8);
+  const LLT v4s8 = LLT::fixed_vector(4, 8);
+  const LLT v8s16 = LLT::fixed_vector(8, 16);
+  const LLT v4s16 = LLT::fixed_vector(4, 16);
+  const LLT v2s16 = LLT::fixed_vector(2, 16);
+  const LLT v2s32 = LLT::fixed_vector(2, 32);
+  const LLT v4s32 = LLT::fixed_vector(4, 32);
+  const LLT v2s64 = LLT::fixed_vector(2, 64);
+  const LLT v2p0 = LLT::fixed_vector(2, p0);
 
   std::initializer_list<LLT> PackedVectorAllTypeList = {/* Begin 128bit types */
                                                         v16s8, v8s16, v4s32,
                                                         v2s64, v2p0,
                                                         /* End 128bit types */
                                                         /* Begin 64bit types */
                                                         v8s8, v4s16, v2s32};
 
getActionDefinitionsBuilder({G_IMPLICIT_DEF, G_FREEZE})
           [=](const LegalityQuery &Query) {
             return Query.Types[0].isVector() &&
                    (Query.Types[0].getElementType() != s64 ||
                     Query.Types[0].getNumElements() != 2);
           },
           [=](const LegalityQuery &Query) {
             LLT EltTy = Query.Types[0].getElementType();
             if (EltTy == s64)
-              return std::make_pair(0, LLT::vector(2, 64));
+              return std::make_pair(0, LLT::fixed_vector(2, 64));
             return std::make_pair(0, EltTy);
           });
 
   getActionDefinitionsBuilder(G_PHI).legalFor({p0, s16, s32, s64})
       .legalFor(PackedVectorAllTypeList)
       .clampScalar(0, s16, s64)
       .widenScalarToNextPow2(0);
 
bool AArch64LegalizerInfo::legalizeLoadStore(
 
   if (!ValTy.isVector() || !ValTy.getElementType().isPointer() ||
       ValTy.getElementType().getAddressSpace() != 0) {
     LLVM_DEBUG(dbgs() << "Tried to do custom legalization on wrong load/store");
     return false;
   }
 
   unsigned PtrSize = ValTy.getElementType().getSizeInBits();
-  const LLT NewTy = LLT::vector(ValTy.getNumElements(), PtrSize);
+  const LLT NewTy = LLT::vector(ValTy.getElementCount(), PtrSize);
   auto &MMO = **MI.memoperands_begin();
   if (MI.getOpcode() == TargetOpcode::G_STORE) {
     auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg);
     MIRBuilder.buildStore(Bitcast.getReg(0), MI.getOperand(1), MMO);
   } else {
     auto NewLoad = MIRBuilder.buildLoad(NewTy, MI.getOperand(1), MMO);
     MIRBuilder.buildBitcast(ValReg, NewLoad);
   }
bool AArch64LegalizerInfo::legalizeCTPOP(MachineInstr &MI,
   assert(!Ty.isVector() && "Vector types not handled yet!");
   assert(Ty == MRI.getType(Dst) &&
          "Expected src and dst to have the same type!");
   // TODO: Handle s128.
   unsigned Size = Ty.getSizeInBits();
   assert((Size == 32 || Size == 64) && "Expected only 32 or 64 bit scalars!");
   if (Size == 32)
     Val = MIRBuilder.buildZExt(LLT::scalar(64), Val).getReg(0);
-  const LLT V8S8 = LLT::vector(8, LLT::scalar(8));
+  const LLT V8S8 = LLT::fixed_vector(8, LLT::scalar(8));
   Val = MIRBuilder.buildBitcast(V8S8, Val).getReg(0);
   auto CTPOP = MIRBuilder.buildCTPOP(V8S8, Val);
   auto UADDLV =
       MIRBuilder
           .buildIntrinsic(Intrinsic::aarch64_neon_uaddlv, {LLT::scalar(32)},
                           /*HasSideEffects = */ false)
           .addUse(CTPOP.getReg(0));
   if (Size == 64)

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp

bool applyDupLane(MachineInstr &MI, MachineRegisterInfo &MRI,
   const LLT SrcTy = MRI.getType(Src1Reg);
 
   B.setInstrAndDebugLoc(MI);
   auto Lane = B.buildConstant(LLT::scalar(64), MatchInfo.second);
 
   Register DupSrc = MI.getOperand(1).getReg();
   // For types like <2 x s32>, we can use G_DUPLANE32, with a <4 x s32> source.
   // To do this, we can use a G_CONCAT_VECTORS to do the widening.
-  if (SrcTy == LLT::vector(2, LLT::scalar(32))) {
+  if (SrcTy == LLT::fixed_vector(2, LLT::scalar(32))) {
     assert(MRI.getType(MI.getOperand(0).getReg()).getNumElements() == 2 &&
            "Unexpected dest elements");
     auto Undef = B.buildUndef(SrcTy);
     DupSrc = B.buildConcatVectors(SrcTy.changeNumElements(4),
                                   {Src1Reg, Undef.getReg(0)})
                  .getReg(0);
   }
   B.buildInstr(MatchInfo.first, {MI.getOperand(0).getReg()}, {DupSrc, Lane});

llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp

 
 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
 AMDGPUFunctionArgInfo::getPreloadedValue(
     AMDGPUFunctionArgInfo::PreloadedValue Value) const {
   switch (Value) {
   case AMDGPUFunctionArgInfo::PRIVATE_SEGMENT_BUFFER: {
     return std::make_tuple(PrivateSegmentBuffer ? &PrivateSegmentBuffer
                                                 : nullptr,
-                           &AMDGPU::SGPR_128RegClass, LLT::vector(4, 32));
+                           &AMDGPU::SGPR_128RegClass, LLT::fixed_vector(4, 32));
   }
   case AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR:
     return std::make_tuple(ImplicitBufferPtr ? &ImplicitBufferPtr : nullptr,
                            &AMDGPU::SGPR_64RegClass,
                            LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
   case AMDGPUFunctionArgInfo::WORKGROUP_ID_X:
     return std::make_tuple(WorkGroupIDX ? &WorkGroupIDX : nullptr,
                            &AMDGPU::SGPR_32RegClass, LLT::scalar(32));

llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

 // call instruction.
 void AMDGPUCallLowering::handleImplicitCallArguments(
     MachineIRBuilder &MIRBuilder, MachineInstrBuilder &CallInst,
     const GCNSubtarget &ST, const SIMachineFunctionInfo &FuncInfo,
     ArrayRef<std::pair<MCRegister, Register>> ImplicitArgRegs) const {
   if (!ST.enableFlatScratch()) {
     // Insert copies for the SRD. In the HSA case, this should be an identity
     // copy.
-    auto ScratchRSrcReg =
-        MIRBuilder.buildCopy(LLT::vector(4, 32), FuncInfo.getScratchRSrcReg());
+    auto ScratchRSrcReg = MIRBuilder.buildCopy(LLT::fixed_vector(4, 32),
+                                               FuncInfo.getScratchRSrcReg());
     MIRBuilder.buildCopy(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, ScratchRSrcReg);
     CallInst.addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Implicit);
   }
 
   for (std::pair<MCRegister, Register> ArgReg : ImplicitArgRegs) {
     MIRBuilder.buildCopy((Register)ArgReg.first, ArgReg.second);
     CallInst.addReg(ArgReg.first, RegState::Implicit);
   }

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

 }
 
 bool AMDGPUInstructionSelector::selectG_BUILD_VECTOR_TRUNC(
   MachineInstr &MI) const {
   if (selectImpl(MI, *CoverageInfo))
     return true;
 
   const LLT S32 = LLT::scalar(32);
-  const LLT V2S16 = LLT::vector(2, 16);
+  const LLT V2S16 = LLT::fixed_vector(2, 16);
 
   Register Dst = MI.getOperand(0).getReg();
   if (MRI->getType(Dst) != V2S16)
     return false;
 
   const RegisterBank *DstBank = RBI.getRegBank(Dst, *MRI, TRI);
   if (DstBank->getID() != AMDGPU::SGPRRegBankID)
     return false;
if (!SrcRC || !DstRC)
     return false;
 
   if (!RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI) ||
       !RBI.constrainGenericRegister(DstReg, *DstRC, *MRI)) {
     LLVM_DEBUG(dbgs() << "Failed to constrain G_TRUNC\n");
     return false;
   }
 
-  if (DstTy == LLT::vector(2, 16) && SrcTy == LLT::vector(2, 32)) {
+  if (DstTy == LLT::fixed_vector(2, 16) && SrcTy == LLT::fixed_vector(2, 32)) {
     MachineBasicBlock *MBB = I.getParent();
     const DebugLoc &DL = I.getDebugLoc();
 
     Register LoReg = MRI->createVirtualRegister(DstRC);
     Register HiReg = MRI->createVirtualRegister(DstRC);
     BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), LoReg)
       .addReg(SrcReg, 0, AMDGPU::sub0);
     BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), HiReg)

 // This is only legal with VOP3P instructions as an aid to op_sel matching.
 bool AMDGPUInstructionSelector::selectG_SHUFFLE_VECTOR(
   MachineInstr &MI) const {
   Register DstReg = MI.getOperand(0).getReg();
   Register Src0Reg = MI.getOperand(1).getReg();
   Register Src1Reg = MI.getOperand(2).getReg();
   ArrayRef<int> ShufMask = MI.getOperand(3).getShuffleMask();
 
-  const LLT V2S16 = LLT::vector(2, 16);
+  const LLT V2S16 = LLT::fixed_vector(2, 16);
   if (MRI->getType(DstReg) != V2S16 || MRI->getType(Src0Reg) != V2S16)
     return false;
 
   if (!AMDGPU::isLegalVOP3PShuffleMask(ShufMask))
     return false;
 
   assert(ShufMask.size() == 2);
   assert(STI.hasSDWA() && "no target has VOP3P but not SDWA");

 AMDGPUInstructionSelector::selectVOP3PModsImpl(
   Register Src, const MachineRegisterInfo &MRI) const {
   unsigned Mods = 0;
   MachineInstr *MI = MRI.getVRegDef(Src);
 
   if (MI && MI->getOpcode() == AMDGPU::G_FNEG &&
       // It's possible to see an f32 fneg here, but unlikely.
       // TODO: Treat f32 fneg as only high bit.
-      MRI.getType(Src) == LLT::vector(2, 16)) {
+      MRI.getType(Src) == LLT::fixed_vector(2, 16)) {
     Mods ^= (SISrcMods::NEG | SISrcMods::NEG_HI);
     Src = MI->getOperand(1).getReg();
     MI = MRI.getVRegDef(Src);
   }
 
   // TODO: Match op_sel through g_build_vector_trunc and g_shuffle_vector.
 
   // Packed instructions do not have abs modifiers.

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

return [=](const LegalityQuery &Query) {
     return EltTy.getSizeInBits() == 16 && Ty.getNumElements() > 2;
   };
 }
 
 static LegalizeMutation oneMoreElement(unsigned TypeIdx) {
   return [=](const LegalityQuery &Query) {
     const LLT Ty = Query.Types[TypeIdx];
     const LLT EltTy = Ty.getElementType();
-    return std::make_pair(TypeIdx, LLT::vector(Ty.getNumElements() + 1, EltTy));
+    return std::make_pair(TypeIdx,
+                          LLT::fixed_vector(Ty.getNumElements() + 1, EltTy));
   };
 }
 
 static LegalizeMutation fewerEltsToSize64Vector(unsigned TypeIdx) {
   return [=](const LegalityQuery &Query) {
     const LLT Ty = Query.Types[TypeIdx];
     const LLT EltTy = Ty.getElementType();
     unsigned Size = Ty.getSizeInBits();
return [=](const LegalityQuery &Query) {
     const LLT EltTy = Ty.getElementType();
     const int Size = Ty.getSizeInBits();
     const int EltSize = EltTy.getSizeInBits();
     const int NextMul32 = (Size + 31) / 32;
 
     assert(EltSize < 32);
 
     const int NewNumElts = (32 * NextMul32 + EltSize - 1) / EltSize;
-    return std::make_pair(TypeIdx, LLT::vector(NewNumElts, EltTy));
+    return std::make_pair(TypeIdx, LLT::fixed_vector(NewNumElts, EltTy));
   };
 }
 
 static LLT getBitcastRegisterType(const LLT Ty) {
   const unsigned Size = Ty.getSizeInBits();
 
   LLT CoercedTy;
   if (Size <= 32) {
AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
   const LLT S16 = LLT::scalar(16);
   const LLT S32 = LLT::scalar(32);
   const LLT S64 = LLT::scalar(64);
   const LLT S128 = LLT::scalar(128);
   const LLT S256 = LLT::scalar(256);
   const LLT S512 = LLT::scalar(512);
   const LLT MaxScalar = LLT::scalar(MaxRegisterSize);
 
-  const LLT V2S8 = LLT::vector(2, 8);
-  const LLT V2S16 = LLT::vector(2, 16);
-  const LLT V4S16 = LLT::vector(4, 16);
-
-  const LLT V2S32 = LLT::vector(2, 32);
-  const LLT V3S32 = LLT::vector(3, 32);
-  const LLT V4S32 = LLT::vector(4, 32);
-  const LLT V5S32 = LLT::vector(5, 32);
-  const LLT V6S32 = LLT::vector(6, 32);
-  const LLT V7S32 = LLT::vector(7, 32);
-  const LLT V8S32 = LLT::vector(8, 32);
-  const LLT V9S32 = LLT::vector(9, 32);
-  const LLT V10S32 = LLT::vector(10, 32);
-  const LLT V11S32 = LLT::vector(11, 32);
-  const LLT V12S32 = LLT::vector(12, 32);
-  const LLT V13S32 = LLT::vector(13, 32);
-  const LLT V14S32 = LLT::vector(14, 32);
-  const LLT V15S32 = LLT::vector(15, 32);
-  const LLT V16S32 = LLT::vector(16, 32);
-  const LLT V32S32 = LLT::vector(32, 32);
-
-  const LLT V2S64 = LLT::vector(2, 64);
-  const LLT V3S64 = LLT::vector(3, 64);
-  const LLT V4S64 = LLT::vector(4, 64);
-  const LLT V5S64 = LLT::vector(5, 64);
-  const LLT V6S64 = LLT::vector(6, 64);
-  const LLT V7S64 = LLT::vector(7, 64);
-  const LLT V8S64 = LLT::vector(8, 64);
-  const LLT V16S64 = LLT::vector(16, 64);
+  const LLT V2S8 = LLT::fixed_vector(2, 8);
+  const LLT V2S16 = LLT::fixed_vector(2, 16);
+  const LLT V4S16 = LLT::fixed_vector(4, 16);
+
+  const LLT V2S32 = LLT::fixed_vector(2, 32);
+  const LLT V3S32 = LLT::fixed_vector(3, 32);
+  const LLT V4S32 = LLT::fixed_vector(4, 32);
+  const LLT V5S32 = LLT::fixed_vector(5, 32);
+  const LLT V6S32 = LLT::fixed_vector(6, 32);
+  const LLT V7S32 = LLT::fixed_vector(7, 32);
+  const LLT V8S32 = LLT::fixed_vector(8, 32);
+  const LLT V9S32 = LLT::fixed_vector(9, 32);
+  const LLT V10S32 = LLT::fixed_vector(10, 32);
+  const LLT V11S32 = LLT::fixed_vector(11, 32);
+  const LLT V12S32 = LLT::fixed_vector(12, 32);
+  const LLT V13S32 = LLT::fixed_vector(13, 32);
+  const LLT V14S32 = LLT::fixed_vector(14, 32);
+  const LLT V15S32 = LLT::fixed_vector(15, 32);
+  const LLT V16S32 = LLT::fixed_vector(16, 32);
+  const LLT V32S32 = LLT::fixed_vector(32, 32);
+
+  const LLT V2S64 = LLT::fixed_vector(2, 64);
+  const LLT V3S64 = LLT::fixed_vector(3, 64);
+  const LLT V4S64 = LLT::fixed_vector(4, 64);
+  const LLT V5S64 = LLT::fixed_vector(5, 64);
+  const LLT V6S64 = LLT::fixed_vector(6, 64);
+  const LLT V7S64 = LLT::fixed_vector(7, 64);
+  const LLT V8S64 = LLT::fixed_vector(8, 64);
+  const LLT V16S64 = LLT::fixed_vector(16, 64);
 
   std::initializer_list<LLT> AllS32Vectors =
     {V2S32, V3S32, V4S32, V5S32, V6S32, V7S32, V8S32,
      V9S32, V10S32, V11S32, V12S32, V13S32, V14S32, V15S32, V16S32, V32S32};
   std::initializer_list<LLT> AllS64Vectors =
     {V2S64, V3S64, V4S64, V5S64, V6S64, V7S64, V8S64, V16S64};
 
   const LLT GlobalPtr = GetAddrSpacePtr(AMDGPUAS::GLOBAL_ADDRESS);
Actions
                 unsigned NumPieces = Query.MMODescrs[0].SizeInBits / MaxSize;
 
                 // FIXME: Refine when odd breakdowns handled
                 // The scalars will need to be re-legalized.
                 if (NumPieces == 1 || NumPieces >= NumElts ||
                     NumElts % NumPieces != 0)
                   return std::make_pair(0, EltTy);
 
-                return std::make_pair(0,
-                                      LLT::vector(NumElts / NumPieces, EltTy));
+                return std::make_pair(
+                    0, LLT::fixed_vector(NumElts / NumPieces, EltTy));
               }
 
               // FIXME: We could probably handle weird extending loads better.
               unsigned MemSize = Query.MMODescrs[0].SizeInBits;
               if (DstTy.getSizeInBits() > MemSize)
                 return std::make_pair(0, EltTy);
 
               unsigned EltSize = EltTy.getSizeInBits();
               unsigned DstSize = DstTy.getSizeInBits();
               if (!isPowerOf2_32(DstSize)) {
                 // We're probably decomposing an odd sized store. Try to split
                 // to the widest type. TODO: Account for alignment. As-is it
                 // should be OK, since the new parts will be further legalized.
                 unsigned FloorSize = PowerOf2Floor(DstSize);
                 return std::make_pair(
                   0, LLT::scalarOrVector(FloorSize / EltSize, EltTy));
               }
 
               // Need to split because of alignment.
               unsigned Align = Query.MMODescrs[0].AlignInBits;
               if (EltSize > Align &&
                   (EltSize / Align < DstTy.getNumElements())) {
-                return std::make_pair(0, LLT::vector(EltSize / Align, EltTy));
+                return std::make_pair(
+                    0, LLT::fixed_vector(EltSize / Align, EltTy));
               }
 
               // May need relegalization for the scalars.
               return std::make_pair(0, EltTy);
             })
     .lowerIfMemSizeNotPow2()
     .minScalar(0, S32)
     .narrowScalarIf(isWideScalarExtLoadTruncStore(0), changeTo(0, S32))
getActionDefinitionsBuilder(G_ATOMIC_CMPXCHG)
     .customFor({{S32, GlobalPtr}, {S64, GlobalPtr},
                 {S32, FlatPtr}, {S64, FlatPtr}})
     .legalFor({{S32, LocalPtr}, {S64, LocalPtr},
                {S32, RegionPtr}, {S64, RegionPtr}});
   // TODO: Pointer types, any 32-bit or 64-bit vector
 
   // Condition should be s32 for scalar, s1 for vector.
   getActionDefinitionsBuilder(G_SELECT)
-    .legalForCartesianProduct({S32, S64, S16, V2S32, V2S16, V4S16,
-          GlobalPtr, LocalPtr, FlatPtr, PrivatePtr,
-          LLT::vector(2, LocalPtr), LLT::vector(2, PrivatePtr)}, {S1, S32})
+      .legalForCartesianProduct({S32, S64, S16, V2S32, V2S16, V4S16, GlobalPtr,
+                                 LocalPtr, FlatPtr, PrivatePtr,
+                                 LLT::fixed_vector(2, LocalPtr),
+                                 LLT::fixed_vector(2, PrivatePtr)},
+                                {S1, S32})
       .clampScalar(0, S16, S64)
       .scalarize(1)
       .moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
       .fewerElementsIf(numElementsNotEven(0), scalarize(0))
       .clampMaxNumElements(0, S32, 2)
       .clampMaxNumElements(0, LocalPtr, 2)
       .clampMaxNumElements(0, PrivatePtr, 2)
       .scalarize(0)
       .widenScalarToNextPow2(0)
       .legalIf(all(isPointer(0), typeInSet(1, {S1, S32})));
 
   // TODO: Only the low 4/5/6 bits of the shift amount are observed, so we can
   // be more flexible with the shift amount type.
   auto &Shifts = getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR})
     .legalFor({{S32, S32}, {S64, S32}});
   if (ST.has16BitInsts()) {
     if (ST.hasVOP3PInsts()) {
       Shifts.legalFor({{S16, S16}, {V2S16, V2S16}})
getActionDefinitionsBuilder(Op)
           // if this is scalar. If not, fall back to 32.
           const LLT EltTy = Query.Types[EltTypeIdx];
           const LLT VecTy = Query.Types[VecTypeIdx];
           const unsigned DstEltSize = EltTy.getSizeInBits();
           const unsigned VecSize = VecTy.getSizeInBits();
 
           const unsigned TargetEltSize = DstEltSize % 64 == 0 ? 64 : 32;
           return std::make_pair(
-            VecTypeIdx, LLT::vector(VecSize / TargetEltSize, TargetEltSize));
+              VecTypeIdx,
+              LLT::fixed_vector(VecSize / TargetEltSize, TargetEltSize));
         })
       .clampScalar(EltTypeIdx, S32, S64)
       .clampScalar(VecTypeIdx, S32, S64)
       .clampScalar(IdxTypeIdx, S32, S32)
       .clampMaxNumElements(VecTypeIdx, S32, 32)
       // TODO: Clamp elements for 64-bit vectors?
       // It should only be necessary with variable indexes.
       // As a last resort, lower to the stack
bool AMDGPULegalizerInfo::legalizeInsertVectorElt(
 
   MI.eraseFromParent();
   return true;
 }
 
 bool AMDGPULegalizerInfo::legalizeShuffleVector(
   MachineInstr &MI, MachineRegisterInfo &MRI,
   MachineIRBuilder &B) const {
-  const LLT V2S16 = LLT::vector(2, 16);
+  const LLT V2S16 = LLT::fixed_vector(2, 16);
 
   Register Dst = MI.getOperand(0).getReg();
   Register Src0 = MI.getOperand(1).getReg();
   LLT DstTy = MRI.getType(Dst);
   LLT SrcTy = MRI.getType(Src0);
 
   if (SrcTy == V2S16 && DstTy == V2S16 &&
       AMDGPU::isLegalVOP3PShuffleMask(MI.getOperand(3).getShuffleMask()))
bool AMDGPULegalizerInfo::legalizeAtomicCmpXChg(
   Register PtrReg = MI.getOperand(1).getReg();
   Register CmpVal = MI.getOperand(2).getReg();
   Register NewVal = MI.getOperand(3).getReg();
 
   assert(AMDGPU::isFlatGlobalAddrSpace(MRI.getType(PtrReg).getAddressSpace()) &&
          "this should not have been custom lowered");
 
   LLT ValTy = MRI.getType(CmpVal);
-  LLT VecTy = LLT::vector(2, ValTy);
+  LLT VecTy = LLT::fixed_vector(2, ValTy);
 
   Register PackedVal = B.buildBuildVector(VecTy, { NewVal, CmpVal }).getReg(0);
 
   B.buildInstr(AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG)
     .addDef(DstReg)
     .addUse(PtrReg)
     .addUse(PackedVal)
     .setMemRefs(MI.memoperands());

 }
 
 // Turn an illegal packed v2s16 build vector into bit operations.
 // TODO: This should probably be a bitcast action in LegalizerHelper.
 bool AMDGPULegalizerInfo::legalizeBuildVector(
   MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const {
   Register Dst = MI.getOperand(0).getReg();
   const LLT S32 = LLT::scalar(32);
-  assert(MRI.getType(Dst) == LLT::vector(2, 16));
+  assert(MRI.getType(Dst) == LLT::fixed_vector(2, 16));
 
   Register Src0 = MI.getOperand(1).getReg();
   Register Src1 = MI.getOperand(2).getReg();
   assert(MRI.getType(Src0) == LLT::scalar(16));
 
   auto Merge = B.buildMerge(S32, {Src0, Src1});
   B.buildBitcast(Dst, Merge);
 
if (ST.hasUnpackedD16VMem()) {
     auto Unmerge = B.buildUnmerge(S16, Reg);
 
     SmallVector<Register, 4> WideRegs;
     for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I)
       WideRegs.push_back(B.buildAnyExt(S32, Unmerge.getReg(I)).getReg(0));
 
     int NumElts = StoreVT.getNumElements();
 
-    return B.buildBuildVector(LLT::vector(NumElts, S32), WideRegs).getReg(0);
+    return B.buildBuildVector(LLT::fixed_vector(NumElts, S32), WideRegs)
+        .getReg(0);
   }
 
   if (ImageStore && ST.hasImageStoreD16Bug()) {
     if (StoreVT.getNumElements() == 2) {
       SmallVector<Register, 4> PackedRegs;
       Reg = B.buildBitcast(S32, Reg).getReg(0);
       PackedRegs.push_back(Reg);
       PackedRegs.resize(2, B.buildUndef(S32).getReg(0));
-      return B.buildBuildVector(LLT::vector(2, S32), PackedRegs).getReg(0);
+      return B.buildBuildVector(LLT::fixed_vector(2, S32), PackedRegs)
+          .getReg(0);
     }
 
     if (StoreVT.getNumElements() == 3) {
       SmallVector<Register, 4> PackedRegs;
       auto Unmerge = B.buildUnmerge(S16, Reg);
       for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I)
         PackedRegs.push_back(Unmerge.getReg(I));
       PackedRegs.resize(6, B.buildUndef(S16).getReg(0));
-      Reg = B.buildBuildVector(LLT::vector(6, S16), PackedRegs).getReg(0);
-      return B.buildBitcast(LLT::vector(3, S32), Reg).getReg(0);
+      Reg = B.buildBuildVector(LLT::fixed_vector(6, S16), PackedRegs).getReg(0);
+      return B.buildBitcast(LLT::fixed_vector(3, S32), Reg).getReg(0);
     }
 
     if (StoreVT.getNumElements() == 4) {
       SmallVector<Register, 4> PackedRegs;
-      Reg = B.buildBitcast(LLT::vector(2, S32), Reg).getReg(0);
+      Reg = B.buildBitcast(LLT::fixed_vector(2, S32), Reg).getReg(0);
       auto Unmerge = B.buildUnmerge(S32, Reg);
       for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I)
         PackedRegs.push_back(Unmerge.getReg(I));
       PackedRegs.resize(4, B.buildUndef(S32).getReg(0));
-      return B.buildBuildVector(LLT::vector(4, S32), PackedRegs).getReg(0);
+      return B.buildBuildVector(LLT::fixed_vector(4, S32), PackedRegs)
+          .getReg(0);
     }
 
     llvm_unreachable("invalid data type");
   }
 
   return Reg;
 }
 

 /// Turn a set of s16 typed registers in \p AddrRegs into a dword sized
 /// vector with s16 typed elements.
 static void packImage16bitOpsToDwords(MachineIRBuilder &B, MachineInstr &MI,
                                       SmallVectorImpl<Register> &PackedAddrs,
                                       unsigned ArgOffset,
                                       const AMDGPU::ImageDimIntrinsicInfo *Intr,
                                       bool IsA16, bool IsG16) {
   const LLT S16 = LLT::scalar(16);
-  const LLT V2S16 = LLT::vector(2, 16);
+  const LLT V2S16 = LLT::fixed_vector(2, 16);
   auto EndIdx = Intr->VAddrEnd;
 
   for (unsigned I = Intr->VAddrStart; I < EndIdx; I++) {
     MachineOperand &SrcOp = MI.getOperand(ArgOffset + I);
     if (!SrcOp.isReg())
       continue; // _L to _LZ may have eliminated this.
 
     Register AddrReg = SrcOp.getReg();
if (NumAddrRegs != 1) {
     // FIXME: Missing intermediate sized register classes and instructions.
     if (NumAddrRegs > 4 && !isPowerOf2_32(NumAddrRegs)) {
       const int RoundedNumRegs = NextPowerOf2(NumAddrRegs);
       auto Undef = B.buildUndef(S32);
       AddrRegs.append(RoundedNumRegs - NumAddrRegs, Undef.getReg(0));
       NumAddrRegs = RoundedNumRegs;
     }
 
-    auto VAddr = B.buildBuildVector(LLT::vector(NumAddrRegs, 32), AddrRegs);
+    auto VAddr =
+        B.buildBuildVector(LLT::fixed_vector(NumAddrRegs, 32), AddrRegs);
     MI.getOperand(DimIdx).setReg(VAddr.getReg(0));
   }
 
   for (int I = 1; I != NumVAddrs; ++I) {
     MachineOperand &SrcOp = MI.getOperand(DimIdx + I);
     if (SrcOp.isReg())
       MI.getOperand(DimIdx + I).setReg(AMDGPU::NoRegister);
   }
bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
 
   // TODO: Do we need to guard against already legalized intrinsics?
   const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
       AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode);
 
   MachineRegisterInfo *MRI = B.getMRI();
   const LLT S32 = LLT::scalar(32);
   const LLT S16 = LLT::scalar(16);
-  const LLT V2S16 = LLT::vector(2, 16);
+  const LLT V2S16 = LLT::fixed_vector(2, 16);
 
   unsigned DMask = 0;
 
   // Check for 16 bit addresses and pack if true.
   LLT GradTy =
       MRI->getType(MI.getOperand(ArgOffset + Intr->GradientStart).getReg());
   LLT AddrTy =
       MRI->getType(MI.getOperand(ArgOffset + Intr->CoordStart).getReg());
if (BaseOpcode->Atomic) {
 
     // TODO: Allow atomic swap and bit ops for v2s16/v4s16
     if (Ty.isVector())
       return false;
 
     if (BaseOpcode->AtomicX2) {
       Register VData1 = MI.getOperand(3).getReg();
       // The two values are packed in one register.
-      LLT PackedTy = LLT::vector(2, Ty);
+      LLT PackedTy = LLT::fixed_vector(2, Ty);
       auto Concat = B.buildBuildVector(PackedTy, {VData0, VData1});
       MI.getOperand(2).setReg(Concat.getReg(0));
       MI.getOperand(3).setReg(AMDGPU::NoRegister);
     }
   }
 
   unsigned CorrectedNumVAddrs = Intr->NumVAddrs;
 
if (Intr->NumVAddrs > 1) {
 
       packImage16bitOpsToDwords(B, MI, PackedRegs, ArgOffset, Intr, IsA16,
                                 IsG16);
 
       // See also below in the non-a16 branch
       const bool UseNSA = PackedRegs.size() >= 3 && ST.hasNSAEncoding();
 
       if (!UseNSA && PackedRegs.size() > 1) {
-        LLT PackedAddrTy = LLT::vector(2 * PackedRegs.size(), 16);
+        LLT PackedAddrTy = LLT::fixed_vector(2 * PackedRegs.size(), 16);
         auto Concat = B.buildConcatVectors(PackedAddrTy, PackedRegs);
         PackedRegs[0] = Concat.getReg(0);
         PackedRegs.resize(1);
       }
 
       const unsigned NumPacked = PackedRegs.size();
       for (unsigned I = Intr->VAddrStart; I < Intr->VAddrEnd; I++) {
         MachineOperand &SrcOp = MI.getOperand(ArgOffset + I);
bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
   // S32 vector to to cover all data, plus TFE result element.
   LLT TFETy;
 
   // Register type to use for each loaded component. Will be S32 or V2S16.
   LLT RegTy;
 
   if (IsD16 && ST.hasUnpackedD16VMem()) {
     RoundedTy = LLT::scalarOrVector(AdjustedNumElts, 32);
-    TFETy = LLT::vector(AdjustedNumElts + 1, 32);
+    TFETy = LLT::fixed_vector(AdjustedNumElts + 1, 32);
     RegTy = S32;
   } else {
     unsigned EltSize = EltTy.getSizeInBits();
     unsigned RoundedElts = (AdjustedTy.getSizeInBits() + 31) / 32;
     unsigned RoundedSize = 32 * RoundedElts;
     RoundedTy = LLT::scalarOrVector(RoundedSize / EltSize, EltSize);
-    TFETy = LLT::vector(RoundedSize / 32 + 1, S32);
+    TFETy = LLT::fixed_vector(RoundedSize / 32 + 1, S32);
     RegTy = !IsTFE && EltSize == 16 ? V2S16 : S32;
   }
 
   // The return type does not need adjustment.
   // TODO: Should we change s16 case to s32 or <2 x s16>?
   if (!IsTFE && (RoundedTy == Ty || !Ty.isVector()))
     return true;
 
if (!ResTy.isVector()) {
     B.buildBuildVector(DstReg, ResultRegs);
     return true;
   }
 
   assert(!ST.hasUnpackedD16VMem() && ResTy == V2S16);
   const int RegsToCover = (Ty.getSizeInBits() + 31) / 32;
 
   // Deal with the one annoying legal case.
-  const LLT V3S16 = LLT::vector(3, 16);
+  const LLT V3S16 = LLT::fixed_vector(3, 16);
   if (Ty == V3S16) {
     padWithUndef(ResTy, RegsToCover - ResultRegs.size() + 1);
-    auto Concat = B.buildConcatVectors(LLT::vector(6, 16), ResultRegs);
+    auto Concat = B.buildConcatVectors(LLT::fixed_vector(6, 16), ResultRegs);
     B.buildUnmerge({DstReg, MRI->createGenericVirtualRegister(V3S16)}, Concat);
     return true;
   }
 
   padWithUndef(ResTy, RegsToCover - ResultRegs.size());
   B.buildConcatVectors(DstReg, ResultRegs);
   return true;
 }

llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp

void AMDGPUPreLegalizerCombinerHelper::applyClampI64ToI16(
 
   B.setMBB(*MI.getParent());
   B.setInstrAndDebugLoc(MI);
 
   auto Unmerge = B.buildUnmerge(S32, Src);
 
   assert(MI.getOpcode() != AMDGPU::G_AMDGPU_CVT_PK_I16_I32);
 
-  const LLT V2S16 = LLT::vector(2, 16);
+  const LLT V2S16 = LLT::fixed_vector(2, 16);
   auto CvtPk =
       B.buildInstr(AMDGPU::G_AMDGPU_CVT_PK_I16_I32, {V2S16},
                    {Unmerge.getReg(0), Unmerge.getReg(1)}, MI.getFlags());
 
   auto MinBoundary = std::min(MatchInfo.Cmp1, MatchInfo.Cmp2);
   auto MaxBoundary = std::max(MatchInfo.Cmp1, MatchInfo.Cmp2);
   auto MinBoundaryDst = B.buildConstant(S32, MinBoundary);
   auto MaxBoundaryDst = B.buildConstant(S32, MaxBoundary);

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

 }
 
 static LLT widen96To128(LLT Ty) {
   if (!Ty.isVector())
     return LLT::scalar(128);
 
   LLT EltTy = Ty.getElementType();
   assert(128 % EltTy.getSizeInBits() == 0);
-  return LLT::vector(128 / EltTy.getSizeInBits(), EltTy);
+  return LLT::fixed_vector(128 / EltTy.getSizeInBits(), EltTy);
 }
 
 bool AMDGPURegisterBankInfo::applyMappingLoad(MachineInstr &MI,
                         const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper,
                                               MachineRegisterInfo &MRI) const {
   Register DstReg = MI.getOperand(0).getReg();
   const LLT LoadTy = MRI.getType(DstReg);
   unsigned LoadSize = LoadTy.getSizeInBits();
Register AMDGPURegisterBankInfo::handleD16VData(MachineIRBuilder &B,
 
   SmallVector<Register, 4> WideRegs;
   for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I)
     WideRegs.push_back(Unmerge.getReg(I));
 
   const LLT S32 = LLT::scalar(32);
   int NumElts = StoreVT.getNumElements();
 
-  return B.buildMerge(LLT::vector(NumElts, S32), WideRegs).getReg(0);
+  return B.buildMerge(LLT::fixed_vector(NumElts, S32), WideRegs).getReg(0);
 }
 
 static std::pair<Register, unsigned>
 getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg) {
   int64_t Const;
   if (mi_match(Reg, MRI, m_ICst(Const)))
     return std::make_pair(Register(), Const);
 
for (unsigned L = 0; L < NumLanes; ++L) {
 
       Register Select = B.buildSelect(EltTy, Cmp, Op0, Op1).getReg(0);
       MRI.setRegBank(Select, DstBank);
 
       Ops[I * NumLanes + L] = Select;
     }
   }
 
-  LLT MergeTy = LLT::vector(Ops.size(), EltTy);
+  LLT MergeTy = LLT::fixed_vector(Ops.size(), EltTy);
   if (MergeTy == MRI.getType(MI.getOperand(0).getReg())) {
     B.buildBuildVector(MI.getOperand(0), Ops);
   } else {
     auto Vec = B.buildBuildVector(MergeTy, Ops);
     MRI.setRegBank(Vec->getOperand(0).getReg(), DstBank);
     B.buildBitcast(MI.getOperand(0).getReg(), Vec);
   }
 
void AMDGPURegisterBankInfo::applyMappingImpl(
   case AMDGPU::G_SMAX:
   case AMDGPU::G_UMIN:
   case AMDGPU::G_UMAX: {
     Register DstReg = MI.getOperand(0).getReg();
     LLT DstTy = MRI.getType(DstReg);
 
     // 16-bit operations are VALU only, but can be promoted to 32-bit SALU.
     // Packed 16-bit operations need to be scalarized and promoted.
-    if (DstTy != LLT::scalar(16) && DstTy != LLT::vector(2, 16))
+    if (DstTy != LLT::scalar(16) && DstTy != LLT::fixed_vector(2, 16))
       break;
 
     const RegisterBank *DstBank =
       OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
     if (DstBank == &AMDGPU::VGPRRegBank)
       break;
 
     const LLT S32 = LLT::scalar(32);
case AMDGPU::G_ANYEXT: {
     }
 
     break;
   }
   case AMDGPU::G_BUILD_VECTOR:
   case AMDGPU::G_BUILD_VECTOR_TRUNC: {
     Register DstReg = MI.getOperand(0).getReg();
     LLT DstTy = MRI.getType(DstReg);
-    if (DstTy != LLT::vector(2, 16))
+    if (DstTy != LLT::fixed_vector(2, 16))
       break;
 
     assert(MI.getNumOperands() == 3 && OpdMapper.getVRegs(0).empty());
     substituteSimpleCopyRegs(OpdMapper, 1);
     substituteSimpleCopyRegs(OpdMapper, 2);
 
     const RegisterBank *DstBank =
       OpdMapper.getInstrMapping().getOperandMapping(0).BreakDown[0].RegBank;
if (DstRegs.empty()) {
       if (ShouldMoveIndexIntoLoop)
         reinsertVectorIndexAdd(B, MI, 2, ConstOffset);
 
       return;
     }
 
     assert(DstTy.getSizeInBits() == 64);
 
-    LLT Vec32 = LLT::vector(2 * SrcTy.getNumElements(), 32);
+    LLT Vec32 = LLT::fixed_vector(2 * SrcTy.getNumElements(), 32);
 
     auto CastSrc = B.buildBitcast(Vec32, SrcReg);
     auto One = B.buildConstant(S32, 1);
 
     MachineBasicBlock::iterator MII = MI.getIterator();
 
     // Split the vector index into 32-bit pieces. Prepare to move all of the
     // new instructions into a waterfall loop if necessary.
if (InsRegs.empty()) {
 
       return;
     }
 
 
     assert(InsTy.getSizeInBits() == 64);
 
     const LLT S32 = LLT::scalar(32);
-    LLT Vec32 = LLT::vector(2 * VecTy.getNumElements(), 32);
+    LLT Vec32 = LLT::fixed_vector(2 * VecTy.getNumElements(), 32);
 
     MachineIRBuilder B(MI);
     auto CastSrc = B.buildBitcast(Vec32, SrcReg);
     auto One = B.buildConstant(S32, 1);
 
     // Split the vector index into 32-bit pieces. Prepare to move all of the
     // new instructions into a waterfall loop if necessary.
     //
case AMDGPU::G_EXTRACT: {
     OpdsMapping[0] = AMDGPU::getValueMapping(BankID, DstSize);
     OpdsMapping[1] = AMDGPU::getValueMapping(BankID, SrcSize);
     OpdsMapping[2] = nullptr;
     break;
   }
   case AMDGPU::G_BUILD_VECTOR:
   case AMDGPU::G_BUILD_VECTOR_TRUNC: {
     LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
-    if (DstTy == LLT::vector(2, 16)) {
+    if (DstTy == LLT::fixed_vector(2, 16)) {
       unsigned DstSize = DstTy.getSizeInBits();
       unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
       unsigned Src0BankID = getRegBankID(MI.getOperand(1).getReg(), MRI);
       unsigned Src1BankID = getRegBankID(MI.getOperand(2).getReg(), MRI);
       unsigned DstBankID = regBankUnion(Src0BankID, Src1BankID);
 
       OpdsMapping[0] = AMDGPU::getValueMapping(DstBankID, DstSize);
       OpdsMapping[1] = AMDGPU::getValueMapping(Src0BankID, SrcSize);

llvm/lib/Target/Mips/MipsLegalizerInfo.cpp

 }
 
 MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
   using namespace TargetOpcode;
 
   const LLT s1 = LLT::scalar(1);
   const LLT s32 = LLT::scalar(32);
   const LLT s64 = LLT::scalar(64);
-  const LLT v16s8 = LLT::vector(16, 8);
-  const LLT v8s16 = LLT::vector(8, 16);
-  const LLT v4s32 = LLT::vector(4, 32);
-  const LLT v2s64 = LLT::vector(2, 64);
+  const LLT v16s8 = LLT::fixed_vector(16, 8);
+  const LLT v8s16 = LLT::fixed_vector(8, 16);
+  const LLT v4s32 = LLT::fixed_vector(4, 32);
+  const LLT v2s64 = LLT::fixed_vector(2, 64);
   const LLT p0 = LLT::pointer(0, 32);
 
   getActionDefinitionsBuilder({G_ADD, G_SUB, G_MUL})
       .legalIf([=, &ST](const LegalityQuery &Query) {
         if (CheckTyN(0, Query, {s32}))
           return true;
         if (ST.hasMSA() && CheckTyN(0, Query, {v16s8, v8s16, v4s32, v2s64}))
           return true;

llvm/lib/Target/X86/X86LegalizerInfo.cpp

 }
 
 void X86LegalizerInfo::setLegalizerInfoSSE1() {
   if (!Subtarget.hasSSE1())
     return;
 
   const LLT s32 = LLT::scalar(32);
   const LLT s64 = LLT::scalar(64);
-  const LLT v4s32 = LLT::vector(4, 32);
-  const LLT v2s64 = LLT::vector(2, 64);
+  const LLT v4s32 = LLT::fixed_vector(4, 32);
+  const LLT v2s64 = LLT::fixed_vector(2, 64);
 
   auto &LegacyInfo = getLegacyLegalizerInfo();
 
   for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
     for (auto Ty : {s32, v4s32})
       LegacyInfo.setAction({BinOp, Ty}, LegacyLegalizeActions::Legal);
 
   for (unsigned MemOp : {G_LOAD, G_STORE})

 }
 
 void X86LegalizerInfo::setLegalizerInfoSSE2() {
   if (!Subtarget.hasSSE2())
     return;
 
   const LLT s32 = LLT::scalar(32);
   const LLT s64 = LLT::scalar(64);
-  const LLT v16s8 = LLT::vector(16, 8);
-  const LLT v8s16 = LLT::vector(8, 16);
-  const LLT v4s32 = LLT::vector(4, 32);
-  const LLT v2s64 = LLT::vector(2, 64);
-
-  const LLT v32s8 = LLT::vector(32, 8);
-  const LLT v16s16 = LLT::vector(16, 16);
-  const LLT v8s32 = LLT::vector(8, 32);
-  const LLT v4s64 = LLT::vector(4, 64);
+  const LLT v16s8 = LLT::fixed_vector(16, 8);
+  const LLT v8s16 = LLT::fixed_vector(8, 16);
+  const LLT v4s32 = LLT::fixed_vector(4, 32);
+  const LLT v2s64 = LLT::fixed_vector(2, 64);
+
+  const LLT v32s8 = LLT::fixed_vector(32, 8);
+  const LLT v16s16 = LLT::fixed_vector(16, 16);
+  const LLT v8s32 = LLT::fixed_vector(8, 32);
+  const LLT v4s64 = LLT::fixed_vector(4, 64);
 
   auto &LegacyInfo = getLegacyLegalizerInfo();
 
   for (unsigned BinOp : {G_FADD, G_FSUB, G_FMUL, G_FDIV})
     for (auto Ty : {s64, v2s64})
       LegacyInfo.setAction({BinOp, Ty}, LegacyLegalizeActions::Legal);
 
   for (unsigned BinOp : {G_ADD, G_SUB})
for (const auto &Ty : {v16s8, v8s16, v4s32, v2s64}) {
     LegacyInfo.setAction({G_UNMERGE_VALUES, Ty}, LegacyLegalizeActions::Legal);
   }
 }
 
 void X86LegalizerInfo::setLegalizerInfoSSE41() {
   if (!Subtarget.hasSSE41())
     return;
 
-  const LLT v4s32 = LLT::vector(4, 32);
+  const LLT v4s32 = LLT::fixed_vector(4, 32);
 
   auto &LegacyInfo = getLegacyLegalizerInfo();
 
   LegacyInfo.setAction({G_MUL, v4s32}, LegacyLegalizeActions::Legal);
 }
 
 void X86LegalizerInfo::setLegalizerInfoAVX() {
   if (!Subtarget.hasAVX())
     return;
 
-  const LLT v16s8 = LLT::vector(16, 8);
-  const LLT v8s16 = LLT::vector(8, 16);
-  const LLT v4s32 = LLT::vector(4, 32);
-  const LLT v2s64 = LLT::vector(2, 64);
-
-  const LLT v32s8 = LLT::vector(32, 8);
-  const LLT v64s8 = LLT::vector(64, 8);
-  const LLT v16s16 = LLT::vector(16, 16);
-  const LLT v32s16 = LLT::vector(32, 16);
-  const LLT v8s32 = LLT::vector(8, 32);
-  const LLT v16s32 = LLT::vector(16, 32);
-  const LLT v4s64 = LLT::vector(4, 64);
-  const LLT v8s64 = LLT::vector(8, 64);
+  const LLT v16s8 = LLT::fixed_vector(16, 8);
+  const LLT v8s16 = LLT::fixed_vector(8, 16);
+  const LLT v4s32 = LLT::fixed_vector(4, 32);
+  const LLT v2s64 = LLT::fixed_vector(2, 64);
+
+  const LLT v32s8 = LLT::fixed_vector(32, 8);
+  const LLT v64s8 = LLT::fixed_vector(64, 8);
+  const LLT v16s16 = LLT::fixed_vector(16, 16);
+  const LLT v32s16 = LLT::fixed_vector(32, 16);
+  const LLT v8s32 = LLT::fixed_vector(8, 32);
+  const LLT v16s32 = LLT::fixed_vector(16, 32);
+  const LLT v4s64 = LLT::fixed_vector(4, 64);
+  const LLT v8s64 = LLT::fixed_vector(8, 64);
 
   auto &LegacyInfo = getLegacyLegalizerInfo();
 
   for (unsigned MemOp : {G_LOAD, G_STORE})
     for (auto Ty : {v8s32, v4s64})
       LegacyInfo.setAction({MemOp, Ty}, LegacyLegalizeActions::Legal);
 
   for (auto Ty : {v32s8, v16s16, v8s32, v4s64}) {
for (const auto &Ty :
     LegacyInfo.setAction({G_UNMERGE_VALUES, Ty}, LegacyLegalizeActions::Legal);
   }
 }
 
 void X86LegalizerInfo::setLegalizerInfoAVX2() {
   if (!Subtarget.hasAVX2())
     return;
 
-  const LLT v32s8 = LLT::vector(32, 8);
-  const LLT v16s16 = LLT::vector(16, 16);
-  const LLT v8s32 = LLT::vector(8, 32);
-  const LLT v4s64 = LLT::vector(4, 64);
-
-  const LLT v64s8 = LLT::vector(64, 8);
-  const LLT v32s16 = LLT::vector(32, 16);
-  const LLT v16s32 = LLT::vector(16, 32);
-  const LLT v8s64 = LLT::vector(8, 64);
+  const LLT v32s8 = LLT::fixed_vector(32, 8);
+  const LLT v16s16 = LLT::fixed_vector(16, 16);
+  const LLT v8s32 = LLT::fixed_vector(8, 32);
+  const LLT v4s64 = LLT::fixed_vector(4, 64);
+
+  const LLT v64s8 = LLT::fixed_vector(64, 8);
+  const LLT v32s16 = LLT::fixed_vector(32, 16);
+  const LLT v16s32 = LLT::fixed_vector(16, 32);
+  const LLT v8s64 = LLT::fixed_vector(8, 64);
 
   auto &LegacyInfo = getLegacyLegalizerInfo();
 
   for (unsigned BinOp : {G_ADD, G_SUB})
     for (auto Ty : {v32s8, v16s16, v8s32, v4s64})
       LegacyInfo.setAction({BinOp, Ty}, LegacyLegalizeActions::Legal);
 
   for (auto Ty : {v16s16, v8s32})
for (const auto &Ty : {v32s8, v16s16, v8s32, v4s64}) {
     LegacyInfo.setAction({G_UNMERGE_VALUES, Ty}, LegacyLegalizeActions::Legal);
   }
 }
 
 void X86LegalizerInfo::setLegalizerInfoAVX512() {
   if (!Subtarget.hasAVX512())
     return;
 
-  const LLT v16s8 = LLT::vector(16, 8);
-  const LLT v8s16 = LLT::vector(8, 16);
-  const LLT v4s32 = LLT::vector(4, 32);
-  const LLT v2s64 = LLT::vector(2, 64);
-
-  const LLT v32s8 = LLT::vector(32, 8);
-  const LLT v16s16 = LLT::vector(16, 16);
-  const LLT v8s32 = LLT::vector(8, 32);
-  const LLT v4s64 = LLT::vector(4, 64);
-
-  const LLT v64s8 = LLT::vector(64, 8);
-  const LLT v32s16 = LLT::vector(32, 16);
-  const LLT v16s32 = LLT::vector(16, 32);
-  const LLT v8s64 = LLT::vector(8, 64);
+  const LLT v16s8 = LLT::fixed_vector(16, 8);
+  const LLT v8s16 = LLT::fixed_vector(8, 16);
+  const LLT v4s32 = LLT::fixed_vector(4, 32);
+  const LLT v2s64 = LLT::fixed_vector(2, 64);
+
+  const LLT v32s8 = LLT::fixed_vector(32, 8);
+  const LLT v16s16 = LLT::fixed_vector(16, 16);
+  const LLT v8s32 = LLT::fixed_vector(8, 32);
+  const LLT v4s64 = LLT::fixed_vector(4, 64);
+
+  const LLT v64s8 = LLT::fixed_vector(64, 8);
+  const LLT v32s16 = LLT::fixed_vector(32, 16);
+  const LLT v16s32 = LLT::fixed_vector(16, 32);
+  const LLT v8s64 = LLT::fixed_vector(8, 64);
 
   auto &LegacyInfo = getLegacyLegalizerInfo();
 
   for (unsigned BinOp : {G_ADD, G_SUB})
     for (auto Ty : {v16s32, v8s64})
       LegacyInfo.setAction({BinOp, Ty}, LegacyLegalizeActions::Legal);
 
   LegacyInfo.setAction({G_MUL, v16s32}, LegacyLegalizeActions::Legal);
void X86LegalizerInfo::setLegalizerInfoAVX512() {
   for (auto Ty : {v4s32, v8s32})
     LegacyInfo.setAction({G_MUL, Ty}, LegacyLegalizeActions::Legal);
 }
 
 void X86LegalizerInfo::setLegalizerInfoAVX512DQ() {
   if (!(Subtarget.hasAVX512() && Subtarget.hasDQI()))
     return;
 
-  const LLT v8s64 = LLT::vector(8, 64);
+  const LLT v8s64 = LLT::fixed_vector(8, 64);
 
   auto &LegacyInfo = getLegacyLegalizerInfo();
 
   LegacyInfo.setAction({G_MUL, v8s64}, LegacyLegalizeActions::Legal);
 
   /************ VLX *******************/
   if (!Subtarget.hasVLX())
     return;
 
-  const LLT v2s64 = LLT::vector(2, 64);
-  const LLT v4s64 = LLT::vector(4, 64);
+  const LLT v2s64 = LLT::fixed_vector(2, 64);
+  const LLT v4s64 = LLT::fixed_vector(4, 64);
 
   for (auto Ty : {v2s64, v4s64})
     LegacyInfo.setAction({G_MUL, Ty}, LegacyLegalizeActions::Legal);
 }
 
 void X86LegalizerInfo::setLegalizerInfoAVX512BW() {
   if (!(Subtarget.hasAVX512() && Subtarget.hasBWI()))
     return;
 
-  const LLT v64s8 = LLT::vector(64, 8);
-  const LLT v32s16 = LLT::vector(32, 16);
+  const LLT v64s8 = LLT::fixed_vector(64, 8);
+  const LLT v32s16 = LLT::fixed_vector(32, 16);
 
   auto &LegacyInfo = getLegacyLegalizerInfo();
 
   for (unsigned BinOp : {G_ADD, G_SUB})
     for (auto Ty : {v64s8, v32s16})
       LegacyInfo.setAction({BinOp, Ty}, LegacyLegalizeActions::Legal);
 
   LegacyInfo.setAction({G_MUL, v32s16}, LegacyLegalizeActions::Legal);
 
   /************ VLX *******************/
   if (!Subtarget.hasVLX())
     return;
 
-  const LLT v8s16 = LLT::vector(8, 16);
-  const LLT v16s16 = LLT::vector(16, 16);
+  const LLT v8s16 = LLT::fixed_vector(8, 16);
+  const LLT v16s16 = LLT::fixed_vector(16, 16);
 
   for (auto Ty : {v8s16, v16s16})
     LegacyInfo.setAction({G_MUL, Ty}, LegacyLegalizeActions::Legal);
 }

llvm/unittests/CodeGen/GlobalISel/CSETest.cpp

TEST_F(AArch64GISelMITest, TestCSE) {
   // Try out building FCONSTANTs.
   auto MIBFP0 = CSEB.buildFConstant(s32, 1.0);
   auto MIBFP0_1 = CSEB.buildFConstant(s32, 1.0);
   EXPECT_TRUE(&*MIBFP0 == &*MIBFP0_1);
   CSEInfo.print();
 
   // Make sure buildConstant with a vector type doesn't crash, and the elements
   // CSE.
-  auto Splat0 = CSEB.buildConstant(LLT::vector(2, s32), 0);
+  auto Splat0 = CSEB.buildConstant(LLT::fixed_vector(2, s32), 0);
   EXPECT_EQ(TargetOpcode::G_BUILD_VECTOR, Splat0->getOpcode());
   EXPECT_EQ(Splat0.getReg(1), Splat0.getReg(2));
   EXPECT_EQ(&*MIBCst, MRI->getVRegDef(Splat0.getReg(1)));
 
-  auto FSplat = CSEB.buildFConstant(LLT::vector(2, s32), 1.0);
+  auto FSplat = CSEB.buildFConstant(LLT::fixed_vector(2, s32), 1.0);
   EXPECT_EQ(TargetOpcode::G_BUILD_VECTOR, FSplat->getOpcode());
   EXPECT_EQ(FSplat.getReg(1), FSplat.getReg(2));
   EXPECT_EQ(&*MIBFP0, MRI->getVRegDef(FSplat.getReg(1)));
 
   // Check G_UNMERGE_VALUES
   auto MIBUnmerge = CSEB.buildUnmerge({s32, s32}, Copies[0]);
   auto MIBUnmerge2 = CSEB.buildUnmerge({s32, s32}, Copies[0]);
   EXPECT_TRUE(&*MIBUnmerge == &*MIBUnmerge2);

llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp

 static const LLT S1 = LLT::scalar(1);
 static const LLT S8 = LLT::scalar(8);
 static const LLT S16 = LLT::scalar(16);
 static const LLT S32 = LLT::scalar(32);
 static const LLT S64 = LLT::scalar(64);
 static const LLT P0 = LLT::pointer(0, 64);
 static const LLT P1 = LLT::pointer(1, 32);
 
-static const LLT V2S8 = LLT::vector(2, 8);
-static const LLT V4S8 = LLT::vector(4, 8);
-static const LLT V8S8 = LLT::vector(8, 8);
-
-static const LLT V2S16 = LLT::vector(2, 16);
-static const LLT V3S16 = LLT::vector(3, 16);
-static const LLT V4S16 = LLT::vector(4, 16);
-
-static const LLT V2S32 = LLT::vector(2, 32);
-static const LLT V3S32 = LLT::vector(3, 32);
-static const LLT V4S32 = LLT::vector(4, 32);
-static const LLT V6S32 = LLT::vector(6, 32);
-
-static const LLT V2S64 = LLT::vector(2, 64);
-static const LLT V3S64 = LLT::vector(3, 64);
-static const LLT V4S64 = LLT::vector(4, 64);
-
-static const LLT V2P0 = LLT::vector(2, P0);
-static const LLT V3P0 = LLT::vector(3, P0);
-static const LLT V4P0 = LLT::vector(4, P0);
-static const LLT V6P0 = LLT::vector(6, P0);
+static const LLT V2S8 = LLT::fixed_vector(2, 8);
+static const LLT V4S8 = LLT::fixed_vector(4, 8);
+static const LLT V8S8 = LLT::fixed_vector(8, 8);
+
+static const LLT V2S16 = LLT::fixed_vector(2, 16);
+static const LLT V3S16 = LLT::fixed_vector(3, 16);
+static const LLT V4S16 = LLT::fixed_vector(4, 16);
+
+static const LLT V2S32 = LLT::fixed_vector(2, 32);
+static const LLT V3S32 = LLT::fixed_vector(3, 32);
+static const LLT V4S32 = LLT::fixed_vector(4, 32);
+static const LLT V6S32 = LLT::fixed_vector(6, 32);
+
+static const LLT V2S64 = LLT::fixed_vector(2, 64);
+static const LLT V3S64 = LLT::fixed_vector(3, 64);
+static const LLT V4S64 = LLT::fixed_vector(4, 64);
+
+static const LLT V2P0 = LLT::fixed_vector(2, P0);
+static const LLT V3P0 = LLT::fixed_vector(3, P0);
+static const LLT V4P0 = LLT::fixed_vector(4, P0);
+static const LLT V6P0 = LLT::fixed_vector(6, P0);
 
-static const LLT V2P1 = LLT::vector(2, P1);
-static const LLT V4P1 = LLT::vector(4, P1);
+static const LLT V2P1 = LLT::fixed_vector(2, P1);
+static const LLT V4P1 = LLT::fixed_vector(4, P1);
 
 TEST(GISelUtilsTest, getGCDType) {
   EXPECT_EQ(S1, getGCDType(S1, S1));
   EXPECT_EQ(S32, getGCDType(S32, S32));
   EXPECT_EQ(S1, getGCDType(S1, S32));
   EXPECT_EQ(S1, getGCDType(S32, S1));
   EXPECT_EQ(S16, getGCDType(S16, S32));
   EXPECT_EQ(S16, getGCDType(S32, S16));
TEST(GISelUtilsTest, getGCDType) {
 
   EXPECT_EQ(V2S16, getGCDType(V2S16, V2S32));
   EXPECT_EQ(S32, getGCDType(V2S32, V2S16));
 
   EXPECT_EQ(V4S8, getGCDType(V4S8, V2S32));
   EXPECT_EQ(S32, getGCDType(V2S32, V4S8));
 
   // Test cases where neither element type nicely divides.
-  EXPECT_EQ(LLT::scalar(3), getGCDType(LLT::vector(3, 5), LLT::vector(2, 6)));
-  EXPECT_EQ(LLT::scalar(3), getGCDType(LLT::vector(2, 6), LLT::vector(3, 5)));
+  EXPECT_EQ(LLT::scalar(3),
+            getGCDType(LLT::fixed_vector(3, 5), LLT::fixed_vector(2, 6)));
+  EXPECT_EQ(LLT::scalar(3),
+            getGCDType(LLT::fixed_vector(2, 6), LLT::fixed_vector(3, 5)));
 
   // Have to go smaller than a pointer element.
-  EXPECT_EQ(LLT::scalar(3), getGCDType(LLT::vector(2, LLT::pointer(3, 6)),
-                                       LLT::vector(3, 5)));
-  EXPECT_EQ(LLT::scalar(3), getGCDType(LLT::vector(3, 5),
-                                       LLT::vector(2, LLT::pointer(3, 6))));
+  EXPECT_EQ(LLT::scalar(3), getGCDType(LLT::fixed_vector(2, LLT::pointer(3, 6)),
+                                       LLT::fixed_vector(3, 5)));
+  EXPECT_EQ(LLT::scalar(3),
+            getGCDType(LLT::fixed_vector(3, 5),
+                       LLT::fixed_vector(2, LLT::pointer(3, 6))));
 
   EXPECT_EQ(V4S8, getGCDType(V4S8, S32));
   EXPECT_EQ(S32, getGCDType(S32, V4S8));
   EXPECT_EQ(V4S8, getGCDType(V4S8, P1));
   EXPECT_EQ(P1, getGCDType(P1, V4S8));
 
   EXPECT_EQ(V2S8, getGCDType(V2S8, V4S16));
   EXPECT_EQ(S16, getGCDType(V4S16, V2S8));
 
-  EXPECT_EQ(S8, getGCDType(V2S8, LLT::vector(4, 2)));
-  EXPECT_EQ(LLT::vector(4, 2), getGCDType(LLT::vector(4, 2), S8));
+  EXPECT_EQ(S8, getGCDType(V2S8, LLT::fixed_vector(4, 2)));
+  EXPECT_EQ(LLT::fixed_vector(4, 2), getGCDType(LLT::fixed_vector(4, 2), S8));
 
+  EXPECT_EQ(LLT::pointer(4, 8),
+            getGCDType(LLT::fixed_vector(2, LLT::pointer(4, 8)),
+                       LLT::fixed_vector(4, 2)));
+
+  EXPECT_EQ(LLT::fixed_vector(4, 2),
+            getGCDType(LLT::fixed_vector(4, 2),
+                       LLT::fixed_vector(2, LLT::pointer(4, 8))));
 
-  EXPECT_EQ(LLT::pointer(4, 8), getGCDType(LLT::vector(2, LLT::pointer(4, 8)),
-                                           LLT::vector(4, 2)));
-
-  EXPECT_EQ(LLT::vector(4, 2), getGCDType(LLT::vector(4, 2),
-                                          LLT::vector(2, LLT::pointer(4, 8))));
-
-  EXPECT_EQ(LLT::scalar(4), getGCDType(LLT::vector(3, 4), S8));
-  EXPECT_EQ(LLT::scalar(4), getGCDType(S8, LLT::vector(3, 4)));
+  EXPECT_EQ(LLT::scalar(4), getGCDType(LLT::fixed_vector(3, 4), S8));
+  EXPECT_EQ(LLT::scalar(4), getGCDType(S8, LLT::fixed_vector(3, 4)));
 }
 
 TEST(GISelUtilsTest, getLCMType) {
   EXPECT_EQ(S1, getLCMType(S1, S1));
   EXPECT_EQ(S32, getLCMType(S32, S1));
   EXPECT_EQ(S32, getLCMType(S1, S32));
   EXPECT_EQ(S32, getLCMType(S32, S32));
 
TEST(GISelUtilsTest, getLCMType) {
   EXPECT_EQ(P0, getLCMType(P1, P0));
 
   EXPECT_EQ(V2S32, getLCMType(V2S32, V2S32));
   EXPECT_EQ(V2S32, getLCMType(V2S32, S32));
   EXPECT_EQ(V2S32, getLCMType(S32, V2S32));
   EXPECT_EQ(V2S32, getLCMType(V2S32, V2S32));
   EXPECT_EQ(V6S32, getLCMType(V2S32, V3S32));
   EXPECT_EQ(V6S32, getLCMType(V3S32, V2S32));
-  EXPECT_EQ(LLT::vector(12, S32), getLCMType(V4S32, V3S32));
-  EXPECT_EQ(LLT::vector(12, S32), getLCMType(V3S32, V4S32));
+  EXPECT_EQ(LLT::fixed_vector(12, S32), getLCMType(V4S32, V3S32));
+  EXPECT_EQ(LLT::fixed_vector(12, S32), getLCMType(V3S32, V4S32));
 
   EXPECT_EQ(V2P0, getLCMType(V2P0, V2P0));
   EXPECT_EQ(V2P0, getLCMType(V2P0, P0));
   EXPECT_EQ(V2P0, getLCMType(P0, V2P0));
   EXPECT_EQ(V2P0, getLCMType(V2P0, V2P0));
   EXPECT_EQ(V6P0, getLCMType(V2P0, V3P0));
   EXPECT_EQ(V6P0, getLCMType(V3P0, V2P0));
-  EXPECT_EQ(LLT::vector(12, P0), getLCMType(V4P0, V3P0));
-  EXPECT_EQ(LLT::vector(12, P0), getLCMType(V3P0, V4P0));
+  EXPECT_EQ(LLT::fixed_vector(12, P0), getLCMType(V4P0, V3P0));
+  EXPECT_EQ(LLT::fixed_vector(12, P0), getLCMType(V3P0, V4P0));
 
-  EXPECT_EQ(LLT::vector(12, S64), getLCMType(V4S64, V3P0));
-  EXPECT_EQ(LLT::vector(12, P0), getLCMType(V3P0, V4S64));
+  EXPECT_EQ(LLT::fixed_vector(12, S64), getLCMType(V4S64, V3P0));
+  EXPECT_EQ(LLT::fixed_vector(12, P0), getLCMType(V3P0, V4S64));
 
-  EXPECT_EQ(LLT::vector(12, P0), getLCMType(V4P0, V3S64));
-  EXPECT_EQ(LLT::vector(12, S64), getLCMType(V3S64, V4P0));
+  EXPECT_EQ(LLT::fixed_vector(12, P0), getLCMType(V4P0, V3S64));
+  EXPECT_EQ(LLT::fixed_vector(12, S64), getLCMType(V3S64, V4P0));
 
   EXPECT_EQ(V2P0, getLCMType(V2P0, S32));
   EXPECT_EQ(V4S32, getLCMType(S32, V2P0));
   EXPECT_EQ(V2P0, getLCMType(V2P0, S64));
   EXPECT_EQ(V2S64, getLCMType(S64, V2P0));
 
 
   EXPECT_EQ(V2P0, getLCMType(V2P0, V2P1));
TEST(GISelUtilsTest, getLCMType) {
   EXPECT_EQ(V2S32, getLCMType(V2S32, V4S16));
 
   EXPECT_EQ(V2S32, getLCMType(V2S32, V4S8));
   EXPECT_EQ(V8S8, getLCMType(V4S8, V2S32));
 
   EXPECT_EQ(V2S16, getLCMType(V2S16, V4S8));
   EXPECT_EQ(V4S8, getLCMType(V4S8, V2S16));
 
-  EXPECT_EQ(LLT::vector(6, S16), getLCMType(V3S16, V4S8));
-  EXPECT_EQ(LLT::vector(12, S8), getLCMType(V4S8, V3S16));
+  EXPECT_EQ(LLT::fixed_vector(6, S16), getLCMType(V3S16, V4S8));
+  EXPECT_EQ(LLT::fixed_vector(12, S8), getLCMType(V4S8, V3S16));
   EXPECT_EQ(V4S16, getLCMType(V4S16, V4S8));
   EXPECT_EQ(V8S8, getLCMType(V4S8, V4S16));
 
-  EXPECT_EQ(LLT::vector(6, 4), getLCMType(LLT::vector(3, 4), S8));
-  EXPECT_EQ(LLT::vector(3, 8), getLCMType(S8, LLT::vector(3, 4)));
+  EXPECT_EQ(LLT::fixed_vector(6, 4), getLCMType(LLT::fixed_vector(3, 4), S8));
+  EXPECT_EQ(LLT::fixed_vector(3, 8), getLCMType(S8, LLT::fixed_vector(3, 4)));
 
-  EXPECT_EQ(LLT::vector(6, 4),
-            getLCMType(LLT::vector(3, 4), LLT::pointer(4, 8)));
-  EXPECT_EQ(LLT::vector(3, LLT::pointer(4, 8)),
-            getLCMType(LLT::pointer(4, 8), LLT::vector(3, 4)));
+  EXPECT_EQ(LLT::fixed_vector(6, 4),
+            getLCMType(LLT::fixed_vector(3, 4), LLT::pointer(4, 8)));
+  EXPECT_EQ(LLT::fixed_vector(3, LLT::pointer(4, 8)),
+            getLCMType(LLT::pointer(4, 8), LLT::fixed_vector(3, 4)));
 
   EXPECT_EQ(V2S64, getLCMType(V2S64, P0));
   EXPECT_EQ(V2P0, getLCMType(P0, V2S64));
 
   EXPECT_EQ(V2S64, getLCMType(V2S64, P1));
   EXPECT_EQ(V4P1, getLCMType(P1, V2S64));
 }
 
 }

llvm/unittests/CodeGen/GlobalISel/KnownBitsVectorTest.cpp

)";
   EXPECT_EQ(0x01u, Res.Zero.getZExtValue());
 }
 
 TEST_F(AArch64GISelMITest, TestVectorSignBitIsZero) {
   setUp();
   if (!TM)
     return;
 
-  const LLT V2S32 = LLT::vector(2, 32);
+  const LLT V2S32 = LLT::fixed_vector(2, 32);
   // Vector buildConstant makes splat G_BUILD_VECTOR instruction.
   auto SignBit = B.buildConstant(V2S32, 0x80000000);
   auto Zero = B.buildConstant(V2S32, 0);
 
   const LLT S32 = LLT::scalar(32);
   auto NonSplat =
       B.buildBuildVector(V2S32, {B.buildConstant(S32, 1).getReg(0),
                                  B.buildConstant(S32, 2).getReg(0)});

llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

TEST_F(AArch64GISelMITest, LowerRotatesVector) {
   if (!TM)
     return;
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder({G_ROTR, G_ROTL}).lower(); });
 
   LLT S32 = LLT::scalar(32);
-  LLT V4S32 = LLT::vector(4, S32);
+  LLT V4S32 = LLT::fixed_vector(4, S32);
   auto SrcTrunc = B.buildTrunc(S32, Copies[0]);
   auto Src = B.buildSplatVector(V4S32, SrcTrunc);
   auto AmtTrunc = B.buildTrunc(S32, Copies[1]);
   auto Amt = B.buildSplatVector(V4S32, AmtTrunc);
   auto ROTR = B.buildInstr(TargetOpcode::G_ROTR, {V4S32}, {Src, Amt});
 
   AInfo Info(MF->getSubtarget());
   DummyGISelObserver Observer;
TEST_F(AArch64GISelMITest, NarrowSSUBE) {
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
 TEST_F(AArch64GISelMITest, FewerElementsAnd) {
   setUp();
   if (!TM)
     return;
 
-  const LLT V2S32 = LLT::vector(2, 32);
-  const LLT V5S32 = LLT::vector(5, 32);
+  const LLT V2S32 = LLT::fixed_vector(2, 32);
+  const LLT V5S32 = LLT::fixed_vector(5, 32);
 
   // Declare your legalization info
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder(G_AND)
       .legalFor({s32});
   });
 
   auto Op0 = B.buildUndef(V5S32);

 }
 
 TEST_F(AArch64GISelMITest, MoreElementsAnd) {
   setUp();
   if (!TM)
     return;
 
   LLT s32 = LLT::scalar(32);
-  LLT v2s32 = LLT::vector(2, 32);
-  LLT v6s32 = LLT::vector(6, 32);
+  LLT v2s32 = LLT::fixed_vector(2, 32);
+  LLT v6s32 = LLT::fixed_vector(6, 32);
 
   LegalizerInfo LI;
   LI.getActionDefinitionsBuilder(TargetOpcode::G_AND)
     .legalFor({v6s32})
     .clampMinNumElements(0, s32, 6);
   LI.getLegacyLegalizerInfo().computeTables();
 
   DummyGISelObserver Observer;

 TEST_F(AArch64GISelMITest, FewerElementsPhi) {
   setUp();
   if (!TM)
     return;
 
   LLT s1 = LLT::scalar(1);
   LLT s32 = LLT::scalar(32);
   LLT s64 = LLT::scalar(64);
-  LLT v2s32 = LLT::vector(2, 32);
-  LLT v5s32 = LLT::vector(5, 32);
+  LLT v2s32 = LLT::fixed_vector(2, 32);
+  LLT v5s32 = LLT::fixed_vector(5, 32);
 
   LegalizerInfo LI;
   LI.getActionDefinitionsBuilder(TargetOpcode::G_PHI)
     .legalFor({v2s32})
     .clampMinNumElements(0, s32, 2);
   LI.getLegacyLegalizerInfo().computeTables();
 
   LLT PhiTy = v5s32;

 }
 
 TEST_F(AArch64GISelMITest, LowerMinMax) {
   setUp();
   if (!TM)
     return;
 
   LLT s64 = LLT::scalar(64);
-  LLT v2s32 = LLT::vector(2, 32);
+  LLT v2s32 = LLT::fixed_vector(2, 32);
 
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX})
-      .lowerFor({s64, LLT::vector(2, s32)});
+        .lowerFor({s64, LLT::fixed_vector(2, s32)});
   });
 
   auto SMin = B.buildSMin(s64, Copies[0], Copies[1]);
   auto SMax = B.buildSMax(s64, Copies[0], Copies[1]);
   auto UMin = B.buildUMin(s64, Copies[0], Copies[1]);
   auto UMax = B.buildUMax(s64, Copies[0], Copies[1]);
 
   auto VecVal0 = B.buildBitcast(v2s32, Copies[0]);

 
 TEST_F(AArch64GISelMITest, WidenScalarBuildVector) {
   setUp();
   if (!TM)
     return;
 
   LLT S32 = LLT::scalar(32);
   LLT S16 = LLT::scalar(16);
-  LLT V2S16 = LLT::vector(2, S16);
-  LLT V2S32 = LLT::vector(2, S32);
+  LLT V2S16 = LLT::fixed_vector(2, S16);
+  LLT V2S32 = LLT::fixed_vector(2, S32);
 
   DefineLegalizerInfo(A, {
     getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX})
-      .lowerFor({s64, LLT::vector(2, s32)});
+        .lowerFor({s64, LLT::fixed_vector(2, s32)});
   });
 
   AInfo Info(MF->getSubtarget());
   DummyGISelObserver Observer;
   LegalizerHelper Helper(*MF, Info, Observer, B);
   B.setInsertPt(*EntryMBB, EntryMBB->end());
 
   Register Constant0 = B.buildConstant(S16, 1).getReg(0);
TEST_F(AArch64GISelMITest, LowerInsert) {
 
   // Declare your legalization info
   DefineLegalizerInfo(A, { getActionDefinitionsBuilder(G_INSERT).lower(); });
 
   LLT S32{LLT::scalar(32)};
   LLT S64{LLT::scalar(64)};
   LLT P0{LLT::pointer(0, 64)};
   LLT P1{LLT::pointer(1, 32)};
-  LLT V2S32{LLT::vector(2, 32)};
+  LLT V2S32{LLT::fixed_vector(2, 32)};
 
   auto TruncS32 = B.buildTrunc(S32, Copies[0]);
   auto IntToPtrP0 = B.buildIntToPtr(P0, Copies[0]);
   auto IntToPtrP1 = B.buildIntToPtr(P1, TruncS32);
   auto BitcastV2S32 = B.buildBitcast(V2S32, Copies[0]);
 
   auto InsertS64S32 = B.buildInsert(S64, Copies[0], TruncS32, 0);
   auto InsertS64P1 = B.buildInsert(S64, Copies[0], IntToPtrP1, 8);

 TEST_F(AArch64GISelMITest, LowerBSWAP) {
   setUp();
   if (!TM)
     return;
 
   DefineLegalizerInfo(A, {});
 
   // Make sure vector lowering doesn't assert.
-  auto Cast = B.buildBitcast(LLT::vector(2, 32), Copies[0]);
-  auto BSwap = B.buildBSwap(LLT::vector(2, 32), Cast);
+  auto Cast = B.buildBitcast(LLT::fixed_vector(2, 32), Copies[0]);
+  auto BSwap = B.buildBSwap(LLT::fixed_vector(2, 32), Cast);
   AInfo Info(MF->getSubtarget());
   DummyGISelObserver Observer;
   LegalizerHelper Helper(*MF, Info, Observer, B);
   // Perform Legalization
   EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
             Helper.lower(*BSwap, 0, LLT()));
 
   auto CheckStr = R"(

 
 TEST_F(AArch64GISelMITest, BitcastLoad) {
   setUp();
   if (!TM)
     return;
 
   LLT P0 = LLT::pointer(0, 64);
   LLT S32 = LLT::scalar(32);
-  LLT V4S8 = LLT::vector(4, 8);
+  LLT V4S8 = LLT::fixed_vector(4, 8);
   auto Ptr = B.buildUndef(P0);
 
   DefineLegalizerInfo(A, {});
 
   MachineMemOperand *MMO = B.getMF().getMachineMemOperand(
       MachinePointerInfo(), MachineMemOperand::MOLoad, 4, Align(4));
   auto Load = B.buildLoad(V4S8, Ptr, *MMO);
 

 
 TEST_F(AArch64GISelMITest, BitcastStore) {
   setUp();
   if (!TM)
     return;
 
   LLT P0 = LLT::pointer(0, 64);
   LLT S32 = LLT::scalar(32);
-  LLT V4S8 = LLT::vector(4, 8);
+  LLT V4S8 = LLT::fixed_vector(4, 8);
   auto Ptr = B.buildUndef(P0);
 
   DefineLegalizerInfo(A, {});
 
   MachineMemOperand *MMO = B.getMF().getMachineMemOperand(
       MachinePointerInfo(), MachineMemOperand::MOStore, 4, Align(4));
   auto Val = B.buildUndef(V4S8);
   auto Store = B.buildStore(Val, Ptr, *MMO);

 
 TEST_F(AArch64GISelMITest, BitcastSelect) {
   setUp();
   if (!TM)
     return;
 
   LLT S1 = LLT::scalar(1);
   LLT S32 = LLT::scalar(32);
-  LLT V4S8 = LLT::vector(4, 8);
+  LLT V4S8 = LLT::fixed_vector(4, 8);
 
   DefineLegalizerInfo(A, {});
 
   auto Cond = B.buildUndef(S1);
   auto Val0 = B.buildConstant(V4S8, 123);
   auto Val1 = B.buildConstant(V4S8, 99);
 
   auto Select = B.buildSelect(V4S8, Cond, Val0, Val1);
TEST_F(AArch64GISelMITest, BitcastSelect) {
   CHECK: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT %{{[0-9]+}}:_(s1), [[CAST0]]:_, [[CAST1]]:_
   CHECK: [[CAST2:%[0-9]+]]:_(<4 x s8>) = G_BITCAST [[SELECT]]
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 
   // Doesn't make sense
-  auto VCond = B.buildUndef(LLT::vector(4, 1));
+  auto VCond = B.buildUndef(LLT::fixed_vector(4, 1));
   auto VSelect = B.buildSelect(V4S8, VCond, Val0, Val1);
 
   B.setInsertPt(*EntryMBB, VSelect->getIterator());
   EXPECT_EQ(LegalizerHelper::LegalizeResult::UnableToLegalize,
             Helper.bitcast(*VSelect, 0, S32));
   EXPECT_EQ(LegalizerHelper::LegalizeResult::UnableToLegalize,
             Helper.bitcast(*VSelect, 1, LLT::scalar(4)));
 }
 
 TEST_F(AArch64GISelMITest, BitcastBitOps) {
   setUp();
   if (!TM)
     return;
 
   LLT S32 = LLT::scalar(32);
-  LLT V4S8 = LLT::vector(4, 8);
+  LLT V4S8 = LLT::fixed_vector(4, 8);
 
   DefineLegalizerInfo(A, {});
 
   auto Val0 = B.buildConstant(V4S8, 123);
   auto Val1 = B.buildConstant(V4S8, 99);
   auto And = B.buildAnd(V4S8, Val0, Val1);
   auto Or = B.buildOr(V4S8, Val0, Val1);
   auto Xor = B.buildXor(V4S8, Val0, Val1);
TEST_F(AArch64GISelMITest, NarrowImplicitDef) {
 
   DefineLegalizerInfo(A, {});
 
   // Make sure that G_IMPLICIT_DEF can be narrowed if the original size is not a
   // multiple of narrow size
   LLT S32{LLT::scalar(32)};
   LLT S48{LLT::scalar(48)};
   LLT S64{LLT::scalar(64)};
-  LLT V2S64{{LLT::vector(2, 64)}};
+  LLT V2S64{{LLT::fixed_vector(2, 64)}};
 
   auto Implicit1 = B.buildUndef(S64);
   auto Implicit2 = B.buildUndef(S64);
   auto Implicit3 = B.buildUndef(V2S64);
   auto Implicit4 = B.buildUndef(V2S64);
 
   AInfo Info(MF->getSubtarget());
   DummyGISelObserver Observer;
TEST_F(AArch64GISelMITest, WidenFreeze) {
   if (!TM)
     return;
 
   DefineLegalizerInfo(A, {});
 
   // Make sure that G_FREEZE is widened with anyext
   LLT S64{LLT::scalar(64)};
   LLT S128{LLT::scalar(128)};
-  LLT V2S32{LLT::vector(2, 32)};
-  LLT V2S64{LLT::vector(2, 64)};
+  LLT V2S32{LLT::fixed_vector(2, 32)};
+  LLT V2S64{LLT::fixed_vector(2, 64)};
 
   auto Vector = B.buildBitcast(V2S32, Copies[0]);
 
   auto FreezeScalar = B.buildInstr(TargetOpcode::G_FREEZE, {S64}, {Copies[0]});
   auto FreezeVector = B.buildInstr(TargetOpcode::G_FREEZE, {V2S32}, {Vector});
 
   AInfo Info(MF->getSubtarget());
   DummyGISelObserver Observer;
TEST_F(AArch64GISelMITest, NarrowFreeze) {
 
   DefineLegalizerInfo(A, {});
 
   // Make sure that G_FREEZE is narrowed using unmerge/extract
   LLT S16{LLT::scalar(16)};
   LLT S32{LLT::scalar(32)};
   LLT S33{LLT::scalar(33)};
   LLT S64{LLT::scalar(64)};
-  LLT V2S16{LLT::vector(2, 16)};
-  LLT V2S32{LLT::vector(2, 32)};
+  LLT V2S16{LLT::fixed_vector(2, 16)};
+  LLT V2S32{LLT::fixed_vector(2, 32)};
 
   auto Trunc = B.buildTrunc(S33, {Copies[0]});
   auto Vector = B.buildBitcast(V2S32, Copies[0]);
 
   auto FreezeScalar = B.buildInstr(TargetOpcode::G_FREEZE, {S64}, {Copies[0]});
   auto FreezeOdd = B.buildInstr(TargetOpcode::G_FREEZE, {S33}, {Trunc});
   auto FreezeVector = B.buildInstr(TargetOpcode::G_FREEZE, {V2S32}, {Vector});
   auto FreezeVector1 = B.buildInstr(TargetOpcode::G_FREEZE, {V2S32}, {Vector});

 TEST_F(AArch64GISelMITest, FewerElementsFreeze) {
   setUp();
   if (!TM)
     return;
 
   DefineLegalizerInfo(A, {});
 
   LLT S32{LLT::scalar(32)};
-  LLT V2S16{LLT::vector(2, 16)};
-  LLT V2S32{LLT::vector(2, 32)};
-  LLT V4S16{LLT::vector(4, 16)};
+  LLT V2S16{LLT::fixed_vector(2, 16)};
+  LLT V2S32{LLT::fixed_vector(2, 32)};
+  LLT V4S16{LLT::fixed_vector(4, 16)};
 
   auto Vector1 = B.buildBitcast(V2S32, Copies[0]);
   auto Vector2 = B.buildBitcast(V4S16, Copies[0]);
 
   auto FreezeVector1 = B.buildInstr(TargetOpcode::G_FREEZE, {V2S32}, {Vector1});
   auto FreezeVector2 = B.buildInstr(TargetOpcode::G_FREEZE, {V4S16}, {Vector2});
 
   AInfo Info(MF->getSubtarget());

 // Test more elements of G_FREEZE
 TEST_F(AArch64GISelMITest, MoreElementsFreeze) {
   setUp();
   if (!TM)
     return;
 
   DefineLegalizerInfo(A, {});
 
-  LLT V2S32{LLT::vector(2, 32)};
-  LLT V4S32{LLT::vector(4, 32)};
+  LLT V2S32{LLT::fixed_vector(2, 32)};
+  LLT V4S32{LLT::fixed_vector(4, 32)};
 
   auto Vector1 = B.buildBitcast(V2S32, Copies[0]);
   auto FreezeVector1 = B.buildInstr(TargetOpcode::G_FREEZE, {V2S32}, {Vector1});
 
   AInfo Info(MF->getSubtarget());
   DummyGISelObserver Observer;
   LegalizerHelper Helper(*MF, Info, Observer, B);
 
TEST_F(AArch64GISelMITest, FewerElementsInsertVectorElt) {
   if (!TM)
     return;
 
   DefineLegalizerInfo(A, {});
 
   LLT P0{LLT::pointer(0, 64)};
   LLT S64{LLT::scalar(64)};
   LLT S16{LLT::scalar(16)};
-  LLT V2S16{LLT::vector(2, 16)};
-  LLT V3S16{LLT::vector(3, 16)};
-  LLT V8S16{LLT::vector(8, 16)};
+  LLT V2S16{LLT::fixed_vector(2, 16)};
+  LLT V3S16{LLT::fixed_vector(3, 16)};
+  LLT V8S16{LLT::fixed_vector(8, 16)};
 
   auto Ptr0 = B.buildIntToPtr(P0, Copies[0]);
   auto VectorV8 = B.buildLoad(V8S16, Ptr0, MachinePointerInfo(), Align(8));
   auto Value = B.buildTrunc(S16, Copies[1]);
 
   auto Seven = B.buildConstant(S64, 7);
   auto InsertV8Constant7_0 =
       B.buildInsertVectorElement(V8S16, VectorV8, Value, Seven);

llvm/unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp

TEST(LegalizerInfoTest, ScalarRISC) {
   }
 }
 
 TEST(LegalizerInfoTest, VectorRISC) {
   using namespace TargetOpcode;
   LegalizerInfo L;
   auto &LegacyInfo = L.getLegacyLegalizerInfo();
   // Typical RISCy set of operations based on ARM.
-  LegacyInfo.setAction({G_ADD, LLT::vector(8, 8)},
+  LegacyInfo.setAction({G_ADD, LLT::fixed_vector(8, 8)},
                        LegacyLegalizeActions::Legal);
-  LegacyInfo.setAction({G_ADD, LLT::vector(16, 8)},
+  LegacyInfo.setAction({G_ADD, LLT::fixed_vector(16, 8)},
                        LegacyLegalizeActions::Legal);
-  LegacyInfo.setAction({G_ADD, LLT::vector(4, 16)},
+  LegacyInfo.setAction({G_ADD, LLT::fixed_vector(4, 16)},
                        LegacyLegalizeActions::Legal);
-  LegacyInfo.setAction({G_ADD, LLT::vector(8, 16)},
+  LegacyInfo.setAction({G_ADD, LLT::fixed_vector(8, 16)},
                        LegacyLegalizeActions::Legal);
-  LegacyInfo.setAction({G_ADD, LLT::vector(2, 32)},
+  LegacyInfo.setAction({G_ADD, LLT::fixed_vector(2, 32)},
                        LegacyLegalizeActions::Legal);
-  LegacyInfo.setAction({G_ADD, LLT::vector(4, 32)},
+  LegacyInfo.setAction({G_ADD, LLT::fixed_vector(4, 32)},
                        LegacyLegalizeActions::Legal);
 
   LegacyInfo.setLegalizeVectorElementToDifferentSizeStrategy(
       G_ADD, 0, LegacyLegalizerInfo::widenToLargerTypesUnsupportedOtherwise);
 
   LegacyInfo.setAction({G_ADD, 0, LLT::scalar(32)},
                        LegacyLegalizeActions::Legal);
 
   LegacyInfo.computeTables();
 
   // Check we infer the correct types and actually do what we're told for some
   // simple cases.
-  EXPECT_EQ(L.getAction({G_ADD, {LLT::vector(8, 8)}}),
+  EXPECT_EQ(L.getAction({G_ADD, {LLT::fixed_vector(8, 8)}}),
             LegalizeActionStep(Legal, 0, LLT{}));
-  EXPECT_EQ(L.getAction({G_ADD, {LLT::vector(8, 7)}}),
-            LegalizeActionStep(WidenScalar, 0, LLT::vector(8, 8)));
-  EXPECT_EQ(L.getAction({G_ADD, {LLT::vector(2, 8)}}),
-            LegalizeActionStep(MoreElements, 0, LLT::vector(8, 8)));
-  EXPECT_EQ(L.getAction({G_ADD, {LLT::vector(8, 32)}}),
-            LegalizeActionStep(FewerElements, 0, LLT::vector(4, 32)));
+  EXPECT_EQ(L.getAction({G_ADD, {LLT::fixed_vector(8, 7)}}),
+            LegalizeActionStep(WidenScalar, 0, LLT::fixed_vector(8, 8)));
+  EXPECT_EQ(L.getAction({G_ADD, {LLT::fixed_vector(2, 8)}}),
+            LegalizeActionStep(MoreElements, 0, LLT::fixed_vector(8, 8)));
+  EXPECT_EQ(L.getAction({G_ADD, {LLT::fixed_vector(8, 32)}}),
+            LegalizeActionStep(FewerElements, 0, LLT::fixed_vector(4, 32)));
   // Check a few non-power-of-2 sizes:
-  EXPECT_EQ(L.getAction({G_ADD, {LLT::vector(3, 3)}}),
-            LegalizeActionStep(WidenScalar, 0, LLT::vector(3, 8)));
-  EXPECT_EQ(L.getAction({G_ADD, {LLT::vector(3, 8)}}),
-            LegalizeActionStep(MoreElements, 0, LLT::vector(8, 8)));
+  EXPECT_EQ(L.getAction({G_ADD, {LLT::fixed_vector(3, 3)}}),
+            LegalizeActionStep(WidenScalar, 0, LLT::fixed_vector(3, 8)));
+  EXPECT_EQ(L.getAction({G_ADD, {LLT::fixed_vector(3, 8)}}),
+            LegalizeActionStep(MoreElements, 0, LLT::fixed_vector(8, 8)));
 }
 
 TEST(LegalizerInfoTest, MultipleTypes) {
   using namespace TargetOpcode;
   LegalizerInfo L;
   auto &LegacyInfo = L.getLegacyLegalizerInfo();
   LLT p0 = LLT::pointer(0, 64);
   LLT s64 = LLT::scalar(64);
TEST(LegalizerInfoTest, RuleSets) {
 
   const LLT s5 = LLT::scalar(5);
   const LLT s8 = LLT::scalar(8);
   const LLT s16 = LLT::scalar(16);
   const LLT s32 = LLT::scalar(32);
   const LLT s33 = LLT::scalar(33);
   const LLT s64 = LLT::scalar(64);
 
-  const LLT v2s5 = LLT::vector(2, 5);
-  const LLT v2s8 = LLT::vector(2, 8);
-  const LLT v2s16 = LLT::vector(2, 16);
-  const LLT v2s32 = LLT::vector(2, 32);
-  const LLT v3s32 = LLT::vector(3, 32);
-  const LLT v4s32 = LLT::vector(4, 32);
-  const LLT v2s33 = LLT::vector(2, 33);
-  const LLT v2s64 = LLT::vector(2, 64);
+  const LLT v2s5 = LLT::fixed_vector(2, 5);
+  const LLT v2s8 = LLT::fixed_vector(2, 8);
+  const LLT v2s16 = LLT::fixed_vector(2, 16);
+  const LLT v2s32 = LLT::fixed_vector(2, 32);
+  const LLT v3s32 = LLT::fixed_vector(3, 32);
+  const LLT v4s32 = LLT::fixed_vector(4, 32);
+  const LLT v2s33 = LLT::fixed_vector(2, 33);
+  const LLT v2s64 = LLT::fixed_vector(2, 64);
 
   const LLT p0 = LLT::pointer(0, 32);
-  const LLT v3p0 = LLT::vector(3, p0);
-  const LLT v4p0 = LLT::vector(4, p0);
+  const LLT v3p0 = LLT::fixed_vector(3, p0);
+  const LLT v4p0 = LLT::fixed_vector(4, p0);
 
   {
     LegalizerInfo LI;
     auto &LegacyInfo = LI.getLegacyLegalizerInfo();
 
     LI.getActionDefinitionsBuilder(G_IMPLICIT_DEF)
       .legalFor({v4s32, v4p0})
       .moreElementsToNextPow2(0);

llvm/unittests/CodeGen/GlobalISel/LegalizerTest.cpp

::testing::AssertionResult isNullMIPtr(const MachineInstr *MI) {
   MI->print(MISStream, /*IsStandalone=*/true, /*SkipOpers=*/false,
             /*SkipDebugLoc=*/false, /*AddNewLine=*/false);
   return ::testing::AssertionFailure()
          << "unable to legalize instruction: " << MISStream.str();
 }
 
 DefineLegalizerInfo(ALegalizer, {
   auto p0 = LLT::pointer(0, 64);
-  auto v2s8 = LLT::vector(2, 8);
-  auto v2s16 = LLT::vector(2, 16);
+  auto v2s8 = LLT::fixed_vector(2, 8);
+  auto v2s16 = LLT::fixed_vector(2, 16);
   getActionDefinitionsBuilder(G_LOAD)
       .legalForTypesWithMemDesc({{s16, p0, 8, 8}})
       .scalarize(0)
       .clampScalar(0, s16, s16);
   getActionDefinitionsBuilder(G_PTR_ADD).legalFor({{p0, s64}});
   getActionDefinitionsBuilder(G_CONSTANT).legalFor({s32, s64});
   getActionDefinitionsBuilder(G_BUILD_VECTOR)
       .legalFor({{v2s16, s16}})

llvm/unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp

 TEST_F(AArch64GISelMITest, TestBuildConstantFConstant) {
   setUp();
   if (!TM)
     return;
 
   B.buildConstant(LLT::scalar(32), 42);
   B.buildFConstant(LLT::scalar(32), 1.0);
 
-  B.buildConstant(LLT::vector(2, 32), 99);
-  B.buildFConstant(LLT::vector(2, 32), 2.0);
+  B.buildConstant(LLT::fixed_vector(2, 32), 99);
+  B.buildFConstant(LLT::fixed_vector(2, 32), 2.0);
 
   // Test APFloat overload.
   APFloat KVal(APFloat::IEEEdouble(), "4.0");
   B.buildFConstant(LLT::scalar(64), KVal);
 
   auto CheckStr = R"(
   CHECK: [[CONST0:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
   CHECK: [[FCONST0:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
if (!TM)
     return;
 
   LLVMContext &Ctx = MF->getFunction().getContext();
   APInt APV32(32, 12345);
 
   // Test APInt version breaks
   EXPECT_DEATH(B.buildConstant(LLT::scalar(16), APV32),
                "creating constant with the wrong size");
-  EXPECT_DEATH(B.buildConstant(LLT::vector(2, 16), APV32),
+  EXPECT_DEATH(B.buildConstant(LLT::fixed_vector(2, 16), APV32),
                "creating constant with the wrong size");
 
   // Test ConstantInt version breaks
   ConstantInt *CI = ConstantInt::get(Ctx, APV32);
   EXPECT_DEATH(B.buildConstant(LLT::scalar(16), *CI),
                "creating constant with the wrong size");
-  EXPECT_DEATH(B.buildConstant(LLT::vector(2, 16), *CI),
+  EXPECT_DEATH(B.buildConstant(LLT::fixed_vector(2, 16), *CI),
                "creating constant with the wrong size");
 
   APFloat DoubleVal(APFloat::IEEEdouble());
   ConstantFP *CF = ConstantFP::get(Ctx, DoubleVal);
   EXPECT_DEATH(B.buildFConstant(LLT::scalar(16), *CF),
                "creating fconstant with the wrong size");
-  EXPECT_DEATH(B.buildFConstant(LLT::vector(2, 16), *CF),
+  EXPECT_DEATH(B.buildFConstant(LLT::fixed_vector(2, 16), *CF),
                "creating fconstant with the wrong size");
 }
 
 #endif
 #endif
 
 TEST_F(AArch64GISelMITest, DstOpSrcOp) {
   setUp();
TEST_F(AArch64GISelMITest, BuildMerge) {
   Register RegC1 = B.buildConstant(S32, 1).getReg(0);
   Register RegC2 = B.buildConstant(S32, 2).getReg(0);
   Register RegC3 = B.buildConstant(S32, 3).getReg(0);
 
   // Merging plain constants as one big blob of bit should produce a
   // G_MERGE_VALUES.
   B.buildMerge(LLT::scalar(128), {RegC0, RegC1, RegC2, RegC3});
   // Merging plain constants to a vector should produce a G_BUILD_VECTOR.
-  LLT V2x32 = LLT::vector(2, 32);
+  LLT V2x32 = LLT::fixed_vector(2, 32);
   Register RegC0C1 =
       B.buildMerge(V2x32, {RegC0, RegC1}).getReg(0);
   Register RegC2C3 =
       B.buildMerge(V2x32, {RegC2, RegC3}).getReg(0);
   // Merging vector constants to a vector should produce a G_CONCAT_VECTORS.
-  B.buildMerge(LLT::vector(4, 32), {RegC0C1, RegC2C3});
+  B.buildMerge(LLT::fixed_vector(4, 32), {RegC0C1, RegC2C3});
   // Merging vector constants to a plain type is not allowed.
   // Nothing else to test.
 
   auto CheckStr = R"(
   ; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
   ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
   ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
   ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3

llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp

TEST_F(AArch64GISelMITest, MatchSpecificType) {
   LLT s32 = LLT::scalar(32);
   auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
   EXPECT_FALSE(mi_match(MIBAdd.getReg(0), *MRI,
                         m_GAdd(m_SpecificType(s32), m_Reg())));
   EXPECT_TRUE(mi_match(MIBAdd.getReg(0), *MRI,
                        m_GAdd(m_SpecificType(s64), m_Reg())));
 
   // Try to match the destination type of a bitcast.
-  LLT v2s32 = LLT::vector(2, 32);
+  LLT v2s32 = LLT::fixed_vector(2, 32);
   auto MIBCast = B.buildCast(v2s32, Copies[0]);
   EXPECT_TRUE(
       mi_match(MIBCast.getReg(0), *MRI, m_GBitcast(m_Reg())));
   EXPECT_TRUE(
       mi_match(MIBCast.getReg(0), *MRI, m_SpecificType(v2s32)));
   EXPECT_TRUE(
       mi_match(MIBCast.getReg(1), *MRI, m_SpecificType(s64)));
 

llvm/unittests/CodeGen/LowLevelTypeTest.cpp

TEST(LowLevelTypeTest, Vector) {
   for (unsigned S : {1U, 17U, 32U, 64U, 0xfffU}) {
     for (auto EC :
          {ElementCount::getFixed(2), ElementCount::getFixed(3),
           ElementCount::getFixed(4), ElementCount::getFixed(32),
           ElementCount::getFixed(0xff), ElementCount::getScalable(2),
           ElementCount::getScalable(3), ElementCount::getScalable(4),
           ElementCount::getScalable(32), ElementCount::getScalable(0xff)}) {
       const LLT STy = LLT::scalar(S);
-      const LLT VTy = LLT::vector(EC.getKnownMinValue(), S, EC.isScalable());
+      const LLT VTy = LLT::vector(EC, S);
 
       // Test the alternative vector().
       {
-        const LLT VSTy =
-            LLT::vector(EC.getKnownMinValue(), STy, EC.isScalable());
+        const LLT VSTy = LLT::vector(EC, STy);
         EXPECT_EQ(VTy, VSTy);
       }
 
       // Test getElementType().
       EXPECT_EQ(STy, VTy.getElementType());
 
       // Test kind.
       ASSERT_TRUE(VTy.isValid());
for (auto EC :
       EXPECT_EQ(VTy, getLLTForType(*IRTy, DL));
     }
   }
 }
 
 TEST(LowLevelTypeTest, ScalarOrVector) {
   // Test version with number of bits for scalar type.
   EXPECT_EQ(LLT::scalar(32), LLT::scalarOrVector(1, 32));
-  EXPECT_EQ(LLT::vector(2, 32), LLT::scalarOrVector(2, 32));
+  EXPECT_EQ(LLT::fixed_vector(2, 32), LLT::scalarOrVector(2, 32));
 
   // Test version with LLT for scalar type.
   EXPECT_EQ(LLT::scalar(32), LLT::scalarOrVector(1, LLT::scalar(32)));
-  EXPECT_EQ(LLT::vector(2, 32), LLT::scalarOrVector(2, LLT::scalar(32)));
+  EXPECT_EQ(LLT::fixed_vector(2, 32), LLT::scalarOrVector(2, LLT::scalar(32)));
 
   // Test with pointer elements.
   EXPECT_EQ(LLT::pointer(1, 32), LLT::scalarOrVector(1, LLT::pointer(1, 32)));
-  EXPECT_EQ(LLT::vector(2, LLT::pointer(1, 32)),
+  EXPECT_EQ(LLT::fixed_vector(2, LLT::pointer(1, 32)),
             LLT::scalarOrVector(2, LLT::pointer(1, 32)));
 }
 
 TEST(LowLevelTypeTest, ChangeElementType) {
   const LLT P0 = LLT::pointer(0, 32);
   const LLT P1 = LLT::pointer(1, 64);
 
   const LLT S32 = LLT::scalar(32);
   const LLT S64 = LLT::scalar(64);
 
-  const LLT V2S32 = LLT::vector(2, 32);
-  const LLT V2S64 = LLT::vector(2, 64);
+  const LLT V2S32 = LLT::fixed_vector(2, 32);
+  const LLT V2S64 = LLT::fixed_vector(2, 64);
 
-  const LLT V2P0 = LLT::vector(2, P0);
-  const LLT V2P1 = LLT::vector(2, P1);
+  const LLT V2P0 = LLT::fixed_vector(2, P0);
+  const LLT V2P1 = LLT::fixed_vector(2, P1);
 
   EXPECT_EQ(S64, S32.changeElementType(S64));
   EXPECT_EQ(S32, S32.changeElementType(S32));
 
   EXPECT_EQ(S32, S64.changeElementSize(32));
   EXPECT_EQ(S32, S32.changeElementSize(32));
 
   EXPECT_EQ(V2S64, V2S32.changeElementType(S64));
   EXPECT_EQ(V2S32, V2S64.changeElementType(S32));
 
   EXPECT_EQ(V2S64, V2S32.changeElementSize(64));
   EXPECT_EQ(V2S32, V2S64.changeElementSize(32));
 
   EXPECT_EQ(P0, S32.changeElementType(P0));
   EXPECT_EQ(S32, P0.changeElementType(S32));
 
   EXPECT_EQ(V2P1, V2P0.changeElementType(P1));
   EXPECT_EQ(V2S32, V2P0.changeElementType(S32));
 
   // Similar tests for for scalable vectors.
-  const LLT NXV2S32 = LLT::vector(2, 32, true);
-  const LLT NXV2S64 = LLT::vector(2, 64, true);
+  const LLT NXV2S32 = LLT::scalable_vector(2, 32);
+  const LLT NXV2S64 = LLT::scalable_vector(2, 64);
 
-  const LLT NXV2P0 = LLT::vector(2, P0, true);
-  const LLT NXV2P1 = LLT::vector(2, P1, true);
+  const LLT NXV2P0 = LLT::scalable_vector(2, P0);
+  const LLT NXV2P1 = LLT::scalable_vector(2, P1);
 
   EXPECT_EQ(NXV2S64, NXV2S32.changeElementType(S64));
   EXPECT_EQ(NXV2S32, NXV2S64.changeElementType(S32));
 
   EXPECT_EQ(NXV2S64, NXV2S32.changeElementSize(64));
   EXPECT_EQ(NXV2S32, NXV2S64.changeElementSize(32));
 
   EXPECT_EQ(NXV2P1, NXV2P0.changeElementType(P1));
   EXPECT_EQ(NXV2S32, NXV2P0.changeElementType(S32));
 }
 
 TEST(LowLevelTypeTest, ChangeNumElements) {
   const LLT P0 = LLT::pointer(0, 32);
-  const LLT V2P0 = LLT::vector(2, P0);
-  const LLT V3P0 = LLT::vector(3, P0);
+  const LLT V2P0 = LLT::fixed_vector(2, P0);
+  const LLT V3P0 = LLT::fixed_vector(3, P0);
 
   const LLT S64 = LLT::scalar(64);
-  const LLT V2S64 = LLT::vector(2, 64);
-  const LLT V3S64 = LLT::vector(3, 64);
+  const LLT V2S64 = LLT::fixed_vector(2, 64);
+  const LLT V3S64 = LLT::fixed_vector(3, 64);
 
   // Vector to scalar
   EXPECT_EQ(S64, V2S64.changeNumElements(1));
 
   // Vector to vector
   EXPECT_EQ(V3S64, V2S64.changeNumElements(3));
 
   // Scalar to vector
   EXPECT_EQ(V2S64, S64.changeNumElements(2));
 
   EXPECT_EQ(P0, V2P0.changeNumElements(1));
   EXPECT_EQ(V3P0, V2P0.changeNumElements(3));
   EXPECT_EQ(V2P0, P0.changeNumElements(2));
 }
 
 #ifdef GTEST_HAS_DEATH_TEST
 #ifndef NDEBUG
 
 // Invalid to directly change the element size for pointers.
 TEST(LowLevelTypeTest, ChangeElementTypeDeath) {
   const LLT P0 = LLT::pointer(0, 32);
-  const LLT V2P0 = LLT::vector(2, P0);
+  const LLT V2P0 = LLT::fixed_vector(2, P0);
 
   EXPECT_DEATH(P0.changeElementSize(64),
                "invalid to directly change element size for pointers");
   EXPECT_DEATH(V2P0.changeElementSize(64),
                "invalid to directly change element size for pointers");
 
   // Make sure this still fails even without a change in size.
   EXPECT_DEATH(P0.changeElementSize(32),
for (unsigned AS : {0U, 1U, 127U, 0xffffU,
         static_cast<unsigned>(maxUIntN(24))}) {
     for (ElementCount EC :
          {ElementCount::getFixed(2), ElementCount::getFixed(3),
           ElementCount::getFixed(4), ElementCount::getFixed(256),
           ElementCount::getFixed(65535), ElementCount::getScalable(2),
           ElementCount::getScalable(3), ElementCount::getScalable(4),
           ElementCount::getScalable(256), ElementCount::getScalable(65535)}) {
       const LLT Ty = LLT::pointer(AS, DL.getPointerSizeInBits(AS));
-      const LLT VTy = LLT::vector(EC.getKnownMinValue(), Ty, EC.isScalable());
+      const LLT VTy = LLT::vector(EC, Ty);
 
       // Test kind.
       ASSERT_TRUE(Ty.isValid());
       ASSERT_TRUE(Ty.isPointer());
 
       ASSERT_FALSE(Ty.isScalar());
       ASSERT_FALSE(Ty.isVector());
 
TEST(LowLevelTypeTest, Divide) {
   EXPECT_EQ(LLT::scalar(16), LLT::scalar(32).divide(2));
   EXPECT_EQ(LLT::scalar(8), LLT::scalar(32).divide(4));
   EXPECT_EQ(LLT::scalar(8), LLT::scalar(32).divide(4));
 
   // Test pointer->scalar
   EXPECT_EQ(LLT::scalar(32), LLT::pointer(0, 64).divide(2));
 
   // Test dividing vectors.
-  EXPECT_EQ(LLT::scalar(32), LLT::vector(2, 32).divide(2));
-  EXPECT_EQ(LLT::vector(2, 32), LLT::vector(4, 32).divide(2));
+  EXPECT_EQ(LLT::scalar(32), LLT::fixed_vector(2, 32).divide(2));
+  EXPECT_EQ(LLT::fixed_vector(2, 32), LLT::fixed_vector(4, 32).divide(2));
 
   // Test vector of pointers
   EXPECT_EQ(LLT::pointer(1, 64),
-            LLT::vector(4, LLT::pointer(1, 64)).divide(4));
-  EXPECT_EQ(LLT::vector(2, LLT::pointer(1, 64)),
-            LLT::vector(4, LLT::pointer(1, 64)).divide(2));
+            LLT::fixed_vector(4, LLT::pointer(1, 64)).divide(4));
+  EXPECT_EQ(LLT::fixed_vector(2, LLT::pointer(1, 64)),
+            LLT::fixed_vector(4, LLT::pointer(1, 64)).divide(2));
 }
 
 }

llvm/utils/TableGen/GlobalISelEmitter.cpp

public:
   }
 
   void emitCxxConstructorCall(raw_ostream &OS) const {
     if (Ty.isScalar()) {
       OS << "LLT::scalar(" << Ty.getSizeInBits() << ")";
       return;
     }
     if (Ty.isVector()) {
-      OS << "LLT::vector(" << Ty.getElementCount().getKnownMinValue() << ", "
-         << Ty.getScalarSizeInBits() << ", " << Ty.isScalable() << ")";
+      OS << "LLT::vector("
+         << (Ty.isScalable() ? "ElementCount::getScalable("
+                             : "ElementCount::getFixed(")
+         << Ty.getElementCount().getKnownMinValue() << "), "
+         << Ty.getScalarSizeInBits() << ")";
       return;
     }
     if (Ty.isPointer() && Ty.getSizeInBits() > 0) {
       OS << "LLT::pointer(" << Ty.getAddressSpace() << ", "
          << Ty.getSizeInBits() << ")";
       return;
     }
     llvm_unreachable("Unhandled LLT");

 
 class InstructionMatcher;
 /// Convert an MVT to an equivalent LLT if possible, or the invalid LLT() for
 /// MVTs that don't map cleanly to an LLT (e.g., iPTR, *any, ...).
 static Optional<LLTCodeGen> MVTToLLT(MVT::SimpleValueType SVT) {
   MVT VT(SVT);
 
   if (VT.isVector() && !VT.getVectorElementCount().isScalar())
-    return LLTCodeGen(LLT::vector(VT.getVectorNumElements(),
-                                  VT.getScalarSizeInBits(),
-                                  VT.isScalableVector()));
+    return LLTCodeGen(
+        LLT::vector(VT.getVectorElementCount(), VT.getScalarSizeInBits()));
 
   if (VT.isInteger() || VT.isFloatingPoint())
     return LLTCodeGen(LLT::scalar(VT.getSizeInBits()));
 
   return None;
 }
 
 static std::string explainPredicates(const TreePatternNode *N) {