[GlobalISel] NFC: Change LLT::scalarOrVector to take ElementCount.

[aemerson]

LGTM.

llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h

return actionIf(
         LegalizeAction::FewerElements,
         [=](const LegalityQuery &Query) {
           LLT VecTy = Query.Types[TypeIdx];
           return VecTy.isVector() && VecTy.getElementType() == EltTy &&
                  VecTy.getNumElements() > MaxElements;
         },
         [=](const LegalityQuery &Query) {
           LLT VecTy = Query.Types[TypeIdx];
-          LLT NewTy = LLT::scalarOrVector(MaxElements, VecTy.getElementType());
+          LLT NewTy = LLT::scalarOrVector(ElementCount::getFixed(MaxElements),
+                                          VecTy.getElementType());
           return std::make_pair(TypeIdx, NewTy);
         });
   }
   /// Limit the number of elements for the given vectors to at least MinTy's
   /// number of elements and at most MaxTy's number of elements.
   ///
   /// No effect if the type is not a vector or does not have the same element
   /// type as the constraints.

llvm/include/llvm/Support/LowLevelTypeImpl.h

public:
   }
 
   /// Get a low-level scalable vector of some number of elements and element
   /// type.
   static LLT scalable_vector(unsigned MinNumElements, LLT ScalarTy) {
     return vector(ElementCount::getScalable(MinNumElements), ScalarTy);
   }
 
-  static LLT scalarOrVector(uint16_t NumElements, LLT ScalarTy) {
-    // FIXME: Migrate interface to use ElementCount
-    return NumElements == 1 ? ScalarTy
-                            : LLT::fixed_vector(NumElements, ScalarTy);
+  static LLT scalarOrVector(ElementCount EC, LLT ScalarTy) {
+    return EC.isScalar() ? ScalarTy : LLT::vector(EC, ScalarTy);
   }
 
-  static LLT scalarOrVector(uint16_t NumElements, unsigned ScalarSize) {
-    return scalarOrVector(NumElements, LLT::scalar(ScalarSize));
+  static LLT scalarOrVector(ElementCount EC, unsigned ScalarSize) {
+    return scalarOrVector(EC, LLT::scalar(ScalarSize));
   }
 
   explicit LLT(bool isPointer, bool isVector, ElementCount EC,
                unsigned SizeInBits, unsigned AddressSpace) {
     init(isPointer, isVector, EC, SizeInBits, AddressSpace);
   }
   explicit LLT() : IsPointer(false), IsVector(false), RawData(0) {}
 
return isVector() ? LLT::vector(getElementCount(), NewEltSize)
                       : LLT::scalar(NewEltSize);
   }
 
   /// Return a vector or scalar with the same element type and the new number of
   /// elements.
   LLT changeNumElements(unsigned NewNumElts) const {
     assert((!isVector() || !isScalable()) &&
            "Cannot use changeNumElements on a scalable vector");
-    return LLT::scalarOrVector(NewNumElts, getScalarType());
+    return LLT::scalarOrVector(ElementCount::getFixed(NewNumElts),
+                               getScalarType());
   }
 
   /// Return a type that is \p Factor times smaller. Reduces the number of
   /// elements if this is a vector, or the bitwidth for scalar/pointers. Does
   /// not attempt to handle cases that aren't evenly divisible.
   LLT divide(int Factor) const {
     assert(Factor != 1);
     if (isVector()) {
       assert(getNumElements() % Factor == 0);
-      return scalarOrVector(getNumElements() / Factor, getElementType());
+      return scalarOrVector(getElementCount().divideCoefficientBy(Factor),
+                            getElementType());
     }
 
     assert(getSizeInBits() % Factor == 0);
     return scalar(getSizeInBits() / Factor);
   }
 
   bool isByteSized() const { return (getSizeInBits() & 7) == 0; }
 

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
 
   if (LeftoverSize == 0)
     return {NumParts, 0};
 
   if (NarrowTy.isVector()) {
     unsigned EltSize = OrigTy.getScalarSizeInBits();
     if (LeftoverSize % EltSize != 0)
       return {-1, -1};
-    LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
+    LeftoverTy = LLT::scalarOrVector(
+        ElementCount::getFixed(LeftoverSize / EltSize), EltSize);
   } else {
     LeftoverTy = LLT::scalar(LeftoverSize);
   }
 
   int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
   return std::make_pair(NumParts, NumLeftover);
 }
 
if (LeftoverSize == 0) {
     MIRBuilder.buildUnmerge(VRegs, Reg);
     return true;
   }
 
   if (MainTy.isVector()) {
     unsigned EltSize = MainTy.getScalarSizeInBits();
     if (LeftoverSize % EltSize != 0)
       return false;
-    LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
+    LeftoverTy = LLT::scalarOrVector(
+        ElementCount::getFixed(LeftoverSize / EltSize), EltSize);
   } else {
     LeftoverTy = LLT::scalar(LeftoverSize);
   }
 
   // For irregular sizes, extract the individual parts.
   for (unsigned I = 0; I != NumParts; ++I) {
     Register NewReg = MRI.createGenericVirtualRegister(MainTy);
     VRegs.push_back(NewReg);
if (NewNumElts > OldNumElts) {
     //   (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))),
     //                       (i32 (extract_vector_elt castx, (2 * y + 1)))
     //
     if (NewNumElts % OldNumElts != 0)
       return UnableToLegalize;
 
     // Type of the intermediate result vector.
     const unsigned NewEltsPerOldElt = NewNumElts / OldNumElts;
-    LLT MidTy = LLT::scalarOrVector(NewEltsPerOldElt, NewEltTy);
+    LLT MidTy =
+        LLT::scalarOrVector(ElementCount::getFixed(NewEltsPerOldElt), NewEltTy);
 
     auto NewEltsPerOldEltK = MIRBuilder.buildConstant(IdxTy, NewEltsPerOldElt);
 
     SmallVector<Register, 8> NewOps(NewEltsPerOldElt);
     auto NewBaseIdx = MIRBuilder.buildMul(IdxTy, Idx, NewEltsPerOldEltK);
 
     for (unsigned I = 0; I < NewEltsPerOldElt; ++I) {
       auto IdxOffset = MIRBuilder.buildConstant(IdxTy, I);

 //             s64 = G_SHL s64, s32
 LegalizerHelper::LegalizeResult
 LegalizerHelper::fewerElementsVectorMultiEltType(
   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
   if (TypeIdx != 0)
     return UnableToLegalize;
 
   const LLT NarrowTy0 = NarrowTyArg;
-  const unsigned NewNumElts =
-      NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
-
   const Register DstReg = MI.getOperand(0).getReg();
   LLT DstTy = MRI.getType(DstReg);
   LLT LeftoverTy0;
 
   // All of the operands need to have the same number of elements, so if we can
   // determine a type breakdown for the result type, we can for all of the
   // source types.
   int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first;
   if (NumParts < 0)
     return UnableToLegalize;
 
   SmallVector<MachineInstrBuilder, 4> NewInsts;
 
   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
   SmallVector<Register, 4> PartRegs, LeftoverRegs;
 
   for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
     Register SrcReg = MI.getOperand(I).getReg();
     LLT SrcTyI = MRI.getType(SrcReg);
-    LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
+    const auto NewEC = NarrowTy0.isVector() ? NarrowTy0.getElementCount()
+                                            : ElementCount::getFixed(1);
+    LLT NarrowTyI = LLT::scalarOrVector(NewEC, SrcTyI.getScalarType());
     LLT LeftoverTyI;
 
     // Split this operand into the requested typed registers, and any leftover
     // required to reproduce the original type.
     if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
                       LeftoverRegs))
       return UnableToLegalize;
 
LegalizerHelper::fewerElementsVectorMulo(MachineInstr &MI, unsigned TypeIdx,
   Register RHS = MI.getOperand(3).getReg();
 
   LLT SrcTy = MRI.getType(LHS);
   if (!SrcTy.isVector())
     return UnableToLegalize;
 
   LLT ElementType = SrcTy.getElementType();
   LLT OverflowElementTy = MRI.getType(Overflow).getElementType();
-  const int NumResult = SrcTy.getNumElements();
+  const ElementCount NumResult = SrcTy.getElementCount();
   LLT GCDTy = getGCDType(SrcTy, NarrowTy);
 
   // Unmerge the operands to smaller parts of GCD type.
   auto UnmergeLHS = MIRBuilder.buildUnmerge(GCDTy, LHS);
   auto UnmergeRHS = MIRBuilder.buildUnmerge(GCDTy, RHS);
 
   const int NumOps = UnmergeLHS->getNumOperands() - 1;
-  const int PartsPerUnmerge = NumResult / NumOps;
+  const ElementCount PartsPerUnmerge = NumResult.divideCoefficientBy(NumOps);
   LLT OverflowTy = LLT::scalarOrVector(PartsPerUnmerge, OverflowElementTy);
   LLT ResultTy = LLT::scalarOrVector(PartsPerUnmerge, ElementType);
 
   // Perform the operation over unmerged parts.
   SmallVector<Register, 8> ResultParts;
   SmallVector<Register, 8> OverflowParts;
   for (int I = 0; I != NumOps; ++I) {
     Register Operand1 = UnmergeLHS->getOperand(I).getReg();
     Register Operand2 = UnmergeRHS->getOperand(I).getReg();
     auto PartMul = MIRBuilder.buildInstr(MI.getOpcode(), {ResultTy, OverflowTy},
                                          {Operand1, Operand2});
     ResultParts.push_back(PartMul->getOperand(0).getReg());
     OverflowParts.push_back(PartMul->getOperand(1).getReg());
   }
 
   LLT ResultLCMTy = buildLCMMergePieces(SrcTy, NarrowTy, GCDTy, ResultParts);
   LLT OverflowLCMTy =
-      LLT::scalarOrVector(ResultLCMTy.getNumElements(), OverflowElementTy);
+      LLT::scalarOrVector(ResultLCMTy.getElementCount(), OverflowElementTy);
 
   // Recombine the pieces to the original result and overflow registers.
   buildWidenedRemergeToDst(Result, ResultLCMTy, ResultParts);
   buildWidenedRemergeToDst(Overflow, OverflowLCMTy, OverflowParts);
   MI.eraseFromParent();
   return Legalized;
 }
 
LegalizerHelper::reduceOperationWidth(MachineInstr &MI, unsigned int TypeIdx,
   // First of all check whether we are narrowing (changing the element type)
   // or reducing the vector elements
   const LLT DstTy = MRI.getType(DstRegs[0]);
   const bool IsNarrow = NarrowTy.getScalarType() != DstTy.getScalarType();
 
   SmallVector<Register, 8> ExtractedRegs[3];
   SmallVector<Register, 8> Parts;
 
-  unsigned NarrowElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
-
   // Break down all the sources into NarrowTy pieces we can operate on. This may
   // involve creating merges to a wider type, padded with undef.
   for (int I = 0; I != NumSrcOps; ++I) {
     Register SrcReg = MI.getOperand(I + NumDefOps).getReg();
     LLT SrcTy = MRI.getType(SrcReg);
 
     // The type to narrow SrcReg to. For narrowing, this is a smaller scalar.
     // For fewerElements, this is a smaller vector with the same element type.
     LLT OpNarrowTy;
     if (IsNarrow) {
       OpNarrowTy = NarrowScalarTy;
 
       // In case of narrowing, we need to cast vectors to scalars for this to
       // work properly
       // FIXME: Can we do without the bitcast here if we're narrowing?
       if (SrcTy.isVector()) {
         SrcTy = LLT::scalar(SrcTy.getSizeInBits());
         SrcReg = MIRBuilder.buildBitcast(SrcTy, SrcReg).getReg(0);
       }
     } else {
-      OpNarrowTy = LLT::scalarOrVector(NarrowElts, SrcTy.getScalarType());
+      auto NarrowEC = NarrowTy.isVector() ? NarrowTy.getElementCount()
+                                          : ElementCount::getFixed(1);
+      OpNarrowTy = LLT::scalarOrVector(NarrowEC, SrcTy.getScalarType());
     }
 
     LLT GCDTy = extractGCDType(ExtractedRegs[I], SrcTy, OpNarrowTy, SrcReg);
 
     // Build a sequence of NarrowTy pieces in ExtractedRegs for this operand.
     buildLCMMergePieces(SrcTy, OpNarrowTy, GCDTy, ExtractedRegs[I],
                         TargetOpcode::G_ANYEXT);
   }

llvm/lib/CodeGen/GlobalISel/Utils.cpp

LLT llvm::getGCDType(LLT OrigTy, LLT TargetTy) {
 
   if (OrigTy.isVector()) {
     LLT OrigElt = OrigTy.getElementType();
     if (TargetTy.isVector()) {
       LLT TargetElt = TargetTy.getElementType();
       if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) {
         int GCD = greatestCommonDivisor(OrigTy.getNumElements(),
                                         TargetTy.getNumElements());
-        return LLT::scalarOrVector(GCD, OrigElt);
+        return LLT::scalarOrVector(ElementCount::getFixed(GCD), OrigElt);
       }
     } else {
       // If the source is a vector of pointers, return a pointer element.
       if (OrigElt.getSizeInBits() == TargetSize)
         return OrigElt;
     }
 
     unsigned GCD = greatestCommonDivisor(OrigSize, TargetSize);

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

 
 static LegalizeMutation fewerEltsToSize64Vector(unsigned TypeIdx) {
   return [=](const LegalityQuery &Query) {
     const LLT Ty = Query.Types[TypeIdx];
     const LLT EltTy = Ty.getElementType();
     unsigned Size = Ty.getSizeInBits();
     unsigned Pieces = (Size + 63) / 64;
     unsigned NewNumElts = (Ty.getNumElements() + 1) / Pieces;
-    return std::make_pair(TypeIdx, LLT::scalarOrVector(NewNumElts, EltTy));
+    return std::make_pair(
+        TypeIdx,
+        LLT::scalarOrVector(ElementCount::getFixed(NewNumElts), EltTy));
   };
 }
 
 // Increase the number of vector elements to reach the next multiple of 32-bit
 // type.
 static LegalizeMutation moreEltsToNext32Bit(unsigned TypeIdx) {
   return [=](const LegalityQuery &Query) {
     const LLT Ty = Query.Types[TypeIdx];
static LLT getBitcastRegisterType(const LLT Ty) {
 
   LLT CoercedTy;
   if (Size <= 32) {
     // <2 x s8> -> s16
     // <4 x s8> -> s32
     return LLT::scalar(Size);
   }
 
-  return LLT::scalarOrVector(Size / 32, 32);
+  return LLT::scalarOrVector(ElementCount::getFixed(Size / 32), 32);
 }
 
 static LegalizeMutation bitcastToRegisterType(unsigned TypeIdx) {
   return [=](const LegalityQuery &Query) {
     const LLT Ty = Query.Types[TypeIdx];
     return std::make_pair(TypeIdx, getBitcastRegisterType(Ty));
   };
 }
 
 static LegalizeMutation bitcastToVectorElement32(unsigned TypeIdx) {
   return [=](const LegalityQuery &Query) {
     const LLT Ty = Query.Types[TypeIdx];
     unsigned Size = Ty.getSizeInBits();
     assert(Size % 32 == 0);
-    return std::make_pair(TypeIdx, LLT::scalarOrVector(Size / 32, 32));
+    return std::make_pair(
+        TypeIdx, LLT::scalarOrVector(ElementCount::getFixed(Size / 32), 32));
   };
 }
 
 static LegalityPredicate vectorSmallerThan(unsigned TypeIdx, unsigned Size) {
   return [=](const LegalityQuery &Query) {
     const LLT QueryTy = Query.Types[TypeIdx];
     return QueryTy.isVector() && QueryTy.getSizeInBits() < Size;
   };
Actions
 
               // Split if it's too large for the address space.
               if (Query.MMODescrs[0].SizeInBits > MaxSize) {
                 unsigned NumElts = DstTy.getNumElements();
                 unsigned EltSize = EltTy.getSizeInBits();
 
                 if (MaxSize % EltSize == 0) {
                   return std::make_pair(
-                    0, LLT::scalarOrVector(MaxSize / EltSize, EltTy));
+                      0, LLT::scalarOrVector(
+                             ElementCount::getFixed(MaxSize / EltSize), EltTy));
                 }
 
                 unsigned NumPieces = Query.MMODescrs[0].SizeInBits / MaxSize;
 
                 // FIXME: Refine when odd breakdowns handled
                 // The scalars will need to be re-legalized.
                 if (NumPieces == 1 || NumPieces >= NumElts ||
                     NumElts % NumPieces != 0)
Actions
               unsigned EltSize = EltTy.getSizeInBits();
               unsigned DstSize = DstTy.getSizeInBits();
               if (!isPowerOf2_32(DstSize)) {
                 // We're probably decomposing an odd sized store. Try to split
                 // to the widest type. TODO: Account for alignment. As-is it
                 // should be OK, since the new parts will be further legalized.
                 unsigned FloorSize = PowerOf2Floor(DstSize);
                 return std::make_pair(
-                  0, LLT::scalarOrVector(FloorSize / EltSize, EltTy));
+                    0, LLT::scalarOrVector(
+                           ElementCount::getFixed(FloorSize / EltSize), EltTy));
               }
 
               // Need to split because of alignment.
               unsigned Align = Query.MMODescrs[0].AlignInBits;
               if (EltSize > Align &&
                   (EltSize / Align < DstTy.getNumElements())) {
                 return std::make_pair(
                     0, LLT::fixed_vector(EltSize / Align, EltTy));
bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
 
   // S32 vector to to cover all data, plus TFE result element.
   LLT TFETy;
 
   // Register type to use for each loaded component. Will be S32 or V2S16.
   LLT RegTy;
 
   if (IsD16 && ST.hasUnpackedD16VMem()) {
-    RoundedTy = LLT::scalarOrVector(AdjustedNumElts, 32);
+    RoundedTy =
+        LLT::scalarOrVector(ElementCount::getFixed(AdjustedNumElts), 32);
     TFETy = LLT::fixed_vector(AdjustedNumElts + 1, 32);
     RegTy = S32;
   } else {
     unsigned EltSize = EltTy.getSizeInBits();
     unsigned RoundedElts = (AdjustedTy.getSizeInBits() + 31) / 32;
     unsigned RoundedSize = 32 * RoundedElts;
-    RoundedTy = LLT::scalarOrVector(RoundedSize / EltSize, EltSize);
+    RoundedTy = LLT::scalarOrVector(
+        ElementCount::getFixed(RoundedSize / EltSize), EltSize);
     TFETy = LLT::fixed_vector(RoundedSize / 32 + 1, S32);
     RegTy = !IsTFE && EltSize == 16 ? V2S16 : S32;
   }
 
   // The return type does not need adjustment.
   // TODO: Should we change s16 case to s32 or <2 x s16>?
   if (!IsTFE && (RoundedTy == Ty || !Ty.isVector()))
     return true;

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

static void setRegsToType(MachineRegisterInfo &MRI, ArrayRef<Register> Regs,
   for (Register Reg : Regs) {
     assert(MRI.getType(Reg).getSizeInBits() == NewTy.getSizeInBits());
     MRI.setType(Reg, NewTy);
   }
 }
 
 static LLT getHalfSizedType(LLT Ty) {
   if (Ty.isVector()) {
-    assert(Ty.getNumElements() % 2 == 0);
-    return LLT::scalarOrVector(Ty.getNumElements() / 2, Ty.getElementType());
+    assert(Ty.getElementCount().isKnownMultipleOf(2));
+    return LLT::scalarOrVector(Ty.getElementCount().divideCoefficientBy(2),
+                               Ty.getElementType());
   }
 
-  assert(Ty.getSizeInBits() % 2 == 0);
-  return LLT::scalar(Ty.getSizeInBits() / 2);
+  assert(Ty.getScalarSizeInBits() % 2 == 0);
+  return LLT::scalar(Ty.getScalarSizeInBits() / 2);
 }
 
 /// Legalize instruction \p MI where operands in \p OpIndices must be SGPRs. If
 /// any of the required SGPR operands are VGPRs, perform a waterfall loop to
 /// execute the instruction for each unique combination of values in all lanes
 /// in the wave. The block will be split such that rest of the instructions are
 /// moved to a new block.
 ///
static std::pair<LLT, LLT> splitUnequalType(LLT Ty, unsigned FirstSize) {
 
   LLT EltTy = Ty.getElementType();
   unsigned EltSize = EltTy.getSizeInBits();
   assert(FirstSize % EltSize == 0);
 
   unsigned FirstPartNumElts = FirstSize / EltSize;
   unsigned RemainderElts = (TotalSize - FirstSize) / EltSize;
 
-  return {LLT::scalarOrVector(FirstPartNumElts, EltTy),
-          LLT::scalarOrVector(RemainderElts, EltTy)};
+  return {LLT::scalarOrVector(ElementCount::getFixed(FirstPartNumElts), EltTy),
+          LLT::scalarOrVector(ElementCount::getFixed(RemainderElts), EltTy)};
 }
 
 static LLT widen96To128(LLT Ty) {
   if (!Ty.isVector())
     return LLT::scalar(128);
 
   LLT EltTy = Ty.getElementType();
   assert(128 % EltTy.getSizeInBits() == 0);

llvm/unittests/CodeGen/LowLevelTypeTest.cpp

for (auto EC :
       Type *IRTy = VectorType::get(IRSTy, EC);
       EXPECT_EQ(VTy, getLLTForType(*IRTy, DL));
     }
   }
 }
 
 TEST(LowLevelTypeTest, ScalarOrVector) {
   // Test version with number of bits for scalar type.
-  EXPECT_EQ(LLT::scalar(32), LLT::scalarOrVector(1, 32));
-  EXPECT_EQ(LLT::fixed_vector(2, 32), LLT::scalarOrVector(2, 32));
+  EXPECT_EQ(LLT::scalar(32),
+            LLT::scalarOrVector(ElementCount::getFixed(1), 32));
+  EXPECT_EQ(LLT::fixed_vector(2, 32),
+            LLT::scalarOrVector(ElementCount::getFixed(2), 32));
+  EXPECT_EQ(LLT::scalable_vector(1, 32),
+            LLT::scalarOrVector(ElementCount::getScalable(1), 32));
 
   // Test version with LLT for scalar type.
-  EXPECT_EQ(LLT::scalar(32), LLT::scalarOrVector(1, LLT::scalar(32)));
-  EXPECT_EQ(LLT::fixed_vector(2, 32), LLT::scalarOrVector(2, LLT::scalar(32)));
+  EXPECT_EQ(LLT::scalar(32),
+            LLT::scalarOrVector(ElementCount::getFixed(1), LLT::scalar(32)));
+  EXPECT_EQ(LLT::fixed_vector(2, 32),
+            LLT::scalarOrVector(ElementCount::getFixed(2), LLT::scalar(32)));
 
   // Test with pointer elements.
-  EXPECT_EQ(LLT::pointer(1, 32), LLT::scalarOrVector(1, LLT::pointer(1, 32)));
-  EXPECT_EQ(LLT::fixed_vector(2, LLT::pointer(1, 32)),
-            LLT::scalarOrVector(2, LLT::pointer(1, 32)));
+  EXPECT_EQ(LLT::pointer(1, 32), LLT::scalarOrVector(ElementCount::getFixed(1),
+                                                     LLT::pointer(1, 32)));
+  EXPECT_EQ(
+      LLT::fixed_vector(2, LLT::pointer(1, 32)),
+      LLT::scalarOrVector(ElementCount::getFixed(2), LLT::pointer(1, 32)));
 }
 
 TEST(LowLevelTypeTest, ChangeElementType) {
   const LLT P0 = LLT::pointer(0, 32);
   const LLT P1 = LLT::pointer(1, 64);
 
   const LLT S32 = LLT::scalar(32);
   const LLT S64 = LLT::scalar(64);