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[RISCV] Turn splat shuffles of vector loads into strided load with stride of x0.
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Authored by craig.topper on Mon, Apr 19, 10:11 PM.

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Summary

Implementations are allowed to optimize an x0 stride to perform
less memory accesses. This is the case in SiFive cores.

No idea if this is the case in other implementations. We might
need a tuning flag for this.

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Event Timeline

craig.topper created this revision.Mon, Apr 19, 10:11 PM
craig.topper requested review of this revision.Mon, Apr 19, 10:11 PM
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arcbbb accepted this revision.Thu, Apr 22, 2:35 AM

LGTM

This revision is now accepted and ready to land.Thu, Apr 22, 2:35 AM
frasercrmck accepted this revision.Thu, Apr 22, 2:42 AM

LGTM too. I don't have an implementation at hand, so can't really add anything to the discussion about performance/tuning.