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llvm/test/CodeGen/AArch64/arm64-inline-asm.ll
301	The comment may not be needed. This is a simple lack of handling of a particular constraint type. Having the coverage is sufficient. Readers may not want to read the link.
303	Appending `:` can make the label more unique.

This revision is now accepted and ready to land.Apr 15 2021, 7:07 PM

This revision was landed with ongoing or failed builds.Apr 15 2021, 11:36 PM

This revision was automatically updated to reflect the committed changes.

thanks for the review

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llvm/

lib/

Target/

AArch64/

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test/

CodeGen/

AArch64/

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	}			}

	bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(			bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
	const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {			const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
	switch(ConstraintID) {			switch(ConstraintID) {
	default:			default:
	llvm_unreachable("Unexpected asm memory constraint");			llvm_unreachable("Unexpected asm memory constraint");
	case InlineAsm::Constraint_m:			case InlineAsm::Constraint_m:
				case InlineAsm::Constraint_o:
	case InlineAsm::Constraint_Q:			case InlineAsm::Constraint_Q:
	// We need to make sure that this one operand does not end up in XZR, thus			// We need to make sure that this one operand does not end up in XZR, thus
	// require the address to be in a PointerRegClass register.			// require the address to be in a PointerRegClass register.
	const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();			const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
	const TargetRegisterClass TRC = TRI->getPointerRegClass(MF);			const TargetRegisterClass TRC = TRI->getPointerRegClass(MF);
	SDLoc dl(Op);			SDLoc dl(Op);
	SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64);			SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i64);
	SDValue NewOp =			SDValue NewOp =
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Show First 20 Lines • Show All 1,021 Lines • ▼ Show 20 Lines	private:

void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,		void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
std::vector<SDValue> &Ops,		std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;		SelectionDAG &DAG) const override;

unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {		unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
if (ConstraintCode == "Q")		if (ConstraintCode == "Q")
return InlineAsm::Constraint_Q;		return InlineAsm::Constraint_Q;
		if (ConstraintCode == "o")
		return InlineAsm::Constraint_o;
// FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are		// FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
// followed by llvm_unreachable so we'll leave them unimplemented in		// followed by llvm_unreachable so we'll leave them unimplemented in
// the backend for now.		// the backend for now.
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);		return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
}		}

bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const override;		bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const override;
bool shouldRemoveExtendFromGSIndex(EVT VT) const override;		bool shouldRemoveExtendFromGSIndex(EVT VT) const override;
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	;			;
	entry:			entry:
	%m.addr = alloca <9 x float>, align 16			%m.addr = alloca <9 x float>, align 16
	%m = load <9 x float>, <9 x float>* %0, align 16			%m = load <9 x float>, <9 x float>* %0, align 16
	store <9 x float> %m, <9 x float>* %m.addr, align 16			store <9 x float> %m, <9 x float>* %m.addr, align 16
	call void asm sideeffect "", "=r\|m,0,~{memory}"(<9 x float> nonnull %m.addr, <9 x float> %m)			call void asm sideeffect "", "=r\|m,0,~{memory}"(<9 x float> nonnull %m.addr, <9 x float> %m)
	ret void			ret void
	}			}

				define void @test_o_output_constraint() {
				MaskRayUnsubmitted Done Reply Inline Actions The comment may not be needed. This is a simple lack of handling of a particular constraint type. Having the coverage is sufficient. Readers may not want to read the link. MaskRay: The comment may not be needed. This is a simple lack of handling of a particular constraint…
				; CHECK-LABEL: test_o_output_constraint:
				; CHECK: sub sp, sp, #16
				MaskRayUnsubmitted Done Reply Inline Actions Appending `:` can make the label more unique. MaskRay: Appending `:` can make the label more unique.
				; CHECK: add x[[REG:[0-9]+]], sp, #15
				; CHECK: mov [x[[REG]]], 7
				%b = alloca i8, align 1
				call void asm "mov $0, 7", "=o"(i8 %b)
				ret void
				}