[RISCV] Handle "o" inline asm memory constraint

[• pcwang-thead]

Summary

This is the same as D100412.

We just found the same crash when we tried to compile some packages
like mariadb, php, etc.

For constraint "o", it means "A memory operand is allowed, but
only if the address is offsettable". So I think it can be handled
just like constraint "m" for RISCV target.

And we print verbose information when unsupported constraints occur.

[jrtc27]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

2147–2148

report_fatal_error? llvm_unreachable doesn't always print its message, doesn't always print at all, and doesn't always even abort; in the worst case it ends up being a __builtin_unreachable() that tells the compiler to assume the case can't happen.

llvm/test/CodeGen/RISCV/inline-asm.ll

116

The implementation could be completely broken and this would be none the wiser. You need to test the implementation actually lowers it to something sensible, not that it doesn't crash.

[• pcwang-thead]

• Use report_fatal_error.
• Add more tests.

[• pcwang-thead]

llvm/test/CodeGen/RISCV/inline-asm.ll

116

These tests are the same as constraint "m" now.

[• pcwang-thead]

I just dug into the crash.
The key point here is that these packages are using DTrace(_SDT_ASM_BODY) and some inline assemblies like below will be generated:

define ptr @simple_key_cache_read(ptr %0) {
  call void asm sideeffect "990: nop\0A.pushsection .note.stapsdt,\22?\22,\22note\22\0A.balign 4\0A.4byte 992f-991f,994f-993f,3\0A991: .asciz \22stapsdt\22\0A992: .balign 4\0A993: .8byte 990b\0A.8byte _.stapsdt.base\0A.8byte mysql_keycache__read__start_semaphore\0A.asciz \22mysql\22\0A.asciz \22keycache__read__start\22\0A.asciz \22${0:n}@$1 ${2:n}@$3 ${4:n}@$5 ${6:n}@$7\22\0A994: .balign 4\0A.popsection\0A", "n,nor,n,nor,n,nor,n,nor"(i32 0, ptr %0, i32 0, i32 0, i32 0, i64 0, i32 0, i64 0)
  ret ptr null
}

There are several usages of constraint "o".

[asb]

LGTM, thanks for this fix.

[MaskRay]

llvm/test/CodeGen/RISCV/inline-asm.ll

116

Thanks for the update. The previous case is what I call

https://maskray.me/blog/2021-08-08-toolchain-testing#the-test-checks-at-the-wrong-layer#the-test-checks-too-little "A regression test which simply runs the compiler and expects it not to crash has low utilization. It is often better to additionally test some properties of the produced object file."

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

#undef CASE_VMXOR_VMANDN_VMOR_OPCODES
   SelectCode(Node);
 }
 
 bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(
     const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
   // Always produce a register and immediate operand, as expected by
   // RISCVAsmPrinter::PrintAsmMemoryOperand.
   switch (ConstraintID) {
+  case InlineAsm::Constraint_o:
   case InlineAsm::Constraint_m: {
     SDValue Op0, Op1;
     bool Found = SelectAddrRegImm(Op, Op0, Op1);
     assert(Found && "SelectAddrRegImm should always succeed");
     (void)Found;
     OutOps.push_back(Op0);
     OutOps.push_back(Op1);
     return false;
   }
   case InlineAsm::Constraint_A:
     OutOps.push_back(Op);
     OutOps.push_back(
         CurDAG->getTargetConstant(0, SDLoc(Op), Subtarget->getXLenVT()));
     return false;
   default:
-    break;
+    report_fatal_error("Unexpected asm memory constraint " +
+                       InlineAsm::getMemConstraintName(ConstraintID));
   }
 
   return true;
 }
 
 bool RISCVDAGToDAGISel::SelectAddrFrameIndex(SDValue Addr, SDValue &Base,
                                              SDValue &Offset) {
   if (auto *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {

llvm/test/CodeGen/RISCV/inline-asm.ll

 ; RV64I-NEXT:    lw a0, 4(a0)
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret
   %1 = getelementptr i32, ptr %a, i32 1
   %2 = tail call i32 asm "lw $0, $1", "=r,*m"(ptr elementtype(i32) %1)
   ret i32 %2
 }
 
+define void @constraint_o(ptr %a) nounwind {
+; RV32I-LABEL: constraint_o:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    #APP
+; RV32I-NEXT:    #NO_APP
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: constraint_o:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    #APP
+; RV64I-NEXT:    #NO_APP
+; RV64I-NEXT:    ret
+  call void asm sideeffect "", "=*o"(ptr elementtype(i32) %a)
+  ret void
+}
+
+define i32 @constraint_o2(ptr %a) nounwind {
+; RV32I-LABEL: constraint_o2:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    #APP
+; RV32I-NEXT:    lw a0, 0(a0)
+; RV32I-NEXT:    #NO_APP
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: constraint_o2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    #APP
+; RV64I-NEXT:    lw a0, 0(a0)
+; RV64I-NEXT:    #NO_APP
+; RV64I-NEXT:    ret
+  %1 = tail call i32 asm "lw $0, $1", "=r,*o"(ptr elementtype(i32) %a)
+  ret i32 %1
+}
+
+define i32 @constraint_o_with_offset(ptr %a) nounwind {
+; RV32I-LABEL: constraint_o_with_offset:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    #APP
+; RV32I-NEXT:    lw a0, 4(a0)
+; RV32I-NEXT:    #NO_APP
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: constraint_o_with_offset:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    #APP
+; RV64I-NEXT:    lw a0, 4(a0)
+; RV64I-NEXT:    #NO_APP
+; RV64I-NEXT:    ret
+  %1 = getelementptr i32, ptr %a, i32 1
+  %2 = tail call i32 asm "lw $0, $1", "=r,*o"(ptr elementtype(i32) %1)
+  ret i32 %2
+}
+
 define void @constraint_I() nounwind {
 ; RV32I-LABEL: constraint_I:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a0, 2047
 ; RV32I-NEXT:    #NO_APP
 ; RV32I-NEXT:    #APP
 ; RV32I-NEXT:    addi a0, a0, -2048