[RISCV] Add inline asm constraint 'v' in Clang for RISC-V 'V'.

[jrtc27]

This seems like the obvious choice for the constraint, but it would be good to ensure there's consensus with GCC people, especially since their assembly constraints are intimately tied to their instruction patterns (or, really, the assembly constraints just expose those and we pretend to be GCC) so they have less flexibility than us.

[kito-cheng]

GCC use vr for vector register and vm for vector mask register.

[jrtc27]

In D98616#2626093, @kito-cheng wrote:

GCC use vr for vector register and vm for vector mask register.

How does that even work? Aren't multi character strings a set of options?

[jrtc27]

In D98616#2626094, @jrtc27 wrote:

In D98616#2626093, @kito-cheng wrote:

GCC use vr for vector register and vm for vector mask register.

How does that even work? Aren't multi character strings a set of options?

Hm, apparently multi-character constraints already exist. Not a fan of it as it parses like "vector or register/memory" to me but if that's how GCC needs to internally model its instructions then we have to copy that...

[kito-cheng]

Provide more implementation detail on GCC,

• if a letter are used as a prefix of multi-char constraint, then it can't be used as a single letter constraint
  • e.g. If we defined vr and vm then we can't define v as constraint
• constraint with same prefix should have same length
  • e.g. If we defined vr and vm then we can't define vrr since has different length.

And in fact we have defined bunch of predicate prefixed with v[1], but I am open mind to change that if needed since GCC isn't upstream that yet.

[1] https://github.com/riscv/riscv-gcc/blob/riscv-gcc-10.1-rvv-dev/gcc/config/riscv/constraints.md#L117

[HsiangKai]

Use 'vr' for vector registers and 'vm' for vector mask registers.

[craig.topper]

LGTM

clang/lib/Basic/Targets/RISCV.h

else
       return -1;
   }
 
   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *&Name,
                              TargetInfo::ConstraintInfo &Info) const override;
 
+  std::string convertConstraint(const char *&Constraint) const override;
+
   bool hasFeature(StringRef Feature) const override;
 
   bool handleTargetFeatures(std::vector<std::string> &Features,
                             DiagnosticsEngine &Diags) override;
 
   bool hasExtIntType() const override { return true; }
 };
 class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo {

clang/lib/Basic/Targets/RISCV.cpp

static const char *const GCCRegNames[] = {
       "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",
       "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
       "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
 
       // Floating point registers
       "f0",  "f1",  "f2",  "f3",  "f4",  "f5",  "f6",  "f7",
       "f8",  "f9",  "f10", "f11", "f12", "f13", "f14", "f15",
       "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
-      "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"};
+      "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
+
+      // Vector registers
+      "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",
+      "v8",  "v9",  "v10", "v11", "v12", "v13", "v14", "v15",
+      "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+      "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"};
   return llvm::makeArrayRef(GCCRegNames);
 }
 
 ArrayRef<TargetInfo::GCCRegAlias> RISCVTargetInfo::getGCCRegAliases() const {
   static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
       {{"zero"}, "x0"}, {{"ra"}, "x1"},   {{"sp"}, "x2"},    {{"gp"}, "x3"},
       {{"tp"}, "x4"},   {{"t0"}, "x5"},   {{"t1"}, "x6"},    {{"t2"}, "x7"},
       {{"s0"}, "x8"},   {{"s1"}, "x9"},   {{"a0"}, "x10"},   {{"a1"}, "x11"},
bool RISCVTargetInfo::validateAsmConstraint(
   case 'f':
     // A floating-point register.
     Info.setAllowsRegister();
     return true;
   case 'A':
     // An address that is held in a general-purpose register.
     Info.setAllowsMemory();
     return true;
+  case 'v':
+    // A vector register.
+    if (Name[1] == 'r' || Name[1] == 'm') {
+      Info.setAllowsRegister();
+      Name += 1;
+      return true;
+    }
+    return false;
+  }
+}
+
+std::string RISCVTargetInfo::convertConstraint(const char *&Constraint) const {
+  std::string R;
+  switch (*Constraint) {
+  case 'v':
+    R = std::string("v");
+    Constraint += 1;
+    break;
+  default:
+    R = TargetInfo::convertConstraint(Constraint);
+    break;
   }
+  return R;
 }
 
 void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
                                        MacroBuilder &Builder) const {
   Builder.defineMacro("__ELF__");
   Builder.defineMacro("__riscv");
   bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
   Builder.defineMacro("__riscv_xlen", Is64Bit ? "64" : "32");

clang/test/CodeGen/RISCV/riscv-inline-asm-rvv.c

+// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v \
+// RUN:     -O2 -emit-llvm %s -o - \
+// RUN:     | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \
+// RUN:     -O2 -emit-llvm %s -o - \
+// RUN:     | FileCheck %s
+
+// Test RISC-V V-extension specific inline assembly constraints.
+#include <riscv_vector.h>
+
+void test_v_reg() {
+  asm volatile(
+      "vsetvli x1, x0, e32,m2,tu,mu\n"
+      "vadd.vv v1, v2, v3, v0.t"
+      :
+      :
+      : "v1", "x1");
+// CHECK-LABEL: define{{.*}} @test_v_reg
+// CHECK: "~{v1},~{x1}"
+}
+
+vint32m1_t test_vr(vint32m1_t a, vint32m1_t b) {
+// CHECK-LABEL: define{{.*}} @test_vr
+// CHECK: %0 = tail call <vscale x 2 x i32> asm sideeffect "vadd.vv $0, $1, $2", "=v,v,v"(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b)
+  vint32m1_t ret;
+  asm volatile ("vadd.vv %0, %1, %2" : "=vr"(ret) : "vr"(a), "vr"(b));
+  return ret;
+}
+
+vbool1_t test_vm(vbool1_t a, vbool1_t b) {
+// CHECK-LABEL: define{{.*}} @test_vm
+// CHECK: %0 = tail call <vscale x 64 x i1> asm sideeffect "vmand.mm $0, $1, $2", "=v,v,v"(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b)
+  vbool1_t ret;
+  asm volatile ("vmand.mm %0, %1, %2" : "=vm"(ret) : "vm"(a), "vm"(b));
+  return ret;
+}