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[RISCV][Docs] Add description about inline asm constraint for V.

Authored by HsiangKai on Jul 22 2021, 8:32 PM.



Add constraint 'v' in LLVM IR for vector registers and 'vr' and 'vm' for
C/C++ inline asm constraints.

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HsiangKai created this revision.Jul 22 2021, 8:32 PM
HsiangKai requested review of this revision.Jul 22 2021, 8:32 PM
Herald added a project: Restricted Project. · View Herald TranscriptJul 22 2021, 8:32 PM
kito-cheng added inline comments.Jul 22 2021, 9:12 PM

I thought we only support vr and vm, but v only is not supported?

HsiangKai added inline comments.Jul 23 2021, 4:30 AM

In LLVM IR, it still keeps to only use 'v'. The document is IR document. That's why I describe 'v' here.

In Clang, it will convert 'vr' and 'vm' to 'v' in LLVM IR.

You could see the convertConstraint in

This revision is now accepted and ready to land.Jul 29 2021, 2:00 AM
kito-cheng added inline comments.Jul 29 2021, 7:55 AM

Description at the begin of this chapter

The constraint codes are, in general, expected to behave the same way they do in GCC. LLVM’s support is often implemented on an ‘as-needed’ basis, to support C inline asm code which was supported by GCC. A mismatch in behavior between LLVM and GCC likely indicates a bug in LLVM.

I would suggest remove v, it's impossible to implement v and vr/vm on GCC site.

HsiangKai updated this revision to Diff 363000.Jul 30 2021, 2:15 AM

After D107139, usr 'vr' for vector register and 'vm' for vector mask in IR.