[AArch64] Implement __rndr, __rndrrs intrinsics

[stelios-arm]

Summary

This patch implements the __rndr and __rndrrs intrinsics to provide access to the random number instructions introduced in Armv8.5-A. They are only defined for the AArch64 execution state and are available when __ARM_FEATURE_RNG is defined.

These intrinsics store the random number in their pointer argument and return a status code if the generation succeeded. The difference between __rndr and __rndrrs, is that the latter intrinsic reseeds the random number generator.

The instructions write the NZCV flags indicating the success of the operation that we can then read with a CSET.

[1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics
[2] https://bugs.llvm.org/show_bug.cgi?id=47838

[SjoerdMeijer]

clang/lib/Basic/Targets/AArch64.cpp

363

Where/when is HasRandGen set?

clang/test/Preprocessor/init-aarch64.c

28 ↗

(On Diff #329347)

Why are we expecting this here? Are we not only expecting this for v8.5?

We also need a negative test and CHECK-NOT of this where we don't expect this.

llvm/lib/Target/AArch64/AArch64InstrFormats.td

1495

Do all MRS instructions do this?

llvm/lib/Target/AArch64/AArch64InstrInfo.td

1276

Nit: can be on the same line.

[dmgreen]

llvm/lib/Target/AArch64/AArch64InstrFormats.td

1495

No, but some do and it's not obvious which ones do and don't. I think it should be reasonable to always def NZCV here, even if they are just dead. It should be very rare that it would be beneficial for NZCV to be live across a MRS instruction.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

1272

These are usually put somewhere else in the aarch64 backend, and it might be worth keeping it with the others.

1276

I always prefer Pat's to have input and output lines separate, for what it's worth. It makes them more easily readable.

[SjoerdMeijer]

llvm/lib/Target/AArch64/AArch64InstrFormats.td

1495

True, but since creating another definition is cheap, what would the cons be of:

class MRS_NZCV : MRSI {
  ..
  let Defs = [NZCV];
}

The way I look at it is that the description would be more accurate?

[dmgreen]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

16019

Can you make sure EQ is correct here? I think it might be backwards.

llvm/lib/Target/AArch64/AArch64InstrFormats.td

1495

I believe that would have an over-lapping definition with the existing MRS instruction?

It would need to be a pseudo I think, which would eventually be turned into a MSR proper late enough on the pipeline for it to be valid (or the other way around, the no-nzcv version gets turned into a the nzcv version to keep the verifier happy).

It could also be a optional def, but those are only used in the arm backend and I would not recommend using them anywhere else. I would probably suggest just setting MRS as a NZCV setting instruction, unless we find a reason to need to implement it differently.

[SjoerdMeijer]

llvm/lib/Target/AArch64/AArch64InstrFormats.td

1495

I believe that would have an over-lapping definition with the existing MRS instruction?

Ah yeah, that might be true.

It would need to be a pseudo I think

How much work is adding a pseudo for this case? My first reaction would be just trying to model this correctly, then we potentially don't have to worry again later about this.

[stelios-arm]

@SjoerdMeijer @dmgreen Thanks for your reviews, I will be looking into this.

[SjoerdMeijer]

llvm/lib/Target/AArch64/AArch64InstrFormats.td

1495

I just wanted to add that I don't have too strong opinions on this, but what I suggested seemed more the correct, even though the consequence of setting NCZV for all MRS is minimal. So I will leave this one up to you @dmgreen and @stelios-arm .

[stelios-arm]

clang/lib/Basic/Targets/AArch64.cpp

363

Oh, I forgot to set it, I am going to address this in the new revision.

clang/test/Preprocessor/init-aarch64.c

28 ↗

(On Diff #329347)

Correct this shouldn't be here. I am going to address this in a new revision.

llvm/lib/Target/AArch64/AArch64InstrFormats.td

1495

I will talk with @dmgreen and if it is decided that it is needed to change, I will address it in a future revision. Please note that the next revision of patch, will not address this comment (temporarily).

llvm/lib/Target/AArch64/AArch64InstrInfo.td

1276

The styling for Pat's is not consistent across the file, some are in one line and others have the input and output lines separate. I also prefer the latter for readability.

[stelios-arm]

Addressed the comments made by @SjoerdMeijer and @dmgreen.

[dmgreen]

llvm/lib/Target/AArch64/AArch64InstrFormats.td

1495

Hmm. I feel like adding the pseudo is more trouble than it is worth - they do not come for free. With the extra lowering and adding things like scheduling info, etc. It feels simpler to me to set the flags, even if that's not always exactly what the instruction would do.

[SjoerdMeijer]

llvm/lib/Target/AArch64/AArch64InstrFormats.td

1495

Okidoki, then we at least need some comments here explaining this all.

[stelios-arm]

1. Addressed the comment made by @SjoerdMeijer and added the comment for the MRS instruction.
2. Added the +rang feature in arm_acle.c

[stelios-arm]

Rephrased a comment.

[SjoerdMeijer]

clang/lib/Basic/Targets/AArch64.cpp

364

This needs a clang preprocessor test: both a check for its presence and absence.
Have a look/grep where these others predefined macros are tested.

clang/test/CodeGen/arm_acle.c

1760

Not sure if I am surprised that this works.... This is (re)using tag AArch64-v8_3 and for the other tests that use this and don't have RNG set, I was expecting FileCheck to complain about this, not sure if I am missing something though.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

610–612

Nit: for this comment to be informative, please expand it, or just remove it if there's not much to say about it.

[stelios-arm]

1. Removed a redundant comment
2. Removed the changes made in the test/CodeGen/arm_acle.c, since the test is disabled.
3. Added a clang preprocessor test to check the presence and absence of the __ARM_FEATURE_RNG macro.

[stelios-arm]

clang/test/CodeGen/arm_acle.c

1760

It turns out that this test is disabled (https://github.com/llvm/llvm-project/commit/6fcd4e080f09c9765d6e0ea03b1da91669c8509a). I am going to remove the changes in this file.

[SjoerdMeijer]

clang/test/CodeGen/arm_acle.c

1760

But this seems to be a useful test to have. Are we testing this elsewhere now?

[stelios-arm]

clang/test/CodeGen/arm_acle.c

1760

@dmgreen created a patch to re-enable this test (https://reviews.llvm.org/D98510). I am going to add the tests again.

[stelios-arm]

Added tests in arm_acle.c.

[SjoerdMeijer]

Thanks, nice one, LGTM.

llvm/test/CodeGen/AArch64/rand.ll

3

Nit: we don't need -mcpu=neoverse-v1, so just remove it?

[stelios-arm]

Changed the rand.ll llc arguments to the ones that are only relevant.

[stelios-arm]

Typo fix for __ARM_FEATURE_RNG macro check in aarch64-target-features.c.

clang/include/clang/Basic/BuiltinsAArch64.def

 BUILTIN(__builtin_arm_frint32z, "dd", "")
 BUILTIN(__builtin_arm_frint64zf, "ff", "")
 BUILTIN(__builtin_arm_frint64z, "dd", "")
 BUILTIN(__builtin_arm_frint32xf, "ff", "")
 BUILTIN(__builtin_arm_frint32x, "dd", "")
 BUILTIN(__builtin_arm_frint64xf, "ff", "")
 BUILTIN(__builtin_arm_frint64x, "dd", "")
 
+// Armv8.5-A Random number generation intrinsics
+BUILTIN(__builtin_arm_rndr,   "iWUi*", "n")
+BUILTIN(__builtin_arm_rndrrs, "iWUi*", "n")
+
 // Armv8.7-A load/store 64-byte intrinsics
 BUILTIN(__builtin_arm_ld64b, "vvC*WUi*", "n")
 BUILTIN(__builtin_arm_st64b, "vv*WUiC*", "n")
 BUILTIN(__builtin_arm_st64bv, "WUiv*WUiC*", "n")
 BUILTIN(__builtin_arm_st64bv0, "WUiv*WUiC*", "n")
 
 TARGET_HEADER_BUILTIN(_BitScanForward, "UcUNi*UNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_BitScanReverse, "UcUNi*UNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")

clang/lib/Basic/Targets/AArch64.h

class LLVM_LIBRARY_VISIBILITY AArch64TargetInfo : public TargetInfo {
   bool HasUnaligned;
   bool HasFullFP16;
   bool HasDotProd;
   bool HasFP16FML;
   bool HasMTE;
   bool HasTME;
   bool HasPAuth;
   bool HasLS64;
+  bool HasRandGen;
   bool HasMatMul;
   bool HasSVE2;
   bool HasSVE2AES;
   bool HasSVE2SHA3;
   bool HasSVE2SM4;
   bool HasSVE2BitPerm;
   bool HasMatmulFP64;
   bool HasMatmulFP32;

clang/lib/Basic/Targets/AArch64.cpp

void AArch64TargetInfo::getTargetDefines(const LangOptions &Opts,
   }
 
   if (Opts.BranchTargetEnforcement)
     Builder.defineMacro("__ARM_FEATURE_BTI_DEFAULT", "1");
 
   if (HasLS64)
     Builder.defineMacro("__ARM_FEATURE_LS64", "1");
 
+  if (HasRandGen)
+    Builder.defineMacro("__ARM_FEATURE_RNG", "1");
+
   switch (ArchKind) {
   default:
     break;
   case llvm::AArch64::ArchKind::ARMV8_1A:
     getTargetDefinesARMV81A(Opts, Builder);
     break;
   case llvm::AArch64::ArchKind::ARMV8_2A:
     getTargetDefinesARMV82A(Opts, Builder);
bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
   HasCrypto = false;
   HasUnaligned = true;
   HasFullFP16 = false;
   HasDotProd = false;
   HasFP16FML = false;
   HasMTE = false;
   HasTME = false;
   HasLS64 = false;
+  HasRandGen = false;
   HasMatMul = false;
   HasBFloat16 = false;
   HasSVE2 = false;
   HasSVE2AES = false;
   HasSVE2SHA3 = false;
   HasSVE2SM4 = false;
   HasSVE2BitPerm = false;
   HasMatmulFP64 = false;
for (const auto &Feature : Features) {
     if (Feature == "+i8mm")
       HasMatMul = true;
     if (Feature == "+bf16")
       HasBFloat16 = true;
     if (Feature == "+lse")
       HasLSE = true;
     if (Feature == "+ls64")
       HasLS64 = true;
+    if (Feature == "+rand")
+      HasRandGen = true;
     if (Feature == "+flagm")
       HasFlagM = true;
   }
 
   setDataLayout();
 
   return true;
 }

clang/lib/CodeGen/CGBuiltin.cpp

if (BuiltinID == AArch64::BI__builtin_arm_ld64b) {
                        : BuiltinID == AArch64::BI__builtin_arm_st64bv
                              ? Intrinsic::aarch64_st64bv
                              : Intrinsic::aarch64_st64bv0);
       Function *F = CGM.getIntrinsic(Intr);
       return Builder.CreateCall(F, Args);
     }
   }
 
+  if (BuiltinID == AArch64::BI__builtin_arm_rndr ||
+      BuiltinID == AArch64::BI__builtin_arm_rndrrs) {
+
+    auto Intr = (BuiltinID == AArch64::BI__builtin_arm_rndr
+                     ? Intrinsic::aarch64_rndr
+                     : Intrinsic::aarch64_rndrrs);
+    Function *F = CGM.getIntrinsic(Intr);
+    llvm::Value *Val = Builder.CreateCall(F);
+    Value *RandomValue = Builder.CreateExtractValue(Val, 0);
+    Value *Status = Builder.CreateExtractValue(Val, 1);
+
+    Address MemAddress = EmitPointerWithAlignment(E->getArg(0));
+    Builder.CreateStore(RandomValue, MemAddress);
+    Status = Builder.CreateZExt(Status, Int32Ty);
+    return Status;
+  }
+
   if (BuiltinID == AArch64::BI__clear_cache) {
     assert(E->getNumArgs() == 2 && "__clear_cache takes 2 arguments");
     const FunctionDecl *FD = E->getDirectCallee();
     Value *Ops[2];
     for (unsigned i = 0; i < 2; i++)
       Ops[i] = EmitScalarExpr(E->getArg(i));
     llvm::Type *Ty = CGM.getTypes().ConvertType(FD->getType());
     llvm::FunctionType *FTy = cast<llvm::FunctionType>(Ty);

clang/lib/Headers/arm_acle.h

 /*===---- arm_acle.h - ARM Non-Neon intrinsics -----------------------------===
  *
  * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
  * See https://llvm.org/LICENSE.txt for license information.
  * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
  *
  *===-----------------------------------------------------------------------===
  */
 
 #ifndef __ARM_ACLE_H
 #define __ARM_ACLE_H
 
 #ifndef __ARM_ACLE
 #error "ACLE intrinsics support not enabled."
 #endif
 
 #include <stdint.h>
 
 #if defined(__cplusplus)
 extern "C" {
 #endif
 
 /* 8 SYNCHRONIZATION, BARRIER AND HINT INTRINSICS */
 /* 8.3 Memory barriers */
 #if !__has_builtin(__dmb)
 #define __dmb(i) __builtin_arm_dmb(i)
 #endif
 #if !__has_builtin(__dsb)
 #define __dsb(i) __builtin_arm_dsb(i)
 #endif
 #if !__has_builtin(__isb)
 #define __isb(i) __builtin_arm_isb(i)
 #endif
 
 /* 8.4 Hints */
 
 #if !__has_builtin(__wfi)
 static __inline__ void __attribute__((__always_inline__, __nodebug__)) __wfi(void) {
   __builtin_arm_wfi();
 }
 #endif
 
 #if !__has_builtin(__wfe)
 static __inline__ void __attribute__((__always_inline__, __nodebug__)) __wfe(void) {
   __builtin_arm_wfe();
 }
 #endif
 
 #if !__has_builtin(__sev)
 static __inline__ void __attribute__((__always_inline__, __nodebug__)) __sev(void) {
   __builtin_arm_sev();
 }
 #endif
 
 #if !__has_builtin(__sevl)
 static __inline__ void __attribute__((__always_inline__, __nodebug__)) __sevl(void) {
   __builtin_arm_sevl();
 }
 #endif
 
 #if !__has_builtin(__yield)
 static __inline__ void __attribute__((__always_inline__, __nodebug__)) __yield(void) {
   __builtin_arm_yield();
 }
 #endif
 
 #if __ARM_32BIT_STATE
 #define __dbg(t) __builtin_arm_dbg(t)
 #endif
 
 /* 8.5 Swap */
 static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
 __swp(uint32_t __x, volatile uint32_t *__p) {
   uint32_t v;
   do
     v = __builtin_arm_ldrex(__p);
   while (__builtin_arm_strex(__x, __p));
   return v;
 }
 
 /* 8.6 Memory prefetch intrinsics */
 /* 8.6.1 Data prefetch */
 #define __pld(addr) __pldx(0, 0, 0, addr)
 
 #if __ARM_32BIT_STATE

 #else
 #define __plix(cache_level, retention_policy, addr) \
   __builtin_arm_prefetch(addr, 0, cache_level, retention_policy, 0)
 #endif
 
 /* 8.7 NOP */
 #if !defined(_MSC_VER) || !defined(__aarch64__)
 static __inline__ void __attribute__((__always_inline__, __nodebug__)) __nop(void) {
   __builtin_arm_nop();
 }
 #endif
 
 /* 9 DATA-PROCESSING INTRINSICS */
 /* 9.2 Miscellaneous data-processing intrinsics */
 /* ROR */
 static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
 __ror(uint32_t __x, uint32_t __y) {

 static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
 __clzll(uint64_t __t) {
   return __builtin_clzll(__t);
 }
 
 /* CLS */
 static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
 __cls(uint32_t __t) {
   return __builtin_arm_cls(__t);
 }
 
 static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
 __clsl(unsigned long __t) {
 #if __SIZEOF_LONG__ == 4
   return __builtin_arm_cls(__t);
 #else
   return __builtin_arm_cls64(__t);
 #endif
 }
 
 static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
 __clsll(uint64_t __t) {
   return __builtin_arm_cls64(__t);
 }
 
 /* REV */
 static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
 __rev(uint32_t __t) {
   return __builtin_bswap32(__t);
 }
 

 static __inline__ int16_t __attribute__((__always_inline__, __nodebug__))
 __revsh(int16_t __t) {
   return __builtin_bswap16(__t);
 }
 
 /* RBIT */
 static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
 __rbit(uint32_t __t) {
   return __builtin_arm_rbit(__t);
 }
 
 static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
 __rbitll(uint64_t __t) {
 #if __ARM_32BIT_STATE
   return (((uint64_t)__builtin_arm_rbit(__t)) << 32) |
          __builtin_arm_rbit(__t >> 32);
 #else
   return __builtin_arm_rbit64(__t);
 #endif
 }
 
 static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
 __rbitl(unsigned long __t) {
 #if __SIZEOF_LONG__ == 4
   return __rbit(__t);
 #else

 
 #define __tstart()        __builtin_arm_tstart()
 #define __tcommit()       __builtin_arm_tcommit()
 #define __tcancel(__arg)  __builtin_arm_tcancel(__arg)
 #define __ttest()         __builtin_arm_ttest()
 
 #endif /* __ARM_FEATURE_TME */
 
+/* Armv8.5-A Random number generation intrinsics */
+#if __ARM_64BIT_STATE && defined(__ARM_FEATURE_RNG)
+static __inline__ int __attribute__((__always_inline__, __nodebug__))
+__rndr(uint64_t *__p) {
+  return __builtin_arm_rndr(__p);
+}
+static __inline__ int __attribute__((__always_inline__, __nodebug__))
+__rndrrs(uint64_t *__p) {
+  return __builtin_arm_rndrrs(__p);
+}
+#endif
+
 #if defined(__cplusplus)
 }
 #endif
 
 #endif /* __ARM_ACLE_H */

clang/test/CodeGen/arm_acle.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -ffreestanding -triple armv8a-none-eabi -target-feature +crc -target-feature +dsp -O0 -disable-O0-optnone -fexperimental-new-pass-manager -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -check-prefixes=ARM,AArch32
 // RUN: %clang_cc1 -ffreestanding -triple aarch64-none-eabi -target-feature +neon -target-feature +crc -target-feature +crypto -O0 -disable-O0-optnone -fexperimental-new-pass-manager -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -check-prefixes=ARM,AArch64
 // RUN: %clang_cc1 -ffreestanding -triple aarch64-none-eabi -target-feature +v8.3a -O0 -disable-O0-optnone -fexperimental-new-pass-manager -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -check-prefixes=ARM,AArch64,AArch6483
-// RUN: %clang_cc1 -ffreestanding -triple aarch64-none-eabi -target-feature +v8.5a -O0 -disable-O0-optnone -fexperimental-new-pass-manager -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -check-prefixes=ARM,AArch64,AArch6483
+// RUN: %clang_cc1 -ffreestanding -triple aarch64-none-eabi -target-feature +v8.5a -target-feature +rand -O0 -disable-O0-optnone -fexperimental-new-pass-manager -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s -check-prefixes=ARM,AArch64,AArch6483,AArch6485
 
 #include <arm_acle.h>
 
 // REQUIRES: arm-registered-target,aarch64-registered-target
 
 /* 8 SYNCHRONIZATION, BARRIER AND HINT INTRINSICS */
 /* 8.3 Memory Barriers */
 

 // AArch6483-NEXT:    [[TMP0:%.*]] = call i32 @llvm.aarch64.fjcvtzs(double [[V:%.*]]) [[ATTR3:#.*]]
 // AArch6483-NEXT:    ret i32 [[TMP0]]
 //
 int32_t test_jcvt(double v) {
   return __jcvt(v);
 }
 #endif
 
+
+#if __ARM_64BIT_STATE && defined(__ARM_FEATURE_RNG)
+
+// AArch6485-LABEL: @test_rndr(
+// AArch6485-NEXT:  entry:
+// AArch6485-NEXT:    [[TMP0:%.*]] = call { i64, i1 } @llvm.aarch64.rndr() [[ATTR3:#.*]]
+// AArch6485-NEXT:    [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 0
+// AArch6485-NEXT:    [[TMP2:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1
+// AArch6485-NEXT:    store i64 [[TMP1]], i64* [[__ADDR:%.*]], align 8
+// AArch6485-NEXT:    [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
+// AArch6485-NEXT:    ret i32 [[TMP3]]
+//
+int test_rndr(uint64_t *__addr) {
+  return __rndr(__addr);
+}
+
+// AArch6485-LABEL: @test_rndrrs(
+// AArch6485-NEXT:  entry:
+// AArch6485-NEXT:    [[TMP0:%.*]] = call { i64, i1 } @llvm.aarch64.rndrrs() [[ATTR3:#.*]]
+// AArch6485-NEXT:    [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 0
+// AArch6485-NEXT:    [[TMP2:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1
+// AArch6485-NEXT:    store i64 [[TMP1]], i64* [[__ADDR:%.*]], align 8
+// AArch6485-NEXT:    [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
+// AArch6485-NEXT:    ret i32 [[TMP3]]
+//
+int test_rndrrs(uint64_t *__addr) {
+  return __rndrrs(__addr);
+}
+#endif
+
 // AArch32: !5 = !{!"cp1:2:c3:c4:5"}
 // AArch32: !6 = !{!"cp1:2:c3"}
 // AArch32: !7 = !{!"sysreg"}
 
 // AArch64: !8 = !{!"1:2:3:4:5"}
 // AArch64: !9 = !{!"sysreg"}

clang/test/CodeGen/builtins-arm64.c

unsigned int clsl(unsigned long v) {
   return __builtin_arm_cls64(v);
 }
 
 unsigned int clsll(uint64_t v) {
   // CHECK: call i32 @llvm.aarch64.cls64(i64 %v)
   return __builtin_arm_cls64(v);
 }
 
+// CHECK-LABEL: @rndr(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call { i64, i1 } @llvm.aarch64.rndr()
+// CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 0
+// CHECK-NEXT:    [[TMP2:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1
+// CHECK-NEXT:    store i64 [[TMP1]], i64* [[__ADDR:%.*]], align 8
+// CHECK-NEXT:    [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
+// CHECK-NEXT:    ret i32 [[TMP3]]
+//
+int rndr(uint64_t *__addr) {
+  return __builtin_arm_rndr(__addr);
+}
+
+// CHECK-LABEL: @rndrrs(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:    [[TMP0:%.*]] = call { i64, i1 } @llvm.aarch64.rndrrs()
+// CHECK-NEXT:    [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 0
+// CHECK-NEXT:    [[TMP2:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1
+// CHECK-NEXT:    store i64 [[TMP1]], i64* [[__ADDR:%.*]], align 8
+// CHECK-NEXT:    [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
+// CHECK-NEXT:    ret i32 [[TMP3]]
+//
+int rndrrs(uint64_t *__addr) {
+  return __builtin_arm_rndrrs(__addr);
+}
+
 // CHECK: ![[M0]] = !{!"1:2:3:4:5"}

clang/test/Preprocessor/aarch64-target-features.c

 // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=pac-ret+b-key -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-BTI-OFF %s
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=pac-ret+leaf+b-key -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-BTI-OFF %s
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=standard -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-BTI %s
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=bti -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-BTI %s
 // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -mbranch-protection=pac-ret+bti -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-BTI %s
 // CHECK-BTI-OFF-NOT: __ARM_FEATURE_BTI_DEFAULT
 // CHECK-BTI:         #define __ARM_FEATURE_BTI_DEFAULT 1
 
+// ================== Check Armv8.5-A random number generation extension.
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.5-a+rng -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-RNG %s
+// RUN: %clang -target aarch64-arm-none-eabi -march=armv8.5-a x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-NO-RNG %s
+// CHECK-RNG: __ARM_FEATURE_RNG 1
+// CHECK-NO-RNG-NOT: __ARM_FEATURE_RNG 1
+
 // ================== Check BFloat16 Extensions.
 // RUN: %clang -target aarch64-arm-none-eabi -march=armv8.6-a+bf16 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-BFLOAT %s
 // CHECK-BFLOAT: __ARM_BF16_FORMAT_ALTERNATIVE 1
 // CHECK-BFLOAT: __ARM_FEATURE_BF16 1
 // CHECK-BFLOAT: __ARM_FEATURE_BF16_VECTOR_ARITHMETIC 1
 
 // ================== Check Armv8.7-A LS64 extension.
 // RUN: %clang -target aarch64-arm-none-eabi -march=armv8.7-a+ls64 -x c -E -dM %s -o - 2>&1 | FileCheck -check-prefix=CHECK-LS64 %s

llvm/include/llvm/IR/IntrinsicsAArch64.td

 def int_aarch64_neon_tbx3 : AdvSIMD_Tbx3_Intrinsic;
 def int_aarch64_neon_tbx4 : AdvSIMD_Tbx4_Intrinsic;
 
 let TargetPrefix = "aarch64" in {
   class FPCR_Get_Intrinsic
     : DefaultAttrsIntrinsic<[llvm_i64_ty], [], [IntrNoMem, IntrHasSideEffects]>;
   class FPCR_Set_Intrinsic
     : DefaultAttrsIntrinsic<[], [llvm_i64_ty], [IntrNoMem, IntrHasSideEffects]>;
+  class RNDR_Intrinsic
+    : DefaultAttrsIntrinsic<[llvm_i64_ty, llvm_i1_ty], [], [IntrNoMem, IntrHasSideEffects]>;
 }
 
 // FPCR
 def int_aarch64_get_fpcr : FPCR_Get_Intrinsic;
 def int_aarch64_set_fpcr : FPCR_Set_Intrinsic;
 
+// Armv8.5-A Random number generation intrinsics
+def int_aarch64_rndr : RNDR_Intrinsic;
+def int_aarch64_rndrrs : RNDR_Intrinsic;
+
 let TargetPrefix = "aarch64" in {
   class Crypto_AES_DataKey_Intrinsic
     : DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_v16i8_ty], [IntrNoMem]>;
 
   class Crypto_AES_Data_Intrinsic
     : DefaultAttrsIntrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
 
   // SHA intrinsic taking 5 words of the hash (v4i32, i32) and 4 of the schedule

llvm/lib/Target/AArch64/AArch64ISelLowering.h

enum NodeType : unsigned {
 
   /// Natural vector cast. ISD::BITCAST is not natural in the big-endian
   /// world w.r.t vectors; which causes additional REV instructions to be
   /// generated to compensate for the byte-swapping. But sometimes we do
   /// need to re-interpret the data in SIMD vector registers in big-endian
   /// mode without emitting such REV instructions.
   NVCAST,
 
+  MRS, // MRS, also sets the flags via a glue.
+
   SMULL,
   UMULL,
 
   // Reciprocal estimates and steps.
   FRECPE,
   FRECPS,
   FRSQRTE,
   FRSQRTS,

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

case AArch64ISD::FIRST_NUMBER:
     MAKE_CASE(AArch64ISD::CBNZ)
     MAKE_CASE(AArch64ISD::TBZ)
     MAKE_CASE(AArch64ISD::TBNZ)
     MAKE_CASE(AArch64ISD::TC_RETURN)
     MAKE_CASE(AArch64ISD::PREFETCH)
     MAKE_CASE(AArch64ISD::SITOF)
     MAKE_CASE(AArch64ISD::UITOF)
     MAKE_CASE(AArch64ISD::NVCAST)
+    MAKE_CASE(AArch64ISD::MRS)
     MAKE_CASE(AArch64ISD::SQSHL_I)
     MAKE_CASE(AArch64ISD::UQSHL_I)
     MAKE_CASE(AArch64ISD::SRSHR_I)
     MAKE_CASE(AArch64ISD::URSHR_I)
     MAKE_CASE(AArch64ISD::SQSHLU_I)
     MAKE_CASE(AArch64ISD::WrapperLarge)
     MAKE_CASE(AArch64ISD::LD2post)
     MAKE_CASE(AArch64ISD::LD3post)
case Intrinsic::aarch64_sve_ld4: {
       SDValue BasePtr = N->getOperand(3);
       SDValue LoadOps[] = {Chain, Mask, BasePtr};
       unsigned IntrinsicID =
           cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
       SDValue Result =
           LowerSVEStructLoad(IntrinsicID, LoadOps, N->getValueType(0), DAG, DL);
       return DAG.getMergeValues({Result, Chain}, DL);
     }
+    case Intrinsic::aarch64_rndr:
+    case Intrinsic::aarch64_rndrrs: {
+      unsigned IntrinsicID =
+          cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+      auto Register =
+          (IntrinsicID == Intrinsic::aarch64_rndr ? AArch64SysReg::RNDR
+                                                  : AArch64SysReg::RNDRRS);
+      SDLoc DL(N);
+      SDValue A = DAG.getNode(
+          AArch64ISD::MRS, DL, DAG.getVTList(MVT::i64, MVT::Glue, MVT::Other),
+          N->getOperand(0), DAG.getConstant(Register, DL, MVT::i64));
+      SDValue B = DAG.getNode(
+          AArch64ISD::CSINC, DL, MVT::i32, DAG.getConstant(0, DL, MVT::i32),
+          DAG.getConstant(0, DL, MVT::i32),
+          DAG.getConstant(AArch64CC::NE, DL, MVT::i32), A.getValue(1));
+      return DAG.getMergeValues(
+          {A, DAG.getZExtOrTrunc(B, DL, MVT::i1), A.getValue(2)}, DL);
+    }
     default:
       break;
     }
     break;
   case ISD::GlobalAddress:
     return performGlobalAddressCombine(N, DAG, Subtarget, getTargetMachine());
   }
   return SDValue();

llvm/lib/Target/AArch64/AArch64InstrFormats.td

def btihint_op : Operand<i32> {
   }];
 }
 
 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
                        "mrs", "\t$Rt, $systemreg"> {
   bits<16> systemreg;
   let Inst{20-5} = systemreg;
   let DecoderNamespace = "Fallback";
+  // The MRS is set as a NZCV setting instruction. Not all MRS instructions
+  // require doing this. The alternative was to explicitly model each one, but
+  // it feels like it is unnecessary because it seems there are no negative
+  // consequences setting these flags for all.
+  let Defs = [NZCV];
 }
 
 // FIXME: Some of these def NZCV, others don't. Best way to model that?
 // Explicitly modeling each of the system register as a register class
 // would do it, but feels like overkill at this point.
 class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
                        "msr", "\t$systemreg, $Rt"> {
   bits<16> systemreg;

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 def AArch64uunpkhi : SDNode<"AArch64ISD::UUNPKHI", SDT_AArch64unpk>;
 def AArch64uunpklo : SDNode<"AArch64ISD::UUNPKLO", SDT_AArch64unpk>;
 
 def AArch64ldp : SDNode<"AArch64ISD::LDP", SDT_AArch64ldp, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
 def AArch64stp : SDNode<"AArch64ISD::STP", SDT_AArch64stp, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 def AArch64stnp : SDNode<"AArch64ISD::STNP", SDT_AArch64stnp, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
 
 def AArch64tbl : SDNode<"AArch64ISD::TBL", SDT_AArch64TBL>;
-
+def AArch64mrs : SDNode<"AArch64ISD::MRS",
+                        SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, i32>]>,
+                        [SDNPHasChain, SDNPOutGlue]>;
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 
 // AArch64 Instruction Predicate Definitions.
 // We could compute these on a per-module basis but doing so requires accessing
 // the Function object through the <Target>Subtarget and objections were raised
 // to that (see post-commit review comments for r301750).

 def : InstAlias<"ssbb", (DSB 0)>;
 def : InstAlias<"pssbb", (DSB 4)>;
 
 def MRS    : MRSI;
 def MSR    : MSRI;
 def MSRpstateImm1 : MSRpstateImm0_1;
 def MSRpstateImm4 : MSRpstateImm0_15;
 
+def : Pat<(AArch64mrs imm:$id),
+          (MRS imm:$id)>;
+
 // The thread pointer (on Linux, at least, where this has been implemented) is
 // TPIDR_EL0.
 def MOVbaseTLS : Pseudo<(outs GPR64:$dst), (ins),
                        [(set GPR64:$dst, AArch64threadpointer)]>, Sched<[WriteSys]>;
 
 let Uses = [ X9 ], Defs = [ X16, X17, LR, NZCV ] in {
 def HWASAN_CHECK_MEMACCESS : Pseudo<
   (outs), (ins GPR64noip:$ptr, i32imm:$accessinfo),
   [(int_hwasan_check_memaccess X9, GPR64noip:$ptr, (i32 timm:$accessinfo))]>,
   Sched<[]>;
 }

llvm/test/CodeGen/AArch64/rand.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64 -mattr=+v8.5a,+rand %s -o - | FileCheck %s
+
+define  i32 @rndr(i64* %__addr) {
+; CHECK-LABEL: rndr:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mrs x9, RNDR
+; CHECK-NEXT:    cset w8, eq
+; CHECK-NEXT:    and w8, w8, #0x1
+; CHECK-NEXT:    str x9, [x0]
+; CHECK-NEXT:    mov w0, w8
+; CHECK-NEXT:    ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndr()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+
+define  i32 @rndrrs(i64*  %__addr) {
+; CHECK-LABEL: rndrrs:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mrs x9, RNDRRS
+; CHECK-NEXT:    cset w8, eq
+; CHECK-NEXT:    and w8, w8, #0x1
+; CHECK-NEXT:    str x9, [x0]
+; CHECK-NEXT:    mov w0, w8
+; CHECK-NEXT:    ret
+  %1 = tail call { i64, i1 } @llvm.aarch64.rndrrs()
+  %2 = extractvalue { i64, i1 } %1, 0
+  %3 = extractvalue { i64, i1 } %1, 1
+  store i64 %2, i64* %__addr, align 8
+  %4 = zext i1 %3 to i32
+  ret i32 %4
+}
+
+declare { i64, i1 } @llvm.aarch64.rndr()
+declare { i64, i1 } @llvm.aarch64.rndrrs()

llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

liveins:
   - { reg: '$x0' }
 frameInfo:
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $x0
 
-    renamable $x8 = MRS 58880
+    renamable $x8 = MRS 58880, implicit-def $nzcv
     renamable $x8 = MOVZXi 15309, 0
     renamable $x8 = MOVKXi renamable $x8, 26239, 16
     STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 8)
-    renamable $x8 = MRS 55840
+    renamable $x8 = MRS 55840, implicit-def $nzcv
     STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 8)
     RET undef $lr
 
 ...
 ---
 # CHECK-LABEL: name: test4
 # CHECK-LABEL:  bb.0:
 # CHECK-NEXT:    liveins: $x0, $x1

 frameInfo:
   maxAlignment:    1
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $x0, $x1
 
-    renamable $x8 = MRS 58880
+    renamable $x8 = MRS 58880, implicit-def $nzcv
     STRXui renamable $x8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-    renamable $x8 = MRS 55840
+    renamable $x8 = MRS 55840, implicit-def $nzcv
     STRXui killed renamable  $x8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
     RET undef $lr
 
 ...
 ---
 # CHECK-LABEL: name: test5
 # CHECK-LABEL:  bb.0:
 # CHECK-NEXT:    liveins: $x0, $x1

 frameInfo:
   maxAlignment:    1
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $x0, $x1
 
-    renamable $x8 = MRS 58880
+    renamable $x8 = MRS 58880, implicit-def $nzcv
     STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-    renamable $x8 = MRS 55840
+    renamable $x8 = MRS 55840, implicit-def $nzcv
     STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
     RET undef $lr
 
 ...
 ---
 # CHECK-LABEL: name: test6
 # CHECK-LABEL: bb.0:
 # CHECK:    liveins: $x0, $x1, $q3

 frameInfo:
   maxAlignment:    1
   maxCallFrameSize: 0
 machineFunctionInfo: {}
 body:             |
   bb.0:
     liveins: $x0, $x1
 
-    renamable $x8 = MRS 58880
+    renamable $x8 = MRS 58880, implicit-def $nzcv
     renamable $w8 = ORRWrs $wzr, killed renamable $w8, 0, implicit-def $x8
     STRWui renamable $w8, renamable $x0, 0, implicit killed $x8 :: (store 4)
-    renamable $x8 = MRS 55840
+    renamable $x8 = MRS 55840, implicit-def $nzcv
     STRWui killed renamable $w8, renamable killed $x0, 1, implicit killed $x8 :: (store 4)
     RET undef $lr
 
 ...
 ---
 # The reg class returned for $q9 contains only the first 16 Q registers.
 # TODO: Can we check that all instructions that require renaming also support
 #       the second 16 Q registers?