Addressed the comment of @dmgreen.

Addressed the comments.

@dmgreen Will do.

@nathanchance Great! Thanks for the update.

Follow up fix: https://reviews.llvm.org/D101888

@nickdesaulniers This patch is a possible fix for the issue, do you mind testing if it's now OK?
@dmgreen I added one in the patch.

Modified the Cortex-A53 test and added one for Cortex-A55.

Addressed the comments made by @dmgreen.

Addressed the comments made by @dmgreen (Thanks for the comments!)

1. Added more test cases
2. Refactoring
3. Added support for LDUR<>i<>Ri/STUR<>i
4. Changed the code so that the same Pre Ld/St Opcodes are not candidates to merge/pair.

1. Added more test cases.
2. Addressed the remarks.

Added back some of the atomic tests.

1. Added comments to the new test.
2. Fixed the failing AMDGPU tests.

In D100383#2688643, @SjoerdMeijer wrote:

And forgot to add, and just double checking, this passes your bootstrap build and test again?

In this link you can see how it results in an error.

1. Added a test that triggers the assertion failure.
2. Changed the isLegalUse parameters in LSRInstance::GenerateConstantOffsetsImpl to look the same as the assertion used for illegal formulas.

In D100383#2685704, @SjoerdMeijer wrote:

I am afraid we need to add a test case for this because this doesn't seem to be covered by existing tests. So, I think you need to make a minimal reproducer of the input file that triggers the assertion failure.

Removed the hack that was used to avoid the memoperands_empty() check for LDR<>pre instructions.

Closed by git revision a655f250fef84795e3e46c0bcb824d7b5fbceec6.

In D99272#2647947, @SjoerdMeijer wrote:

Hi Stelios, many thanks for putting this together, good stuff.
I will do a code-review a bit later, but as there's potential for some corner cases here, first a testing question. Did you do a bootstrap build and e.g. ran the llvm test suite?

1. Added all the various forms of STR<>pre/LDR<>pre.
2. Added additional test cases for the MIR tests to cover the various forms of STR<>pre/LDR<>pre.
3. Added constraints so that it optimizes cases where the offset of the second LDR/STR<>ui is equal to the size of the destination register. Additionally, it only optimizes cases where the base register of the pre-index LDR/STRpre<> is not used or modified.
4. Did a bootstrap build and ran the llvm test-suite on an AArch64 machine. Both the test-suite and regression tests results in no errors.
5. Currently there is a hack to avoid the memoperands_empty() check for LDR<>pre instructions. This is because they are missing the load memory operand. See below:

Typo fix for __ARM_FEATURE_RNG macro check in aarch64-target-features.c.

Changed the rand.ll llc arguments to the ones that are only relevant.

Added tests in arm_acle.c.

1. Removed a redundant comment
2. Removed the changes made in the test/CodeGen/arm_acle.c, since the test is disabled.
3. Added a clang preprocessor test to check the presence and absence of the __ARM_FEATURE_RNG macro.

Rephrased a comment.

1. Addressed the comment made by @SjoerdMeijer and added the comment for the MRS instruction.
2. Added the +rang feature in arm_acle.c

Addressed the comments made by @SjoerdMeijer and @dmgreen.

@SjoerdMeijer @dmgreen Thanks for your reviews, I will be looking into this.

Closed by git revision 30cb9c03b53ee03af2cdf16f4ee645e5dcff7e21.