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Differential D96741

[RISCV] Add support for fixed vector mask logic operations.
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Authored by craig.topper on Feb 15 2021, 6:54 PM.

Details

Reviewers
frasercrmck
HsiangKai
evandro
khchen
arcbbb
Commits
rG07ca13fe0766: [RISCV] Add support for fixed vector mask logic operations.

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Event Timeline

craig.topper created this revision.Feb 15 2021, 6:54 PM
Herald added subscribers: StephenFan, vkmr, luismarques and 24 others. · View Herald TranscriptFeb 15 2021, 6:54 PM
craig.topper requested review of this revision.Feb 15 2021, 6:54 PM
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craig.topper retitled this revision from [RISCV] Add support for fixed vector mask operations. to [RISCV] Add support for fixed vector mask logic operations..Feb 15 2021, 6:55 PM
Harbormaster completed remote builds in B89302: Diff 323862.Feb 15 2021, 7:33 PM
frasercrmck accepted this revision.Feb 16 2021, 2:24 AM

LGTM other than my suggestion.

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
563–564

I wonder if a PatFrag for our "vnot_vl" would simplify some of these?

This revision is now accepted and ready to land.Feb 16 2021, 2:24 AM
Closed by commit rG07ca13fe0766: [RISCV] Add support for fixed vector mask logic operations. (authored by craig.topper). · Explain WhyFeb 16 2021, 9:37 AM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG07ca13fe0766: [RISCV] Add support for fixed vector mask logic operations..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
7 lines
28 lines
37 lines
test/
CodeGen/
RISCV/
rvv/
180 lines

Diff 324038

llvm/lib/Target/RISCV/RISCVISelLowering.h

Show First 20 Lines • Show All 401 Lines • ▼ Show 20 Linesprivate:
SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const; SDValue lowerVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFPVECREDUCE(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFixedLengthVectorLoadToRVV(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFixedLengthVectorStoreToRVV(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const; SDValue lowerFixedLengthVectorSetccToRVV(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, SDValue lowerFixedLengthVectorLogicOpToRVV(SDValue Op, SelectionDAG &DAG,
unsigned NewOpc) const; unsigned MaskOpc,
unsigned VecOpc) const;
SDValue lowerToScalableOp(SDValue Op, SelectionDAG &DAG, unsigned NewOpc,
bool HasMask = true) const;
bool isEligibleForTailCallOptimization( bool isEligibleForTailCallOptimization(
CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF, CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
const SmallVector<CCValAssign, 16> &ArgLocs) const; const SmallVector<CCValAssign, 16> &ArgLocs) const;
/// Generate error diagnostics if any register used by CC has been marked /// Generate error diagnostics if any register used by CC has been marked
/// reserved. /// reserved.
void validateCCReservedRegs( void validateCCReservedRegs(
▲ Show 20 Lines • Show All 44 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Show First 20 Lines • Show All 525 Lines • ▼ Show 20 Lines if (Subtarget.useRVVForFixedLengthVectors()) {
setOperationAction(ISD::BUILD_VECTOR, VT, Custom); setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
setOperationAction(ISD::LOAD, VT, Custom); setOperationAction(ISD::LOAD, VT, Custom);
setOperationAction(ISD::STORE, VT, Custom); setOperationAction(ISD::STORE, VT, Custom);
// Operations below are different for between masks and other vectors. // Operations below are different for between masks and other vectors.
if (VT.getVectorElementType() == MVT::i1) { if (VT.getVectorElementType() == MVT::i1) {
setOperationAction(ISD::AND, VT, Custom);
setOperationAction(ISD::OR, VT, Custom);
setOperationAction(ISD::XOR, VT, Custom);
setOperationAction(ISD::SETCC, VT, Custom); setOperationAction(ISD::SETCC, VT, Custom);
continue; continue;
} }
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
setOperationAction(ISD::ADD, VT, Custom); setOperationAction(ISD::ADD, VT, Custom);
setOperationAction(ISD::MUL, VT, Custom); setOperationAction(ISD::MUL, VT, Custom);
▲ Show 20 Lines • Show All 662 Lines • ▼ Show 20 Lines case ISD::SETCC:
return lowerFixedLengthVectorSetccToRVV(Op, DAG); return lowerFixedLengthVectorSetccToRVV(Op, DAG);
case ISD::ADD: case ISD::ADD:
return lowerToScalableOp(Op, DAG, RISCVISD::ADD_VL); return lowerToScalableOp(Op, DAG, RISCVISD::ADD_VL);
case ISD::SUB: case ISD::SUB:
return lowerToScalableOp(Op, DAG, RISCVISD::SUB_VL); return lowerToScalableOp(Op, DAG, RISCVISD::SUB_VL);
case ISD::MUL: case ISD::MUL:
return lowerToScalableOp(Op, DAG, RISCVISD::MUL_VL); return lowerToScalableOp(Op, DAG, RISCVISD::MUL_VL);
case ISD::AND: case ISD::AND:
return lowerToScalableOp(Op, DAG, RISCVISD::AND_VL); return lowerFixedLengthVectorLogicOpToRVV(Op, DAG, RISCVISD::VMAND_VL,
RISCVISD::AND_VL);
case ISD::OR: case ISD::OR:
return lowerToScalableOp(Op, DAG, RISCVISD::OR_VL); return lowerFixedLengthVectorLogicOpToRVV(Op, DAG, RISCVISD::VMOR_VL,
RISCVISD::OR_VL);
case ISD::XOR: case ISD::XOR:
return lowerToScalableOp(Op, DAG, RISCVISD::XOR_VL); return lowerFixedLengthVectorLogicOpToRVV(Op, DAG, RISCVISD::VMXOR_VL,
RISCVISD::XOR_VL);
case ISD::SDIV: case ISD::SDIV:
return lowerToScalableOp(Op, DAG, RISCVISD::SDIV_VL); return lowerToScalableOp(Op, DAG, RISCVISD::SDIV_VL);
case ISD::SREM: case ISD::SREM:
return lowerToScalableOp(Op, DAG, RISCVISD::SREM_VL); return lowerToScalableOp(Op, DAG, RISCVISD::SREM_VL);
case ISD::UDIV: case ISD::UDIV:
return lowerToScalableOp(Op, DAG, RISCVISD::UDIV_VL); return lowerToScalableOp(Op, DAG, RISCVISD::UDIV_VL);
case ISD::UREM: case ISD::UREM:
return lowerToScalableOp(Op, DAG, RISCVISD::UREM_VL); return lowerToScalableOp(Op, DAG, RISCVISD::UREM_VL);
▲ Show 20 Lines • Show All 1,001 Lines • ▼ Show 20 LinesRISCVTargetLowering::lowerFixedLengthVectorSetccToRVV(SDValue Op,
if (Invert) { if (Invert) {
SDValue AllOnes = DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL); SDValue AllOnes = DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL);
Cmp = DAG.getNode(RISCVISD::VMXOR_VL, DL, MaskVT, Cmp, AllOnes, VL); Cmp = DAG.getNode(RISCVISD::VMXOR_VL, DL, MaskVT, Cmp, AllOnes, VL);
} }
return convertFromScalableVector(VT, Cmp, DAG, Subtarget); return convertFromScalableVector(VT, Cmp, DAG, Subtarget);
} }
SDValue RISCVTargetLowering::lowerFixedLengthVectorLogicOpToRVV(
SDValue Op, SelectionDAG &DAG, unsigned MaskOpc, unsigned VecOpc) const {
MVT VT = Op.getSimpleValueType();
if (VT.getVectorElementType() == MVT::i1)
return lowerToScalableOp(Op, DAG, MaskOpc, /*HasMask*/ false);
return lowerToScalableOp(Op, DAG, VecOpc, /*HasMask*/ true);
}
SDValue RISCVTargetLowering::lowerToScalableOp(SDValue Op, SelectionDAG &DAG, SDValue RISCVTargetLowering::lowerToScalableOp(SDValue Op, SelectionDAG &DAG,
unsigned NewOpc) const { unsigned NewOpc,
bool HasMask) const {
MVT VT = Op.getSimpleValueType(); MVT VT = Op.getSimpleValueType();
assert(useRVVForFixedLengthVectorVT(VT) && assert(useRVVForFixedLengthVectorVT(VT) &&
"Only expected to lower fixed length vector operation!"); "Only expected to lower fixed length vector operation!");
MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget); MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
// Create list of operands by converting existing ones to scalable types. // Create list of operands by converting existing ones to scalable types.
SmallVector<SDValue, 6> Ops; SmallVector<SDValue, 6> Ops;
for (const SDValue &V : Op->op_values()) { for (const SDValue &V : Op->op_values()) {
Show All 9 Lines for (const SDValue &V : Op->op_values()) {
assert(useRVVForFixedLengthVectorVT(V.getSimpleValueType()) && assert(useRVVForFixedLengthVectorVT(V.getSimpleValueType()) &&
"Only fixed length vectors are supported!"); "Only fixed length vectors are supported!");
Ops.push_back(convertToScalableVector(ContainerVT, V, DAG, Subtarget)); Ops.push_back(convertToScalableVector(ContainerVT, V, DAG, Subtarget));
} }
SDLoc DL(Op); SDLoc DL(Op);
SDValue Mask, VL; SDValue Mask, VL;
std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget); std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
if (HasMask)
Ops.push_back(Mask); Ops.push_back(Mask);
Ops.push_back(VL); Ops.push_back(VL);
SDValue ScalableRes = DAG.getNode(NewOpc, DL, ContainerVT, Ops); SDValue ScalableRes = DAG.getNode(NewOpc, DL, ContainerVT, Ops);
return convertFromScalableVector(VT, ScalableRes, DAG, Subtarget); return convertFromScalableVector(VT, ScalableRes, DAG, Subtarget);
} }
// Returns the opcode of the target-specific SDNode that implements the 32-bit // Returns the opcode of the target-specific SDNode that implements the 32-bit
// form of the given Opcode. // form of the given Opcode.
▲ Show 20 Lines • Show All 3,165 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Show First 20 Lines • Show All 120 Lines • ▼ Show 20 Lines
def SDT_RISCVVMSETCLR_VL : SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i1>, def SDT_RISCVVMSETCLR_VL : SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i1>,
SDTCisVT<1, XLenVT>]>; SDTCisVT<1, XLenVT>]>;
def riscv_vmclr_vl : SDNode<"RISCVISD::VMCLR_VL", SDT_RISCVVMSETCLR_VL>; def riscv_vmclr_vl : SDNode<"RISCVISD::VMCLR_VL", SDT_RISCVVMSETCLR_VL>;
def riscv_vmset_vl : SDNode<"RISCVISD::VMSET_VL", SDT_RISCVVMSETCLR_VL>; def riscv_vmset_vl : SDNode<"RISCVISD::VMSET_VL", SDT_RISCVVMSETCLR_VL>;
def true_mask : PatLeaf<(riscv_vmset_vl (XLenVT srcvalue))>; def true_mask : PatLeaf<(riscv_vmset_vl (XLenVT srcvalue))>;
def riscv_vmnot_vl : PatFrag<(ops node:$rs, node:$vl),
(riscv_vmxor_vl node:$rs, true_mask, node:$vl)>;
// Ignore the vl operand. // Ignore the vl operand.
def SplatFPOp : PatFrag<(ops node:$op), def SplatFPOp : PatFrag<(ops node:$op),
(riscv_vfmv_v_f_vl node:$op, srcvalue)>; (riscv_vfmv_v_f_vl node:$op, srcvalue)>;
def sew8simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<8>", []>; def sew8simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<8>", []>;
def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>; def sew16simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<16>", []>;
def sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>; def sew32simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<32>", []>;
def sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>; def sew64simm5 : ComplexPattern<XLenVT, 1, "selectRVVSimm5<64>", []>;
▲ Show 20 Lines • Show All 415 Lines • ▼ Show 20 Lines def : Pat<(mti.Mask (riscv_vmand_vl VR:$rs1, VR:$rs2, (XLenVT (VLOp GPR:$vl)))),
(!cast<Instruction>("PseudoVMAND_MM_" # mti.LMul.MX) (!cast<Instruction>("PseudoVMAND_MM_" # mti.LMul.MX)
VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>; VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>;
def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, VR:$rs2, (XLenVT (VLOp GPR:$vl)))), def : Pat<(mti.Mask (riscv_vmor_vl VR:$rs1, VR:$rs2, (XLenVT (VLOp GPR:$vl)))),
(!cast<Instruction>("PseudoVMOR_MM_" # mti.LMul.MX) (!cast<Instruction>("PseudoVMOR_MM_" # mti.LMul.MX)
VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>; VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>;
def : Pat<(mti.Mask (riscv_vmxor_vl VR:$rs1, VR:$rs2, (XLenVT (VLOp GPR:$vl)))), def : Pat<(mti.Mask (riscv_vmxor_vl VR:$rs1, VR:$rs2, (XLenVT (VLOp GPR:$vl)))),
(!cast<Instruction>("PseudoVMXOR_MM_" # mti.LMul.MX) (!cast<Instruction>("PseudoVMXOR_MM_" # mti.LMul.MX)
VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>; VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>;
// FIXME: Add remaining mask instructions. def : Pat<(mti.Mask (riscv_vmand_vl (riscv_vmnot_vl VR:$rs1,
frasercrmckUnsubmitted
Not Done
ReplyInline Actions

I wonder if a PatFrag for our "vnot_vl" would simplify some of these?

frasercrmck: I wonder if a PatFrag for our "vnot_vl" would simplify some of these?
def : Pat<(mti.Mask (riscv_vmxor_vl (riscv_vmor_vl VR:$rs1, VR:$rs2, (XLenVT (VLOp GPR:$vl))),
VR:$rs2, (XLenVT (VLOp GPR:$vl)))),
(!cast<Instruction>("PseudoVMANDNOT_MM_" # mti.LMul.MX)
VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>;
def : Pat<(mti.Mask (riscv_vmor_vl (riscv_vmnot_vl VR:$rs1,
(XLenVT (VLOp GPR:$vl))),
VR:$rs2, (XLenVT (VLOp GPR:$vl)))),
(!cast<Instruction>("PseudoVMORNOT_MM_" # mti.LMul.MX)
VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>;
// XOR is associative so we need 2 patterns for VMXNOR.
def : Pat<(mti.Mask (riscv_vmxor_vl (riscv_vmnot_vl VR:$rs1,
(XLenVT (VLOp GPR:$vl))),
VR:$rs2, (XLenVT (VLOp GPR:$vl)))),
(!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX)
VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>;
def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmand_vl VR:$rs1, VR:$rs2,
(XLenVT (VLOp GPR:$vl))), (XLenVT (VLOp GPR:$vl))),
true_mask, (XLenVT (VLOp GPR:$vl)))), (XLenVT (VLOp GPR:$vl)))),
(!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX)
VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>;
def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmor_vl VR:$rs1, VR:$rs2,
(XLenVT (VLOp GPR:$vl))),
(XLenVT (VLOp GPR:$vl)))),
(!cast<Instruction>("PseudoVMNOR_MM_" # mti.LMul.MX) (!cast<Instruction>("PseudoVMNOR_MM_" # mti.LMul.MX)
VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>; VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>;
def : Pat<(mti.Mask (riscv_vmnot_vl (riscv_vmxor_vl VR:$rs1, VR:$rs2,
(XLenVT (VLOp GPR:$vl))),
(XLenVT (VLOp GPR:$vl)))),
(!cast<Instruction>("PseudoVMXNOR_MM_" # mti.LMul.MX)
VR:$rs1, VR:$rs2, GPR:$vl, mti.SEW)>;
// Match the not idiom to the vnot.mm pseudo. // Match the not idiom to the vnot.mm pseudo.
def : Pat<(mti.Mask (riscv_vmxor_vl VR:$rs, true_mask, (XLenVT (VLOp GPR:$vl)))), def : Pat<(mti.Mask (riscv_vmnot_vl VR:$rs, (XLenVT (VLOp GPR:$vl)))),
(!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX) (!cast<Instruction>("PseudoVMNAND_MM_" # mti.LMul.MX)
VR:$rs, VR:$rs, GPR:$vl, mti.SEW)>; VR:$rs, VR:$rs, GPR:$vl, mti.SEW)>;
} }
} // Predicates = [HasStdExtV] } // Predicates = [HasStdExtV]
// 17.4. Vector Register GAther Instruction // 17.4. Vector Register GAther Instruction
let Predicates = [HasStdExtV] in { let Predicates = [HasStdExtV] in {
▲ Show 20 Lines • Show All 91 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK
define void @and_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
; CHECK-LABEL: and_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 8
; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu
; CHECK-NEXT: vle1.v v25, (a0)
; CHECK-NEXT: vle1.v v26, (a1)
; CHECK-NEXT: vmand.mm v25, v25, v26
; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret
%a = load <8 x i1>, <8 x i1>* %x
%b = load <8 x i1>, <8 x i1>* %y
%c = and <8 x i1> %a, %b
store <8 x i1> %c, <8 x i1>* %x
ret void
}
define void @or_v16i1(<16 x i1>* %x, <16 x i1>* %y) {
; CHECK-LABEL: or_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 16
; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu
; CHECK-NEXT: vle1.v v25, (a0)
; CHECK-NEXT: vle1.v v26, (a1)
; CHECK-NEXT: vmor.mm v25, v25, v26
; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret
%a = load <16 x i1>, <16 x i1>* %x
%b = load <16 x i1>, <16 x i1>* %y
%c = or <16 x i1> %a, %b
store <16 x i1> %c, <16 x i1>* %x
ret void
}
define void @xor_v32i1(<32 x i1>* %x, <32 x i1>* %y) {
; CHECK-LABEL: xor_v32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu
; CHECK-NEXT: vle1.v v25, (a0)
; CHECK-NEXT: vle1.v v26, (a1)
; CHECK-NEXT: vmxor.mm v25, v25, v26
; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret
%a = load <32 x i1>, <32 x i1>* %x
%b = load <32 x i1>, <32 x i1>* %y
%c = xor <32 x i1> %a, %b
store <32 x i1> %c, <32 x i1>* %x
ret void
}
define void @not_v64i1(<64 x i1>* %x, <64 x i1>* %y) {
; CHECK-LABEL: not_v64i1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a1, zero, 64
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vle1.v v25, (a0)
; CHECK-NEXT: vmnand.mm v25, v25, v25
; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret
%a = load <64 x i1>, <64 x i1>* %x
%b = load <64 x i1>, <64 x i1>* %y
%c = xor <64 x i1> %a, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
store <64 x i1> %c, <64 x i1>* %x
ret void
}
define void @andnot_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
; CHECK-LABEL: andnot_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 8
; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu
; CHECK-NEXT: vle1.v v25, (a0)
; CHECK-NEXT: vle1.v v26, (a1)
; CHECK-NEXT: vmandnot.mm v25, v25, v26
; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret
%a = load <8 x i1>, <8 x i1>* %x
%b = load <8 x i1>, <8 x i1>* %y
%c = xor <8 x i1> %a, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
%d = and <8 x i1> %b, %c
store <8 x i1> %d, <8 x i1>* %x
ret void
}
define void @ornot_v16i1(<16 x i1>* %x, <16 x i1>* %y) {
; CHECK-LABEL: ornot_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 16
; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu
; CHECK-NEXT: vle1.v v25, (a0)
; CHECK-NEXT: vle1.v v26, (a1)
; CHECK-NEXT: vmornot.mm v25, v25, v26
; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret
%a = load <16 x i1>, <16 x i1>* %x
%b = load <16 x i1>, <16 x i1>* %y
%c = xor <16 x i1> %a, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
%d = or <16 x i1> %b, %c
store <16 x i1> %d, <16 x i1>* %x
ret void
}
define void @xornot_v32i1(<32 x i1>* %x, <32 x i1>* %y) {
; CHECK-LABEL: xornot_v32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu
; CHECK-NEXT: vle1.v v25, (a0)
; CHECK-NEXT: vle1.v v26, (a1)
; CHECK-NEXT: vmxnor.mm v25, v25, v26
; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret
%a = load <32 x i1>, <32 x i1>* %x
%b = load <32 x i1>, <32 x i1>* %y
%c = xor <32 x i1> %a, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
%d = xor <32 x i1> %b, %c
store <32 x i1> %d, <32 x i1>* %x
ret void
}
define void @nand_v8i1(<8 x i1>* %x, <8 x i1>* %y) {
; CHECK-LABEL: nand_v8i1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 8
; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu
; CHECK-NEXT: vle1.v v25, (a0)
; CHECK-NEXT: vle1.v v26, (a1)
; CHECK-NEXT: vmnand.mm v25, v25, v26
; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret
%a = load <8 x i1>, <8 x i1>* %x
%b = load <8 x i1>, <8 x i1>* %y
%c = and <8 x i1> %a, %b
%d = xor <8 x i1> %c, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
store <8 x i1> %d, <8 x i1>* %x
ret void
}
define void @nor_v16i1(<16 x i1>* %x, <16 x i1>* %y) {
; CHECK-LABEL: nor_v16i1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 16
; CHECK-NEXT: vsetvli a2, a2, e8,m1,ta,mu
; CHECK-NEXT: vle1.v v25, (a0)
; CHECK-NEXT: vle1.v v26, (a1)
; CHECK-NEXT: vmnor.mm v25, v25, v26
; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret
%a = load <16 x i1>, <16 x i1>* %x
%b = load <16 x i1>, <16 x i1>* %y
%c = or <16 x i1> %a, %b
%d = xor <16 x i1> %c, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
store <16 x i1> %d, <16 x i1>* %x
ret void
}
define void @xnor_v32i1(<32 x i1>* %x, <32 x i1>* %y) {
; CHECK-LABEL: xnor_v32i1:
; CHECK: # %bb.0:
; CHECK-NEXT: addi a2, zero, 32
; CHECK-NEXT: vsetvli a2, a2, e8,m2,ta,mu
; CHECK-NEXT: vle1.v v25, (a0)
; CHECK-NEXT: vle1.v v26, (a1)
; CHECK-NEXT: vmxnor.mm v25, v25, v26
; CHECK-NEXT: vse1.v v25, (a0)
; CHECK-NEXT: ret
%a = load <32 x i1>, <32 x i1>* %x
%b = load <32 x i1>, <32 x i1>* %y
%c = xor <32 x i1> %a, %b
%d = xor <32 x i1> %c, <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1>
store <32 x i1> %d, <32 x i1>* %x
ret void
}