AMDGPU: Add target id and code object v4 support

[kzhuravl]

Summary

• Add target id support (https://clang.llvm.org/docs/ClangOffloadBundler.html#target-id)
• Add code object v4 support (https://llvm.org/docs/AMDGPUUsage.html#elf-code-object)
  • Add kernarg_size to kernel descriptor
  • Change trap handler ABI to no longer move queue pointer into s[0:1]
• Cleanup ELF definitions
  • Add V2, V3, V4 suffixes to make a clear distinction for code object version
  • Consolidate note names

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPU.td

873 ↗

(On Diff #319953)

This looks like a separate change

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

129

Why check getTargetStreamer()? Why would htis ever be null? The uses below don't check it

207–208

Probably should use proper context errors here

627

Should use a temp var for getTargetStreaemr()->getTargetId() instead of repeating it so many times

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

5121–5124

Weird naming scheme. lowerTrapHSAQueuePtr?

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

381–390

StringSwitch? Also check the prefix and drop gfx?

[jhenderson]

I've only looked at the llvm-readobj stuff: there are a very large number of changes to that tool in this change, but no direct testing (i.e. tests under llvm\test\llvm-readobj) that has been changed. I'm guessing it's not all covered by existing direct testing of the tool?

llvm/tools/llvm-readobj/ELFDumper.cpp

5011

Whilst I follow what's going on here after reading more carefully, the single byte array is confusing to me. Is there a particular reason for doing it this way, rather than just omitting it and using Desc.data() + sizeof(IsaVersion)? The latter seems more obvious to me.

5052

i -> I. Also LLVM style is to precalculate the end condition where possible. See inline edit.

5055

Could you just return MetadataString directly? Similar comment in other cases.

6115

It seems to me like there's potential for other versions either now or in the future that don't support the V3 flags? Is there a risk this default case will be unintentionally hit in those cases?

[kzhuravl]

In D95638#2530115, @jhenderson wrote:

I've only looked at the llvm-readobj stuff: there are a very large number of changes to that tool in this change, but no direct testing (i.e. tests under llvm\test\llvm-readobj) that has been changed. I'm guessing it's not all covered by existing direct testing of the tool?

It is not covered by the direct testing of the tool (no tests in llvm\test\llvm-readobj), but has a very good coverage in llvm/test/CodeGen/AMDGPU.

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

129

Check is here because the following test is passing "-emit-codegen-only" option to cc1, which executes EmitCodeGenOnlyAction, which does not have MC including target streamer.

Clang :: Misc/backend-resource-limit-diagnostics.cl

The uses below never check it because backend-resource-limit-diagnostics.cl does not specify the os in the triple.

Do you have better suggestions on how to work around it?

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

381–390

Do you suggest converting the whole if-else block into StringSwitch? If yes, how would errors be handled?

In addition there is an else statement saying we do not support the processor in v2:

...
      } else if (Processor == "gfx906") {
        if (isXnackOnOrAny())
          Processor = "gfx907";
      } else {
        report_fatal_error(
            "AMD GPU code object V2 does not support processor " + Processor);
      }

llvm/tools/llvm-readobj/ELFDumper.cpp

5011

I guess this was done to convey more readability. But since it failed, I have changed to the way you suggested.

6115

I think being more explicit is good. Thanks!

[kzhuravl]

Address review feedback.

[MaskRay]

lld/ELF/Arch/AMDGPU.cpp

17

Consider posting lld/ELF changes separately. It is loosely related to the main change.

47

Delete this helper - it is only used once.

55

Delete

59

Delete

63

Delete

101

delete braces around simple statements

106

delete parens

115

delete braces

132

If the value is possible (malformed input), use error instead of unreachable

don't capitalize messages

[kzhuravl]

Address review feedback.

lld/ELF/Arch/AMDGPU.cpp

17

https://reviews.llvm.org/D95811

[kzhuravl]

ping

[kzhuravl]

ping

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

129

I don't understand why the asm printer would ever execute without the streamer. I don't see why the triple would matter, or why it matters for this specific test. What happens if you add a triple to that test?

[kzhuravl]

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

129

I don't understand why the asm printer would ever execute without the streamer.

-emit-codegen-only option results in no streamer being created

I don't see why the triple would matter, or why it matters for this specific test. What happens if you add a triple to that test?

If amdhsa or amdpal is not specified, this function is a NOP. If I add amdhsa or amdpal to triple in the backend-resource-limit-diagnostics.cl test, then it segfaults (without D95638)

I have modified the test to not specify -emit-codegen-only option, which allows us to remove the check here.

https://reviews.llvm.org/D96728

[kzhuravl]

Rebase and remove streamer check in AMDGPUAsmPrinter.cpp

[jhenderson]

In D95638#2531247, @kzhuravl wrote:

In D95638#2530115, @jhenderson wrote:

I've only looked at the llvm-readobj stuff: there are a very large number of changes to that tool in this change, but no direct testing (i.e. tests under llvm\test\llvm-readobj) that has been changed. I'm guessing it's not all covered by existing direct testing of the tool?

It is not covered by the direct testing of the tool (no tests in llvm\test\llvm-readobj), but has a very good coverage in llvm/test/CodeGen/AMDGPU.

Usually we have testing for llvm-readobj behaviour in test/tools/llvm-readobj, so that it can be kept independent of other testing, and so that changes in other areas don't impact test coverage for llvm-readobj. It also makes it easier to keep the tests focused on individual features. For example, what testing is there for EM_AMDGPU objects with an unrecognised ABI Version, or other aspects of that switch?

llvm/test/tools/llvm-readobj/ELF/note-amd.s

27

What are you trying to achieve with these checks? That there is explicit whitespace on this line and nothing else? That seems less than ideal to me. Why would you want that?

llvm/tools/llvm-readobj/ELFDumper.cpp

6115

You need to print an empty Flags field here, for consistency with other output.

[kzhuravl]

In D95638#2564830, @jhenderson wrote:

In D95638#2531247, @kzhuravl wrote:

In D95638#2530115, @jhenderson wrote:

I've only looked at the llvm-readobj stuff: there are a very large number of changes to that tool in this change, but no direct testing (i.e. tests under llvm\test\llvm-readobj) that has been changed. I'm guessing it's not all covered by existing direct testing of the tool?

It is not covered by the direct testing of the tool (no tests in llvm\test\llvm-readobj), but has a very good coverage in llvm/test/CodeGen/AMDGPU.

Usually we have testing for llvm-readobj behaviour in test/tools/llvm-readobj, so that it can be kept independent of other testing, and so that changes in other areas don't impact test coverage for llvm-readobj. It also makes it easier to keep the tests focused on individual features. For example, what testing is there for EM_AMDGPU objects with an unrecognised ABI Version, or other aspects of that switch?

The test for unrecognized ABI version is missing, thanks for catching this, it will be included in the newer patchset I am currently working on.

We do have numerous tests that rely on llvm-readobj (and particularly that switch) to test e_flags in codegen, yaml, asm, and lld. Couple of examples:

llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-any.ll
llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-1.ll
llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-2.ll
llvm/test/CodeGen/AMDGPU/elf-header-flags-xnack.ll
llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-off.ll
llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-on.ll
llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-any.ll
llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-2.ll
llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-off.ll
llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll
llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-on.ll
llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-1.ll
llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
llvm/test/Object/AMDGPU/elf-header-flags-sramecc.yaml
llvm/test/Object/AMDGPU/elf-header-flags-xnack.yaml

LLD test also uses llvm-readobj: https://reviews.llvm.org/D95811

Similar situation with notes.

Is the suggestion to add similar tests [maybe selective?] tests under test/tools/llvm-readobj?

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

129

Added back null check as discussed offline. I will post a separate review to fix other places.

llvm/test/tools/llvm-readobj/ELF/note-amd.s

27

This check is here because we started processing *NT_AMD_PAL_METADATA* in *getAMDNote*, and if note's desc is empty (which is the case here), we are going to output an empty string (there is whitespace before returned empty string so we cannot use EMPTY).

Similar checks were put in https://reviews.llvm.org/D96010 . Also see lines 11 and 14 above. Do you have suggestions on how to improve this?

llvm/tools/llvm-readobj/ELFDumper.cpp

6115

Thanks, will be in newer diff.

[kzhuravl]

In D95638#2564830, @jhenderson wrote:

In D95638#2531247, @kzhuravl wrote:

In D95638#2530115, @jhenderson wrote:

I've only looked at the llvm-readobj stuff: there are a very large number of changes to that tool in this change, but no direct testing (i.e. tests under llvm\test\llvm-readobj) that has been changed. I'm guessing it's not all covered by existing direct testing of the tool?

It is not covered by the direct testing of the tool (no tests in llvm\test\llvm-readobj), but has a very good coverage in llvm/test/CodeGen/AMDGPU.

Usually we have testing for llvm-readobj behaviour in test/tools/llvm-readobj, so that it can be kept independent of other testing, and so that changes in other areas don't impact test coverage for llvm-readobj. It also makes it easier to keep the tests focused on individual features. For example, what testing is there for EM_AMDGPU objects with an unrecognised ABI Version, or other aspects of that switch?

Updated llvm/test/tools/llvm-readobj/ELF/amdgpu-elf-hea ders.test.

[kzhuravl]

Address review feedback.

[rampitec]

llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll

6

Can you add gfx90a and gfx90c?

[rampitec]

llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll

6

Actually only gfx90a.

[kzhuravl]

Address @rampitec 's comments.

[kzhuravl]

Rebase.

[kzhuravl]

ping.

[kzhuravl]

ping.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

4516

Why &&? I also have no idea what this type is, so I think the auto hurts

4517

I'm guessing this is an Optional, in which case *HasAbiVer

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

4822

The subtarget still has the register even if xnack isn't enabled

[kzhuravl]

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

4822

supported != enabled. isXnackSupported returns true for every ASIC that supports xnack, false otherwise. To check whether xnack is enabled or not, one can check the return value of getXnackSetting and see if it is "On":

https://github.com/llvm/llvm-project/blob/main/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h#L108

[kzhuravl]

Rebase and address review feedback.

[kzhuravl]

ping.

[kzhuravl]

ping.

[jhenderson]

llvm/tools/llvm-readobj/ELFDumper.cpp

5052

@kzhuravl - this is a good example of why I want llvm-readobj testing for llvm-readobj code. There's a bug in this code (which I unfortunately introduced with my previous suggestion) which should have been easily picked up if it was properly tested. It should be ++I not ++E. Please fix ASAP, as it is being flagged up by our downstream static analyzer.

[jhenderson]

Apologies for not coming back to review this before. I've taken a look through the llvm-readobj changes, and highlighted a number of code paths which I don't think have been tested at all (based on the fact that strings that should be printed don't appear in any of the test changes with this patch). Please create a new patch to address these and my previous comment. If necessary, use yaml2obj to generate note sections with the appropriate metadata.

llvm/tools/llvm-readobj/ELFDumper.cpp

4974–4976

This code appears to be untested.

4980–4981

This code is untested.

4992–4993

This code appears to be untested.

4997–5001

This code is untested.

5012–5013

This code appears to be untested.

5015–5018

This code appears to be untested.

5021–5027

This code is untested.

[jhenderson]

@kzhuravl, are my comments going to be addressed?

[kzhuravl]

In D95638#2704559, @jhenderson wrote:

@kzhuravl, are my comments going to be addressed?

Hi, sorry, I was out of office, and I just returned.

I did ping few weeks overall, submitted 1 week after this patch was accepted (thinking there may be additional feedback), and did not hear back from you.

I will address your comments and post a follow up patch today or tomorrow.

[jhenderson]

In D95638#2716560, @kzhuravl wrote:

In D95638#2704559, @jhenderson wrote:

@kzhuravl, are my comments going to be addressed?

Hi, sorry, I was out of office, and I just returned.

I did ping few weeks overall, submitted 1 week after this patch was accepted (thinking there may be additional feedback), and did not hear back from you.

I will address your comments and post a follow up patch today or tomorrow.

No problem, and sorry for abandoning the review originally - things got a bit hectic my end and I couldn't keep track of all the reviews.

[kzhuravl]

https://reviews.llvm.org/D101304

lld/ELF/Arch/AMDGPU.cpp

 //===- AMDGPU.cpp ---------------------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "InputFiles.h"
 #include "Symbols.h"
 #include "Target.h"
 #include "lld/Common/ErrorHandler.h"
 #include "llvm/Object/ELF.h"
 #include "llvm/Support/Endian.h"
 
 using namespace llvm;
 using namespace llvm::object;
 using namespace llvm::support::endian;
 using namespace llvm::ELF;
 using namespace lld;
 using namespace lld::elf;
 
 namespace {
 class AMDGPU final : public TargetInfo {
+private:
+  uint32_t calcEFlagsV3() const;
+  uint32_t calcEFlagsV4() const;
+
 public:
   AMDGPU();
   uint32_t calcEFlags() const override;
   void relocate(uint8_t *loc, const Relocation &rel,
                 uint64_t val) const override;
   RelExpr getRelExpr(RelType type, const Symbol &s,
                      const uint8_t *loc) const override;
   RelType getDynRel(RelType type) const override;
 };
 } // namespace
 
 AMDGPU::AMDGPU() {
   relativeRel = R_AMDGPU_RELATIVE64;
   gotRel = R_AMDGPU_ABS64;
   noneRel = R_AMDGPU_NONE;
   symbolicRel = R_AMDGPU_ABS64;
 }
 
+static uint8_t getAbiVersion(InputFile *file) {
+  return cast<ObjFile<ELF64LE>>(file)->getObj().getHeader().e_ident[EI_ABIVERSION];
+}
+
 static uint32_t getEFlags(InputFile *file) {
   return cast<ObjFile<ELF64LE>>(file)->getObj().getHeader().e_flags;
 }
 
-uint32_t AMDGPU::calcEFlags() const {
-  assert(!objectFiles.empty());
+static uint32_t getMach(InputFile *file) {
+  return getEFlags(file) & EF_AMDGPU_MACH;
+}
+
+static uint32_t getXnackV4(InputFile *file) {
+  return getEFlags(file) & EF_AMDGPU_FEATURE_XNACK_V4;
+}
+
+static uint32_t getSramEccV4(InputFile *file) {
+  return getEFlags(file) & EF_AMDGPU_FEATURE_SRAMECC_V4;
+}
+
+uint32_t AMDGPU::calcEFlagsV3() const {
   uint32_t ret = getEFlags(objectFiles[0]);
 
   // Verify that all input files have the same e_flags.
   for (InputFile *f : makeArrayRef(objectFiles).slice(1)) {
     if (ret == getEFlags(f))
       continue;
     error("incompatible e_flags: " + toString(f));
     return 0;
   }
   return ret;
 }
 
+uint32_t AMDGPU::calcEFlagsV4() const {
+  uint32_t retMach = getMach(objectFiles[0]);
+  uint32_t retXnack = getXnackV4(objectFiles[0]);
+  uint32_t retSramEcc = getSramEccV4(objectFiles[0]);
+
+  // Verify that all input files have compatible e_flags (same mach, all
+  // features in the same category are either ANY, ANY and ON, or ANY and OFF).
+  for (InputFile *f : makeArrayRef(objectFiles).slice(1)) {
+    if (retMach != getMach(f)) {
+      error("incompatible mach: " + toString(f));
+      return 0;
+    }
+
+    if ((retXnack == EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4) ||
+        (retXnack != EF_AMDGPU_FEATURE_XNACK_ANY_V4 &&
+            getXnackV4(f) != EF_AMDGPU_FEATURE_XNACK_ANY_V4)) {
+      if (retXnack != getXnackV4(f)) {
+        error("incompatible xnack: " + toString(f));
+        return 0;
+      }
+    } else {
+      if (retXnack == EF_AMDGPU_FEATURE_XNACK_ANY_V4) {
+        retXnack = getXnackV4(f);
+      }
+    }
+
+    if ((retSramEcc == EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4) ||
+        (retSramEcc != EF_AMDGPU_FEATURE_SRAMECC_ANY_V4 &&
+            getSramEccV4(f) != EF_AMDGPU_FEATURE_SRAMECC_ANY_V4)) {
+      if (retSramEcc != getSramEccV4(f)) {
+        error("incompatible sramecc: " + toString(f));
+        return 0;
+      }
+    } else {
+      if (retSramEcc == EF_AMDGPU_FEATURE_SRAMECC_ANY_V4) {
+        retSramEcc = getSramEccV4(f);
+      }
+    }
+  }
+
+  return retMach | retXnack | retSramEcc;
+}
+
+uint32_t AMDGPU::calcEFlags() const {
+  assert(!objectFiles.empty());
+  switch (getAbiVersion(objectFiles[0])) {
+  case ELFABIVERSION_AMDGPU_HSA_V2:
+  case ELFABIVERSION_AMDGPU_HSA_V3:
+    return calcEFlagsV3();
+  case ELFABIVERSION_AMDGPU_HSA_V4:
+    return calcEFlagsV4();
+  default:
+    llvm_unreachable("Unknown ABI Version");
+  }
+}
+
 void AMDGPU::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
   switch (rel.type) {
   case R_AMDGPU_ABS32:
   case R_AMDGPU_GOTPCREL:
   case R_AMDGPU_GOTPCREL32_LO:
   case R_AMDGPU_REL32:
   case R_AMDGPU_REL32_LO:
     write32le(loc, val);

lld/test/ELF/amdgpu-abi-version.s

 # REQUIRES: amdgpu
-# RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj %s -o %t.o
+# RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=3 -filetype=obj %s -o %t.o
 # RUN: ld.lld -shared %t.o -o %t.so
 # RUN: llvm-readobj --file-headers %t.so | FileCheck %s
 
 # CHECK: OS/ABI: AMDGPU_HSA (0x40)
 # CHECK: ABIVersion: 1
 
 .text
   s_nop 0x0
   s_endpgm

lld/test/ELF/lto/amdgcn-oses.ll

 ; RUN: ld.lld %t/amdpal.o -o %t/amdpal.so
 ; RUN: llvm-readobj --file-headers %t/amdpal.so | FileCheck %s --check-prefixes=GCN,NON-AMDHSA,AMDPAL
 
 ; RUN: llvm-as %t/mesa3d.ll -o %t/mesa3d.o
 ; RUN: ld.lld %t/mesa3d.o -o %t/mesa3d.so
 ; RUN: llvm-readobj --file-headers %t/mesa3d.so | FileCheck %s --check-prefixes=GCN,NON-AMDHSA,MESA3D
 
 ; AMDHSA: OS/ABI: AMDGPU_HSA (0x40)
-; AMDHSA: ABIVersion: 1
+; AMDHSA: ABIVersion: 2
 
 ; AMDPAL: OS/ABI: AMDGPU_PAL (0x41)
 ; MESA3D: OS/ABI: AMDGPU_MESA3D (0x42)
 ; NON-AMDHSA: ABIVersion: 0
 
 ;--- amdhsa.ll
 target triple = "amdgcn-amd-amdhsa"
 target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5"

llvm/include/llvm/BinaryFormat/ELF.h

 };
 
 // AMDGPU OS ABI Version identification.
 enum {
   // ELFABIVERSION_AMDGPU_HSA_V1 does not exist because OS ABI identification
   // was never defined for V1.
   ELFABIVERSION_AMDGPU_HSA_V2 = 0,
   ELFABIVERSION_AMDGPU_HSA_V3 = 1,
+  ELFABIVERSION_AMDGPU_HSA_V4 = 2
 };
 
 #define ELF_RELOC(name, value) name = value,
 
 // X86_64 relocations.
 enum {
 #include "ELFRelocs/x86_64.def"
 };
enum : unsigned {
   EF_AMDGPU_MACH_AMDGCN_GFX805        = 0x03c,
 
   // First/last AMDGCN-based processors.
   EF_AMDGPU_MACH_AMDGCN_FIRST = EF_AMDGPU_MACH_AMDGCN_GFX600,
   EF_AMDGPU_MACH_AMDGCN_LAST = EF_AMDGPU_MACH_AMDGCN_GFX805,
 
   // Indicates if the "xnack" target feature is enabled for all code contained
   // in the object.
-  EF_AMDGPU_XNACK = 0x100,
-  // Indicates if the "sram-ecc" target feature is enabled for all code
+  //
+  // Only valid for ELFOSABI_AMDGPU_HSA and ELFABIVERSION_AMDGPU_HSA_V2.
+  EF_AMDGPU_FEATURE_XNACK_V2 = 0x01,
+  // Indicates if the trap handler is enabled for all code contained
+  // in the object.
+  //
+  // Only valid for ELFOSABI_AMDGPU_HSA and ELFABIVERSION_AMDGPU_HSA_V2.
+  EF_AMDGPU_FEATURE_TRAP_HANDLER_V2 = 0x02,
+
+  // Indicates if the "xnack" target feature is enabled for all code contained
+  // in the object.
+  //
+  // Only valid for ELFOSABI_AMDGPU_HSA and ELFABIVERSION_AMDGPU_HSA_V3.
+  EF_AMDGPU_FEATURE_XNACK_V3 = 0x100,
+  // Indicates if the "sramecc" target feature is enabled for all code
   // contained in the object.
-  EF_AMDGPU_SRAM_ECC = 0x200,
+  //
+  // Only valid for ELFOSABI_AMDGPU_HSA and ELFABIVERSION_AMDGPU_HSA_V3.
+  EF_AMDGPU_FEATURE_SRAMECC_V3 = 0x200,
+
+  // XNACK selection mask for EF_AMDGPU_FEATURE_XNACK_* values.
+  //
+  // Only valid for ELFOSABI_AMDGPU_HSA and ELFABIVERSION_AMDGPU_HSA_V4.
+  EF_AMDGPU_FEATURE_XNACK_V4 = 0x300,
+  // XNACK is not supported.
+  EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4 = 0x000,
+  // XNACK is any/default/unspecified.
+  EF_AMDGPU_FEATURE_XNACK_ANY_V4 = 0x100,
+  // XNACK is off.
+  EF_AMDGPU_FEATURE_XNACK_OFF_V4 = 0x200,
+  // XNACK is on.
+  EF_AMDGPU_FEATURE_XNACK_ON_V4 = 0x300,
+
+  // SRAMECC selection mask for EF_AMDGPU_FEATURE_SRAMECC_* values.
+  //
+  // Only valid for ELFOSABI_AMDGPU_HSA and ELFABIVERSION_AMDGPU_HSA_V4.
+  EF_AMDGPU_FEATURE_SRAMECC_V4 = 0xc00,
+  // SRAMECC is not supported.
+  EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4 = 0x000,
+  // SRAMECC is any/default/unspecified.
+  EF_AMDGPU_FEATURE_SRAMECC_ANY_V4 = 0x400,
+  // SRAMECC is off.
+  EF_AMDGPU_FEATURE_SRAMECC_OFF_V4 = 0x800,
+  // SRAMECC is on.
+  EF_AMDGPU_FEATURE_SRAMECC_ON_V4 = 0xc00,
 };
 
 // ELF Relocation types for AMDGPU
 enum {
 #include "ELFRelocs/AMDGPU.def"
 };
 
 // ELF Relocation types for BPF
enum : unsigned {
   GNU_PROPERTY_X86_FEATURE_2_XSAVEC = 1 << 9,
 };
 
 // AMDGPU-specific section indices.
 enum {
   SHN_AMDGPU_LDS = 0xff00, // Variable in LDS; symbol encoded like SHN_COMMON
 };
 
-// AMD specific notes. (Code Object V2)
+// AMD vendor specific notes. (Code Object V2)
 enum {
-  // Note types with values between 0 and 9 (inclusive) are reserved.
-  NT_AMD_AMDGPU_HSA_METADATA = 10,
-  NT_AMD_AMDGPU_ISA = 11,
-  NT_AMD_AMDGPU_PAL_METADATA = 12
+  NT_AMD_HSA_CODE_OBJECT_VERSION = 1,
+  NT_AMD_HSA_HSAIL = 2,
+  NT_AMD_HSA_ISA_VERSION = 3,
+  // Note types with values between 4 and 9 (inclusive) are reserved.
+  NT_AMD_HSA_METADATA = 10,
+  NT_AMD_HSA_ISA_NAME = 11,
+  NT_AMD_PAL_METADATA = 12
 };
 
-// AMDGPU specific notes. (Code Object V3)
+// AMDGPU vendor specific notes. (Code Object V3)
 enum {
   // Note types with values between 0 and 31 (inclusive) are reserved.
   NT_AMDGPU_METADATA = 32
 };
 
 enum {
   GNU_ABI_TAG_LINUX = 0,
   GNU_ABI_TAG_HURD = 1,

llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h

public:
   virtual void flushPendingInstructions(MCStreamer &Out) {}
 
   virtual const MCExpr *createTargetUnaryExpr(const MCExpr *E,
                                               AsmToken::TokenKind OperatorToken,
                                               MCContext &Ctx) {
     return nullptr;
   }
 
+  // For any initialization at the beginning of parsing.
+  virtual void onBeginOfFile() {}
+
   // For any checks or cleanups at the end of parsing.
   virtual void onEndOfFile() {}
 };
 
 } // end namespace llvm
 
 #endif // LLVM_MC_MCPARSER_MCTARGETASMPARSER_H

llvm/include/llvm/MC/MCSubtargetInfo.h

class MCSubtargetInfo {
   const MCWriteLatencyEntry *WriteLatencyTable;
   const MCReadAdvanceEntry *ReadAdvanceTable;
   const MCSchedModel *CPUSchedModel;
 
   const InstrStage *Stages;            // Instruction itinerary stages
   const unsigned *OperandCycles;       // Itinerary operand cycles
   const unsigned *ForwardingPaths;
   FeatureBitset FeatureBits;           // Feature bits for current CPU + FS
+  std::string FeatureString;           // Feature string
 
 public:
   MCSubtargetInfo(const MCSubtargetInfo &) = default;
   MCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU,
                   StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
                   ArrayRef<SubtargetSubTypeKV> PD,
                   const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
                   const MCReadAdvanceEntry *RA, const InstrStage *IS,
                   const unsigned *OC, const unsigned *FP);
   MCSubtargetInfo() = delete;
   MCSubtargetInfo &operator=(const MCSubtargetInfo &) = delete;
   MCSubtargetInfo &operator=(MCSubtargetInfo &&) = delete;
   virtual ~MCSubtargetInfo() = default;
 
   const Triple &getTargetTriple() const { return TargetTriple; }
   StringRef getCPU() const { return CPU; }
   StringRef getTuneCPU() const { return TuneCPU; }
 
   const FeatureBitset& getFeatureBits() const { return FeatureBits; }
   void setFeatureBits(const FeatureBitset &FeatureBits_) {
     FeatureBits = FeatureBits_;
   }
 
+  StringRef getFeatureString() const { return FeatureString; }
+
   bool hasFeature(unsigned Feature) const {
     return FeatureBits[Feature];
   }
 
 protected:
   /// Initialize the scheduling model and feature bits.
   ///
   /// FIXME: Find a way to stick this in the constructor, since it should only

llvm/include/llvm/Support/AMDGPUMetadata.h

 namespace llvm {
 namespace AMDGPU {
 
 //===----------------------------------------------------------------------===//
 // HSA metadata.
 //===----------------------------------------------------------------------===//
 namespace HSAMD {
 
-/// HSA metadata major version.
-constexpr uint32_t VersionMajor = 1;
-/// HSA metadata minor version.
-constexpr uint32_t VersionMinor = 0;
+/// HSA metadata major version for code object V2.
+constexpr uint32_t VersionMajorV2 = 1;
+/// HSA metadata minor version for code object V2.
+constexpr uint32_t VersionMinorV2 = 0;
+
+/// HSA metadata major version for code object V3.
+constexpr uint32_t VersionMajorV3 = 1;
+/// HSA metadata minor version for code object V3.
+constexpr uint32_t VersionMinorV3 = 0;
+
+/// HSA metadata major version for code object V4.
+constexpr uint32_t VersionMajorV4 = 1;
+/// HSA metadata minor version for code object V4.
+constexpr uint32_t VersionMinorV4 = 1;
 
 /// HSA metadata beginning assembler directive.
 constexpr char AssemblerDirectiveBegin[] = ".amd_amdgpu_hsa_metadata";
 /// HSA metadata ending assembler directive.
 constexpr char AssemblerDirectiveEnd[] = ".end_amd_amdgpu_hsa_metadata";
 
 /// Access qualifiers.
 enum class AccessQualifier : uint8_t {

llvm/include/llvm/Support/AMDHSAKernelDescriptor.h

enum : int32_t {
   KERNEL_CODE_PROPERTY(RESERVED1, 11, 5),
 };
 #undef KERNEL_CODE_PROPERTY
 
 // Kernel descriptor. Must be kept backwards compatible.
 struct kernel_descriptor_t {
   uint32_t group_segment_fixed_size;
   uint32_t private_segment_fixed_size;
-  uint8_t reserved0[8];
+  uint32_t kernarg_size;
+  uint8_t reserved0[4];
   int64_t kernel_code_entry_byte_offset;
   uint8_t reserved1[20];
   uint32_t compute_pgm_rsrc3; // GFX10+
   uint32_t compute_pgm_rsrc1;
   uint32_t compute_pgm_rsrc2;
   uint16_t kernel_code_properties;
   uint8_t reserved2[6];
 };
 
 enum : uint32_t {
   GROUP_SEGMENT_FIXED_SIZE_OFFSET = 0,
   PRIVATE_SEGMENT_FIXED_SIZE_OFFSET = 4,
-  RESERVED0_OFFSET = 8,
+  KERNARG_SIZE_OFFSET = 8,
+  RESERVED0_OFFSET = 12,
   KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET = 16,
   RESERVED1_OFFSET = 24,
   COMPUTE_PGM_RSRC3_OFFSET = 44,
   COMPUTE_PGM_RSRC1_OFFSET = 48,
   COMPUTE_PGM_RSRC2_OFFSET = 52,
   KERNEL_CODE_PROPERTIES_OFFSET = 56,
   RESERVED2_OFFSET = 58,
 };
 
 static_assert(
     sizeof(kernel_descriptor_t) == 64,
     "invalid size for kernel_descriptor_t");
 static_assert(offsetof(kernel_descriptor_t, group_segment_fixed_size) ==
                   GROUP_SEGMENT_FIXED_SIZE_OFFSET,
               "invalid offset for group_segment_fixed_size");
 static_assert(offsetof(kernel_descriptor_t, private_segment_fixed_size) ==
                   PRIVATE_SEGMENT_FIXED_SIZE_OFFSET,
               "invalid offset for private_segment_fixed_size");
+static_assert(offsetof(kernel_descriptor_t, kernarg_size) ==
+                  KERNARG_SIZE_OFFSET,
+              "invalid offset for kernarg_size");
 static_assert(offsetof(kernel_descriptor_t, reserved0) == RESERVED0_OFFSET,
               "invalid offset for reserved0");
 static_assert(offsetof(kernel_descriptor_t, kernel_code_entry_byte_offset) ==
                   KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET,
               "invalid offset for kernel_code_entry_byte_offset");
 static_assert(offsetof(kernel_descriptor_t, reserved1) == RESERVED1_OFFSET,
               "invalid offset for reserved1");
 static_assert(offsetof(kernel_descriptor_t, compute_pgm_rsrc3) ==

llvm/lib/MC/MCParser/AsmParser.cpp

if (!Sec->getBeginSymbol()) {
       getStreamer().emitLabel(SectionStartSym);
       Sec->setBeginSymbol(SectionStartSym);
     }
     bool InsertResult = getContext().addGenDwarfSection(Sec);
     assert(InsertResult && ".text section should not have debug info yet");
     (void)InsertResult;
   }
 
+  getTargetParser().onBeginOfFile();
+
   // While we have input, parse each statement.
   while (Lexer.isNot(AsmToken::Eof)) {
     ParseStatementInfo Info(&AsmStrRewrites);
     bool Parsed = parseStatement(Info, nullptr);
 
     // If we have a Lexer Error we are on an Error Token. Load in Lexer Error
     // for printing ErrMsg via Lex() only if no (presumably better) parser error
     // exists.

llvm/lib/MC/MCParser/MasmParser.cpp

if (!Sec->getBeginSymbol()) {
       getStreamer().emitLabel(SectionStartSym);
       Sec->setBeginSymbol(SectionStartSym);
     }
     bool InsertResult = getContext().addGenDwarfSection(Sec);
     assert(InsertResult && ".text section should not have debug info yet");
     (void)InsertResult;
   }
 
+  getTargetParser().onBeginOfFile();
+
   // While we have input, parse each statement.
   while (Lexer.isNot(AsmToken::Eof) ||
          SrcMgr.getParentIncludeLoc(CurBuffer) != SMLoc()) {
     // Skip through the EOF at the end of an inclusion.
     if (Lexer.is(AsmToken::Eof))
       Lex();
 
     ParseStatementInfo Info(&AsmStrRewrites);

llvm/lib/MC/MCSubtargetInfo.cpp

static FeatureBitset getFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS,
   }
 
   return Bits;
 }
 
 void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef TuneCPU,
                                           StringRef FS) {
   FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures);
+  FeatureString = std::string(FS);
+
   if (!TuneCPU.empty())
     CPUSchedModel = &getSchedModelForCPU(TuneCPU);
   else
     CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
 }
 
 void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef TuneCPU,
                                          StringRef FS) {
   FeatureBits = getFeatures(CPU, TuneCPU, FS, ProcDesc, ProcFeatures);
+  FeatureString = std::string(FS);
 }
 
 MCSubtargetInfo::MCSubtargetInfo(const Triple &TT, StringRef C, StringRef TC,
                                  StringRef FS, ArrayRef<SubtargetFeatureKV> PF,
                                  ArrayRef<SubtargetSubTypeKV> PD,
                                  const MCWriteProcResEntry *WPR,
                                  const MCWriteLatencyEntry *WL,
                                  const MCReadAdvanceEntry *RA,

llvm/lib/ObjectYAML/ELFYAML.cpp

case ELF::EM_AMDGPU:
     BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX90C, EF_AMDGPU_MACH);
     BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1010, EF_AMDGPU_MACH);
     BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1011, EF_AMDGPU_MACH);
     BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1012, EF_AMDGPU_MACH);
     BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1030, EF_AMDGPU_MACH);
     BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1031, EF_AMDGPU_MACH);
     BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1032, EF_AMDGPU_MACH);
     BCaseMask(EF_AMDGPU_MACH_AMDGCN_GFX1033, EF_AMDGPU_MACH);
-    BCase(EF_AMDGPU_XNACK);
-    BCase(EF_AMDGPU_SRAM_ECC);
+    switch (Object->Header.ABIVersion) {
+    default:
+      // ELFOSABI_AMDGPU_PAL, ELFOSABI_AMDGPU_MESA3D support *_V3 flags.
+      LLVM_FALLTHROUGH;
+    case ELF::ELFABIVERSION_AMDGPU_HSA_V3:
+      BCase(EF_AMDGPU_FEATURE_XNACK_V3);
+      BCase(EF_AMDGPU_FEATURE_SRAMECC_V3);
+      break;
+    case ELF::ELFABIVERSION_AMDGPU_HSA_V4:
+      BCaseMask(EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4,
+                EF_AMDGPU_FEATURE_XNACK_V4);
+      BCaseMask(EF_AMDGPU_FEATURE_XNACK_ANY_V4,
+                EF_AMDGPU_FEATURE_XNACK_V4);
+      BCaseMask(EF_AMDGPU_FEATURE_XNACK_OFF_V4,
+                EF_AMDGPU_FEATURE_XNACK_V4);
+      BCaseMask(EF_AMDGPU_FEATURE_XNACK_ON_V4,
+                EF_AMDGPU_FEATURE_XNACK_V4);
+      BCaseMask(EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4,
+                EF_AMDGPU_FEATURE_SRAMECC_V4);
+      BCaseMask(EF_AMDGPU_FEATURE_SRAMECC_ANY_V4,
+                EF_AMDGPU_FEATURE_SRAMECC_V4);
+      BCaseMask(EF_AMDGPU_FEATURE_SRAMECC_OFF_V4,
+                EF_AMDGPU_FEATURE_SRAMECC_V4);
+      BCaseMask(EF_AMDGPU_FEATURE_SRAMECC_ON_V4,
+                EF_AMDGPU_FEATURE_SRAMECC_V4);
+      break;
+    }
     break;
   default:
     break;
   }
 #undef BCase
 #undef BCaseMask
 }
 

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.h

struct SIFunctionResourceInfo {
     bool UsesFlatScratch = false;
     bool HasDynamicallySizedStack = false;
     bool HasRecursion = false;
 
     int32_t getTotalNumSGPRs(const GCNSubtarget &ST) const;
     int32_t getTotalNumVGPRs(const GCNSubtarget &ST) const;
   };
 
+  void initializeTargetID(const Module &M);
+
   SIProgramInfo CurrentProgramInfo;
   DenseMap<const Function *, SIFunctionResourceInfo> CallGraphResourceInfo;
 
   std::unique_ptr<AMDGPU::HSAMD::MetadataStreamer> HSAMetadataStream;
 
   MCCodeEmitter *DumpCodeInstEmitter = nullptr;
 
   uint64_t getFunctionCodeSize(const MachineFunction &MF) const;

llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

extern "C" void LLVM_EXTERNAL_VISIBILITY LLVMInitializeAMDGPUAsmPrinter() {
   TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
                                      llvm::createR600AsmPrinterPass);
   TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
                                      createAMDGPUAsmPrinterPass);
 }
 
 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
                                    std::unique_ptr<MCStreamer> Streamer)
     : AsmPrinter(TM, std::move(Streamer)) {
   if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
     if (isHsaAbiVersion2(getGlobalSTI())) {
       HSAMetadataStream.reset(new HSAMD::MetadataStreamerV2());
-    } else {
+    } else if (isHsaAbiVersion3(getGlobalSTI())) {
       HSAMetadataStream.reset(new HSAMD::MetadataStreamerV3());
+    } else {
+      HSAMetadataStream.reset(new HSAMD::MetadataStreamerV4());
     }
   }
 }
 
 StringRef AMDGPUAsmPrinter::getPassName() const {
   return "AMDGPU Assembly Printer";
 }
 
 const MCSubtargetInfo *AMDGPUAsmPrinter::getGlobalSTI() const {
   return TM.getMCSubtargetInfo();
 }
 
 AMDGPUTargetStreamer* AMDGPUAsmPrinter::getTargetStreamer() const {
   if (!OutStreamer)
     return nullptr;
   return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
 }
 
 void AMDGPUAsmPrinter::emitStartOfAsmFile(Module &M) {
-  if (isHsaAbiVersion3(getGlobalSTI())) {
-    std::string ExpectedTarget;
-    raw_string_ostream ExpectedTargetOS(ExpectedTarget);
-    IsaInfo::streamIsaVersion(getGlobalSTI(), ExpectedTargetOS);
-
-    getTargetStreamer()->EmitDirectiveAMDGCNTarget(ExpectedTarget);
-  }
+  // TODO: Which one is called first, emitStartOfAsmFile or
+  // emitFunctionBodyStart?
+  if (getTargetStreamer() && !getTargetStreamer()->getTargetID())
+    initializeTargetID(M);
 
   if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
       TM.getTargetTriple().getOS() != Triple::AMDPAL)
     return;
 
+  if (isHsaAbiVersion3Or4(getGlobalSTI()))
+    getTargetStreamer()->EmitDirectiveAMDGCNTarget();
+
   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
-    HSAMetadataStream->begin(M);
+    HSAMetadataStream->begin(M, *getTargetStreamer()->getTargetID());
 
   if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
     getTargetStreamer()->getPALMetadata()->readFromIR(M);
 
-  if (isHsaAbiVersion3(getGlobalSTI()))
+  if (isHsaAbiVersion3Or4(getGlobalSTI()))
     return;
 
-  // HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2.
+  // HSA emits NT_AMD_HSA_CODE_OBJECT_VERSION for code objects v2.
   if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
     getTargetStreamer()->EmitDirectiveHSACodeObjectVersion(2, 1);
 
-  // HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2.
+  // HSA and PAL emit NT_AMD_HSA_ISA_VERSION for code objects v2.
   IsaVersion Version = getIsaVersion(getGlobalSTI()->getCPU());
-  getTargetStreamer()->EmitDirectiveHSACodeObjectISA(
+  getTargetStreamer()->EmitDirectiveHSACodeObjectISAV2(
       Version.Major, Version.Minor, Version.Stepping, "AMD", "AMDGPU");
 }
 
 void AMDGPUAsmPrinter::emitEndOfAsmFile(Module &M) {
   // Following code requires TargetStreamer to be present.
   if (!getTargetStreamer())
     return;
 
   if (TM.getTargetTriple().getOS() != Triple::AMDHSA ||
-      isHsaAbiVersion2(getGlobalSTI())) {
-    // Emit ISA Version (NT_AMD_AMDGPU_ISA).
-    std::string ISAVersionString;
-    raw_string_ostream ISAVersionStream(ISAVersionString);
-    IsaInfo::streamIsaVersion(getGlobalSTI(), ISAVersionStream);
-    getTargetStreamer()->EmitISAVersion(ISAVersionStream.str());
-  }
+      isHsaAbiVersion2(getGlobalSTI()))
+    getTargetStreamer()->EmitISAVersion();
 
   // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
+  // Emit HSA Metadata (NT_AMD_HSA_METADATA).
   if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
     HSAMetadataStream->end();
     bool Success = HSAMetadataStream->emitTo(*getTargetStreamer());
     (void)Success;
     assert(Success && "Malformed HSA Metadata");
   }
 }
 
 bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
   const MachineBasicBlock *MBB) const {
   if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
     return false;
 
   if (MBB->empty())
     return true;
 
   // If this is a block implementing a long branch, an expression relative to
   // the start of the block is needed.  to the start of the block.
   // XXX - Is there a smarter way to check this?
   return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
 }
 
 void AMDGPUAsmPrinter::emitFunctionBodyStart() {
   const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
+  const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
+  const Function &F = MF->getFunction();
+
+  // TODO: Which one is called first, emitStartOfAsmFile or
+  // emitFunctionBodyStart?
+  if (getTargetStreamer() && !getTargetStreamer()->getTargetID())
+    initializeTargetID(*F.getParent());
+
+  const auto &FunctionTargetID = STM.getTargetID();
+  // Make sure function's xnack settings are compatible with module's
+  // xnack settings.
+  if (FunctionTargetID.isXnackSupported() &&
+      FunctionTargetID.getXnackSetting() != IsaInfo::TargetIDSetting::Any &&
+      FunctionTargetID.getXnackSetting() != getTargetStreamer()->getTargetID()->getXnackSetting()) {
+    OutContext.reportError({}, "xnack setting of '" + Twine(MF->getName()) +
+                           "' function does not match module xnack setting");
+    return;
+  }
+  // Make sure function's sramecc settings are compatible with module's
+  // sramecc settings.
+  if (FunctionTargetID.isSramEccSupported() &&
+      FunctionTargetID.getSramEccSetting() != IsaInfo::TargetIDSetting::Any &&
+      FunctionTargetID.getSramEccSetting() != getTargetStreamer()->getTargetID()->getSramEccSetting()) {
+    OutContext.reportError({}, "sramecc setting of '" + Twine(MF->getName()) +
+                           "' function does not match module sramecc setting");
+    return;
+  }
+
   if (!MFI.isEntryFunction())
     return;
 
-  const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
-  const Function &F = MF->getFunction();
   if ((STM.isMesaKernel(F) || isHsaAbiVersion2(getGlobalSTI())) &&
       (F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
        F.getCallingConv() == CallingConv::SPIR_KERNEL)) {
     amd_kernel_code_t KernelCode;
     getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
     getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
   }
 
void AMDGPUAsmPrinter::emitFunctionBodyEnd() {
   Streamer.SwitchSection(&ReadOnlySection);
 
   // CP microcode requires the kernel descriptor to be allocated on 64 byte
   // alignment.
   Streamer.emitValueToAlignment(64, 0, 1, 0);
   if (ReadOnlySection.getAlignment() < 64)
     ReadOnlySection.setAlignment(Align(64));
 
-  const MCSubtargetInfo &STI = MF->getSubtarget();
+  const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
 
   SmallString<128> KernelName;
   getNameWithPrefix(KernelName, &MF->getFunction());
   getTargetStreamer()->EmitAmdhsaKernelDescriptor(
-      STI, KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo),
+      STM, KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo),
       CurrentProgramInfo.NumVGPRsForWavesPerEU,
       CurrentProgramInfo.NumSGPRsForWavesPerEU -
-          IsaInfo::getNumExtraSGPRs(&STI,
+          IsaInfo::getNumExtraSGPRs(&STM,
                                     CurrentProgramInfo.VCCUsed,
                                     CurrentProgramInfo.FlatUsed),
-      CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed,
-      hasXNACK(STI));
+      CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed);
 
   Streamer.PopSection();
 }
 
 void AMDGPUAsmPrinter::emitFunctionEntryLabel() {
   if (TM.getTargetTriple().getOS() == Triple::AMDHSA &&
-      isHsaAbiVersion3(getGlobalSTI())) {
+      isHsaAbiVersion3Or4(getGlobalSTI())) {
     AsmPrinter::emitFunctionEntryLabel();
     return;
   }
 
   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
   const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
   if (MFI->isEntryFunction() && STM.isAmdHsaOrMesa(MF->getFunction())) {
     SmallString<128> SymbolName;
uint16_t AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties(
   }
 
   return KernelCodeProperties;
 }
 
 amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(
     const MachineFunction &MF,
     const SIProgramInfo &PI) const {
+  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
+  const Function &F = MF.getFunction();
+
   amdhsa::kernel_descriptor_t KernelDescriptor;
   memset(&KernelDescriptor, 0x0, sizeof(KernelDescriptor));
 
   assert(isUInt<32>(PI.ScratchSize));
   assert(isUInt<32>(PI.getComputePGMRSrc1()));
   assert(isUInt<32>(PI.ComputePGMRSrc2));
 
   KernelDescriptor.group_segment_fixed_size = PI.LDSSize;
   KernelDescriptor.private_segment_fixed_size = PI.ScratchSize;
+
+  Align MaxKernArgAlign;
+  KernelDescriptor.kernarg_size = STM.getKernArgSegmentSize(F, MaxKernArgAlign);
+
   KernelDescriptor.compute_pgm_rsrc1 = PI.getComputePGMRSrc1();
   KernelDescriptor.compute_pgm_rsrc2 = PI.ComputePGMRSrc2;
   KernelDescriptor.kernel_code_properties = getAmdhsaKernelCodeProperties(MF);
 
   return KernelDescriptor;
 }
 
 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
for (size_t i = 0; i < DisasmLines.size(); ++i) {
       OutStreamer->emitBytes(StringRef(DisasmLines[i]));
       OutStreamer->emitBytes(StringRef(Comment));
     }
   }
 
   return false;
 }
 
+// TODO: Fold this into emitFunctionBodyStart.
+void AMDGPUAsmPrinter::initializeTargetID(const Module &M) {
+  // In the beginning all features are either 'Any' or 'NotSupported',
+  // depending on global target features. This will cover empty modules.
+  getTargetStreamer()->initializeTargetID(
+      *getGlobalSTI(), getGlobalSTI()->getFeatureString());
+
+  // If module is empty, we are done.
+  if (M.empty())
+    return;
+
+  // If module is not empty, need to find first 'Off' or 'On' feature
+  // setting per feature from functions in module.
+  for (auto &F : M) {
+    auto &TSTargetID = getTargetStreamer()->getTargetID();
+    if ((!TSTargetID->isXnackSupported() || TSTargetID->isXnackOnOrOff()) &&
+        (!TSTargetID->isSramEccSupported() || TSTargetID->isSramEccOnOrOff()))
+      break;
+
+    const GCNSubtarget &STM = TM.getSubtarget<GCNSubtarget>(F);
+    const IsaInfo::AMDGPUTargetID &STMTargetID = STM.getTargetID();
+    if (TSTargetID->isXnackSupported())
+      if (TSTargetID->getXnackSetting() == IsaInfo::TargetIDSetting::Any)
+        TSTargetID->setXnackSetting(STMTargetID.getXnackSetting());
+    if (TSTargetID->isSramEccSupported())
+      if (TSTargetID->getSramEccSetting() == IsaInfo::TargetIDSetting::Any)
+        TSTargetID->setSramEccSetting(STMTargetID.getSramEccSetting());
+  }
+}
+
 uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
   const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
   const SIInstrInfo *TII = STM.getInstrInfo();
 
   uint64_t CodeSize = 0;
 
   for (const MachineBasicBlock &MBB : MF) {
     for (const MachineInstr &MI : MBB) {
if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
       return true;
   }
 
   return false;
 }
 
 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumSGPRs(
   const GCNSubtarget &ST) const {
-  return NumExplicitSGPR + IsaInfo::getNumExtraSGPRs(&ST,
-                                                     UsesVCC, UsesFlatScratch);
+  return NumExplicitSGPR + IsaInfo::getNumExtraSGPRs(
+      &ST, UsesVCC, UsesFlatScratch, ST.getTargetID().isXnackOnOrAny());
 }
 
 int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumVGPRs(
   const GCNSubtarget &ST) const {
   return std::max(NumVGPR, NumAGPR);
 }
 
 static const Function *getCalleeFunction(const MachineOperand &Op) {

llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h

 /// AMDGPU HSA Metadata Streamer.
 ///
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUHSAMETADATASTREAMER_H
 #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUHSAMETADATASTREAMER_H
 
+#include "Utils/AMDGPUBaseInfo.h"
 #include "llvm/BinaryFormat/MsgPackDocument.h"
 #include "llvm/Support/AMDGPUMetadata.h"
 #include "llvm/Support/Alignment.h"
 
 namespace llvm {
 
 class AMDGPUTargetStreamer;
 class Argument;

 namespace HSAMD {
 
 class MetadataStreamer {
 public:
   virtual ~MetadataStreamer(){};
 
   virtual bool emitTo(AMDGPUTargetStreamer &TargetStreamer) = 0;
 
-  virtual void begin(const Module &Mod) = 0;
+  virtual void begin(const Module &Mod,
+                     const IsaInfo::AMDGPUTargetID &TargetID) = 0;
 
   virtual void end() = 0;
 
   virtual void emitKernel(const MachineFunction &MF,
                           const SIProgramInfo &ProgramInfo) = 0;
 };
 
-class MetadataStreamerV3 final : public MetadataStreamer {
-private:
+// TODO: Rename MetadataStreamerV3 -> MetadataStreamerMsgPackV3.
+class MetadataStreamerV3 : public MetadataStreamer {
+protected:
   std::unique_ptr<msgpack::Document> HSAMetadataDoc =
       std::make_unique<msgpack::Document>();
 
   void dump(StringRef HSAMetadataString) const;
 
   void verify(StringRef HSAMetadataString) const;
 
   Optional<StringRef> getAccessQualifier(StringRef AccQual) const;
protected:
   }
 
 public:
   MetadataStreamerV3() = default;
   ~MetadataStreamerV3() = default;
 
   bool emitTo(AMDGPUTargetStreamer &TargetStreamer) override;
 
-  void begin(const Module &Mod) override;
+  void begin(const Module &Mod,
+             const IsaInfo::AMDGPUTargetID &TargetID) override;
 
   void end() override;
 
   void emitKernel(const MachineFunction &MF,
                   const SIProgramInfo &ProgramInfo) override;
 };
 
+// TODO: Rename MetadataStreamerV4 -> MetadataStreamerMsgPackV4.
+class MetadataStreamerV4 final : public MetadataStreamerV3 {
+  void emitVersion();
+
+  void emitTargetID(const IsaInfo::AMDGPUTargetID &TargetID);
+
+public:
+  MetadataStreamerV4() = default;
+  ~MetadataStreamerV4() = default;
+
+  void begin(const Module &Mod,
+             const IsaInfo::AMDGPUTargetID &TargetID) override;
+};
+
+// TODO: Rename MetadataStreamerV2 -> MetadataStreamerYamlV2.
 class MetadataStreamerV2 final : public MetadataStreamer {
 private:
   Metadata HSAMetadata;
 
   void dump(StringRef HSAMetadataString) const;
 
   void verify(StringRef HSAMetadataString) const;
 
private:
   }
 
 public:
   MetadataStreamerV2() = default;
   ~MetadataStreamerV2() = default;
 
   bool emitTo(AMDGPUTargetStreamer &TargetStreamer) override;
 
-  void begin(const Module &Mod) override;
+  void begin(const Module &Mod,
+             const IsaInfo::AMDGPUTargetID &TargetID) override;
 
   void end() override;
 
   void emitKernel(const MachineFunction &MF,
                   const SIProgramInfo &ProgramInfo) override;
 };
 
 } // end namespace HSAMD
 } // end namespace AMDGPU
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUHSAMETADATASTREAMER_H

llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp

 MetadataStreamerV2::getHSADebugProps(const MachineFunction &MF,
                                      const SIProgramInfo &ProgramInfo) const {
   return HSAMD::Kernel::DebugProps::Metadata();
 }
 
 void MetadataStreamerV2::emitVersion() {
   auto &Version = HSAMetadata.mVersion;
 
-  Version.push_back(VersionMajor);
-  Version.push_back(VersionMinor);
+  Version.push_back(VersionMajorV2);
+  Version.push_back(VersionMinorV2);
 }
 
 void MetadataStreamerV2::emitPrintf(const Module &Mod) {
   auto &Printf = HSAMetadata.mPrintf;
 
   auto Node = Mod.getNamedMetadata("llvm.printf.fmts");
   if (!Node)
     return;
void MetadataStreamerV2::emitHiddenKernelArgs(const Function &Func) {
   if (HiddenArgNumBytes >= 56)
     emitKernelArg(DL, Int8PtrTy, Align(8), ValueKind::HiddenMultiGridSyncArg);
 }
 
 bool MetadataStreamerV2::emitTo(AMDGPUTargetStreamer &TargetStreamer) {
   return TargetStreamer.EmitHSAMetadata(getHSAMetadata());
 }
 
-void MetadataStreamerV2::begin(const Module &Mod) {
+void MetadataStreamerV2::begin(const Module &Mod,
+                               const IsaInfo::AMDGPUTargetID &TargetID) {
   emitVersion();
   emitPrintf(Mod);
 }
 
 void MetadataStreamerV2::end() {
   std::string HSAMetadataString;
   if (toString(HSAMetadata, HSAMetadataString))
     return;
MetadataStreamerV3::getWorkGroupDimensions(MDNode *Node) const {
   for (auto &Op : Node->operands())
     Dims.push_back(Dims.getDocument()->getNode(
         uint64_t(mdconst::extract<ConstantInt>(Op)->getZExtValue())));
   return Dims;
 }
 
 void MetadataStreamerV3::emitVersion() {
   auto Version = HSAMetadataDoc->getArrayNode();
-  Version.push_back(Version.getDocument()->getNode(VersionMajor));
-  Version.push_back(Version.getDocument()->getNode(VersionMinor));
+  Version.push_back(Version.getDocument()->getNode(VersionMajorV3));
+  Version.push_back(Version.getDocument()->getNode(VersionMinorV3));
   getRootMetadata("amdhsa.version") = Version;
 }
 
 void MetadataStreamerV3::emitPrintf(const Module &Mod) {
   auto Node = Mod.getNamedMetadata("llvm.printf.fmts");
   if (!Node)
     return;
 
MetadataStreamerV3::getHSAKernelProps(const MachineFunction &MF,
 
   return Kern;
 }
 
 bool MetadataStreamerV3::emitTo(AMDGPUTargetStreamer &TargetStreamer) {
   return TargetStreamer.EmitHSAMetadata(*HSAMetadataDoc, true);
 }
 
-void MetadataStreamerV3::begin(const Module &Mod) {
+void MetadataStreamerV3::begin(const Module &Mod,
+                               const IsaInfo::AMDGPUTargetID &TargetID) {
   emitVersion();
   emitPrintf(Mod);
   getRootMetadata("amdhsa.kernels") = HSAMetadataDoc->getArrayNode();
 }
 
 void MetadataStreamerV3::end() {
   std::string HSAMetadataString;
   raw_string_ostream StrOS(HSAMetadataString);
auto Kernels =
     emitKernelLanguage(Func, Kern);
     emitKernelAttrs(Func, Kern);
     emitKernelArgs(Func, Kern);
   }
 
   Kernels.push_back(Kern);
 }
 
+//===----------------------------------------------------------------------===//
+// HSAMetadataStreamerV4
+//===----------------------------------------------------------------------===//
+
+void MetadataStreamerV4::emitVersion() {
+  auto Version = HSAMetadataDoc->getArrayNode();
+  Version.push_back(Version.getDocument()->getNode(VersionMajorV4));
+  Version.push_back(Version.getDocument()->getNode(VersionMinorV4));
+  getRootMetadata("amdhsa.version") = Version;
+}
+
+void MetadataStreamerV4::emitTargetID(const IsaInfo::AMDGPUTargetID &TargetID) {
+  getRootMetadata("amdhsa.target") =
+      HSAMetadataDoc->getNode(TargetID.toString(), /*Copy=*/true);
+}
+
+void MetadataStreamerV4::begin(const Module &Mod,
+                               const IsaInfo::AMDGPUTargetID &TargetID) {
+  emitVersion();
+  emitTargetID(TargetID);
+  emitPrintf(Mod);
+  getRootMetadata("amdhsa.kernels") = HSAMetadataDoc->getArrayNode();
+}
+
 } // end namespace HSAMD
 } // end namespace AMDGPU
 } // end namespace llvm

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h

public:
 
   bool legalizeSBufferLoad(LegalizerHelper &Helper, MachineInstr &MI) const;
 
   bool legalizeAtomicIncDec(MachineInstr &MI,  MachineIRBuilder &B,
                             bool IsInc) const;
 
   bool legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
                              MachineIRBuilder &B) const;
+  bool legalizeTrapEndpgm(MachineInstr &MI, MachineRegisterInfo &MRI,
+                          MachineIRBuilder &B) const;
+  bool legalizeTrapHsaQueuePtr(MachineInstr &MI, MachineRegisterInfo &MRI,
+                               MachineIRBuilder &B) const;
+  bool legalizeTrapHsa(MachineInstr &MI, MachineRegisterInfo &MRI,
+                       MachineIRBuilder &B) const;
   bool legalizeDebugTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
                                   MachineIRBuilder &B) const;
 
   bool legalizeIntrinsic(LegalizerHelper &Helper,
                          MachineInstr &MI) const override;
 };
 } // End llvm namespace.
 #endif

llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

 
 #include "AMDGPULegalizerInfo.h"
 
 #include "AMDGPU.h"
 #include "AMDGPUGlobalISelUtils.h"
 #include "AMDGPUInstrInfo.h"
 #include "AMDGPUTargetMachine.h"
 #include "SIMachineFunctionInfo.h"
+#include "Utils/AMDGPUBaseInfo.h"
 #include "llvm/ADT/ScopeExit.h"
+#include "llvm/BinaryFormat/ELF.h"
 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/IR/IntrinsicsAMDGPU.h"
 
 #define DEBUG_TYPE "amdgpu-legalinfo"
 
bool AMDGPULegalizerInfo::legalizeSBufferLoad(
   Observer.changedInstr(MI);
   return true;
 }
 
 // TODO: Move to selection
 bool AMDGPULegalizerInfo::legalizeTrapIntrinsic(MachineInstr &MI,
                                                 MachineRegisterInfo &MRI,
                                                 MachineIRBuilder &B) const {
-  // Is non-HSA path or trap-handler disabled? then, insert s_endpgm instruction
-  if (ST.getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa ||
-      !ST.isTrapHandlerEnabled()) {
-    B.buildInstr(AMDGPU::S_ENDPGM).addImm(0);
-  } else {
-    // Pass queue pointer to trap handler as input, and insert trap instruction
-    // Reference: https://llvm.org/docs/AMDGPUUsage.html#trap-handler-abi
-    MachineRegisterInfo &MRI = *B.getMRI();
-
-    Register LiveIn =
-      MRI.createGenericVirtualRegister(LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
-    if (!loadInputValue(LiveIn, B, AMDGPUFunctionArgInfo::QUEUE_PTR))
-      return false;
+  if (!ST.isTrapHandlerEnabled() ||
+      ST.getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA)
+    return legalizeTrapEndpgm(MI, MRI, B);
+
+  if (const auto &&HsaAbiVer = AMDGPU::getHsaAbiVersion(&ST)) {
+    switch (HsaAbiVer.getValue()) {
+    case ELF::ELFABIVERSION_AMDGPU_HSA_V2:
+    case ELF::ELFABIVERSION_AMDGPU_HSA_V3:
+      return legalizeTrapHsaQueuePtr(MI, MRI, B);
+    case ELF::ELFABIVERSION_AMDGPU_HSA_V4:
+      return ST.supportsGetDoorbellID() ?
+          legalizeTrapHsa(MI, MRI, B) :
+          legalizeTrapHsaQueuePtr(MI, MRI, B);
+    }
+  }
+
+  llvm_unreachable("Unknown trap handler");
+}
+
+bool AMDGPULegalizerInfo::legalizeTrapEndpgm(
+    MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const {
+  MI.eraseFromParent();
+  return true;
+}
+
+bool AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr(
+    MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const {
 
-    Register SGPR01(AMDGPU::SGPR0_SGPR1);
-    B.buildCopy(SGPR01, LiveIn);
-    B.buildInstr(AMDGPU::S_TRAP)
-        .addImm(GCNSubtarget::TrapIDLLVMTrap)
-        .addReg(SGPR01, RegState::Implicit);
-  }
+      .addImm(static_cast<unsigned>(GCNSubtarget::TrapID::LLVMAMDHSATrap))
+
+  MI.eraseFromParent();
+  return true;
 
+bool AMDGPULegalizerInfo::legalizeTrapHsa(
+    MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const {
+  B.buildInstr(AMDGPU::S_TRAP)
+      .addImm(static_cast<unsigned>(GCNSubtarget::TrapID::LLVMAMDHSATrap));
   MI.eraseFromParent();
   return true;
 }
 
 bool AMDGPULegalizerInfo::legalizeDebugTrapIntrinsic(
     MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const {
   // Is non-HSA path or trap-handler disabled? then, report a warning
   // accordingly
-  if (ST.getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa ||
-      !ST.isTrapHandlerEnabled()) {
+  if (!ST.isTrapHandlerEnabled() ||
+      ST.getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA) {
     DiagnosticInfoUnsupported NoTrap(B.getMF().getFunction(),
                                      "debugtrap handler not supported",
                                      MI.getDebugLoc(), DS_Warning);
     LLVMContext &Ctx = B.getMF().getFunction().getContext();
     Ctx.diagnose(NoTrap);
   } else {
     // Insert debug-trap instruction
-    B.buildInstr(AMDGPU::S_TRAP).addImm(GCNSubtarget::TrapIDLLVMDebugTrap);
+    B.buildInstr(AMDGPU::S_TRAP)
+        .addImm(static_cast<unsigned>(GCNSubtarget::TrapID::LLVMAMDHSADebugTrap));
   }
 
   MI.eraseFromParent();
   return true;
 }
 
 bool AMDGPULegalizerInfo::legalizeBVHIntrinsic(MachineInstr &MI,
                                                MachineIRBuilder &B) const {

llvm/lib/Target/AMDGPU/AMDGPUPTNote.h

 
 namespace ElfNote {
 
 const char SectionName[] = ".note";
 
 const char NoteNameV2[] = "AMD";
 const char NoteNameV3[] = "AMDGPU";
 
-// TODO: Remove this file once we drop code object v2.
-enum NoteType{
-    NT_AMDGPU_HSA_RESERVED_0 = 0,
-    NT_AMDGPU_HSA_CODE_OBJECT_VERSION = 1,
-    NT_AMDGPU_HSA_HSAIL = 2,
-    NT_AMDGPU_HSA_ISA = 3,
-    NT_AMDGPU_HSA_PRODUCER = 4,
-    NT_AMDGPU_HSA_PRODUCER_OPTIONS = 5,
-    NT_AMDGPU_HSA_EXTENSION = 6,
-    NT_AMDGPU_HSA_RESERVED_7 = 7,
-    NT_AMDGPU_HSA_RESERVED_8 = 8,
-    NT_AMDGPU_HSA_RESERVED_9 = 9,
-    NT_AMDGPU_HSA_HLDEBUG_DEBUG = 101,
-    NT_AMDGPU_HSA_HLDEBUG_TARGET = 102
-};
-
 } // End namespace ElfNote
 } // End namespace AMDGPU
 } // End namespace llvm
 #endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUNOTETYPE_H

llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

bool calculateGPRBlocks(const FeatureBitset &Features, bool VCCUsed,
                           unsigned &SGPRBlocks);
   bool ParseDirectiveAMDGCNTarget();
   bool ParseDirectiveAMDHSAKernel();
   bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor);
   bool ParseDirectiveHSACodeObjectVersion();
   bool ParseDirectiveHSACodeObjectISA();
   bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header);
   bool ParseDirectiveAMDKernelCodeT();
-  bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo) const;
+  // TODO: Possibly make subtargetHasRegister const.
+  bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo);
   bool ParseDirectiveAMDGPUHsaKernel();
 
   bool ParseDirectiveISAVersion();
   bool ParseDirectiveHSAMetadata();
   bool ParseDirectivePALMetadataBegin();
   bool ParseDirectivePALMetadata();
   bool ParseDirectiveAMDGPULDS();
 
AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,
 
     {
       // TODO: make those pre-defined variables read-only.
       // Currently there is none suitable machinery in the core llvm-mc for this.
       // MCSymbol::isRedefinable is intended for another purpose, and
       // AsmParser::parseDirectiveSet() cannot be specialized for specific target.
       AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());
       MCContext &Ctx = getContext();
-      if (ISA.Major >= 6 && isHsaAbiVersion3(&getSTI())) {
+      if (ISA.Major >= 6 && isHsaAbiVersion3Or4(&getSTI())) {
         MCSymbol *Sym =
             Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_number"));
         Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));
         Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_minor"));
         Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));
         Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_stepping"));
         Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));
       } else {
         MCSymbol *Sym =
             Ctx.getOrCreateSymbol(Twine(".option.machine_version_major"));
         Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));
         Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_minor"));
         Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));
         Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_stepping"));
         Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));
       }
-      if (ISA.Major >= 6 && isHsaAbiVersion3(&getSTI())) {
+      if (ISA.Major >= 6 && isHsaAbiVersion3Or4(&getSTI())) {
         initializeGprCountSymbol(IS_VGPR);
         initializeGprCountSymbol(IS_SGPR);
       } else
         KernelScope.initialize(getContext());
     }
   }
 
-  bool hasXNACK() const {
-    return AMDGPU::hasXNACK(getSTI());
-  }
-
   bool hasMIMG_R128() const {
     return AMDGPU::hasMIMG_R128(getSTI());
   }
 
   bool hasPackedD16() const {
     return AMDGPU::hasPackedD16(getSTI());
   }
 
private:
   bool parseExpr(OperandVector &Operands);
   StringRef getTokenStr() const;
   AsmToken peekToken();
   AsmToken getToken() const;
   SMLoc getLoc() const;
   void lex();
 
 public:
+  void onBeginOfFile() override;
+
   OperandMatchResultTy parseOptionalOperand(OperandVector &Operands);
   OperandMatchResultTy parseOptionalOpr(OperandVector &Operands);
 
   OperandMatchResultTy parseExpTgt(OperandVector &Operands);
   OperandMatchResultTy parseSendMsgOp(OperandVector &Operands);
   OperandMatchResultTy parseInterpSlot(OperandVector &Operands);
   OperandMatchResultTy parseInterpAttr(OperandVector &Operands);
   OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
AMDGPUAsmParser::parseRegister(bool RestoreOnFailure) {
   SMLoc StartLoc = Tok.getLoc();
   SMLoc EndLoc = Tok.getEndLoc();
   RegisterKind RegKind;
   unsigned Reg, RegNum, RegWidth;
 
   if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) {
     return nullptr;
   }
-  if (isHsaAbiVersion3(&getSTI())) {
+  if (isHsaAbiVersion3Or4(&getSTI())) {
     if (!updateGprCountSymbols(RegKind, RegNum, RegWidth))
       return nullptr;
   } else
     KernelScope.usesRegister(RegKind, RegNum, RegWidth);
   return AMDGPUOperand::CreateReg(this, Reg, StartLoc, EndLoc);
 }
 
 OperandMatchResultTy
bool AMDGPUAsmParser::ParseDirectiveMajorMinor(uint32_t &Major,
 
   return false;
 }
 
 bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() {
   if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)
     return TokError("directive only supported for amdgcn architecture");
 
-  std::string Target;
-
-  SMLoc TargetStart = getLoc();
-  if (getParser().parseEscapedString(Target))
+  std::string TargetIDDirective;
+  SMLoc TargetStart = getTok().getLoc();
+  if (getParser().parseEscapedString(TargetIDDirective))
     return true;
-  SMRange TargetRange = SMRange(TargetStart, getLoc());
-
-  std::string ExpectedTarget;
-  raw_string_ostream ExpectedTargetOS(ExpectedTarget);
-  IsaInfo::streamIsaVersion(&getSTI(), ExpectedTargetOS);
 
-  if (Target != ExpectedTargetOS.str())
-    return Error(TargetRange.Start, "target must match options", TargetRange);
+  SMRange TargetRange = SMRange(TargetStart, getTok().getLoc());
+  if (getTargetStreamer().getTargetID()->toString() != TargetIDDirective)
+    return getParser().Error(TargetRange.Start,
+        (Twine(".amdgcn_target directive's target id ") +
+         Twine(TargetIDDirective) +
+         Twine(" does not match the specified target id ") +
+         Twine(getTargetStreamer().getTargetID()->toString())).str());
 
-  getTargetStreamer().EmitDirectiveAMDGCNTarget(Target);
   return false;
 }
 
 bool AMDGPUAsmParser::OutOfRangeError(SMRange Range) {
   return Error(Range.Start, "value out of range", Range);
 }
 
 bool AMDGPUAsmParser::calculateGPRBlocks(
bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
 
   SMRange VGPRRange;
   uint64_t NextFreeVGPR = 0;
   SMRange SGPRRange;
   uint64_t NextFreeSGPR = 0;
   unsigned UserSGPRCount = 0;
   bool ReserveVCC = true;
   bool ReserveFlatScr = true;
-  bool ReserveXNACK = hasXNACK();
   Optional<bool> EnableWavefrontSize32;
 
   while (true) {
     while (trySkipToken(AsmToken::EndOfStatement));
 
     StringRef ID;
     SMRange IDRange = getTok().getLocRange();
     if (!parseId(ID, "expected .amdhsa_ directive or .end_amdhsa_kernel"))
AMDHSA_BITS_SET(FIELD, ENTRY, VALUE);
     if (ID == ".amdhsa_group_segment_fixed_size") {
       if (!isUInt<sizeof(KD.group_segment_fixed_size) * CHAR_BIT>(Val))
         return OutOfRangeError(ValRange);
       KD.group_segment_fixed_size = Val;
     } else if (ID == ".amdhsa_private_segment_fixed_size") {
       if (!isUInt<sizeof(KD.private_segment_fixed_size) * CHAR_BIT>(Val))
         return OutOfRangeError(ValRange);
       KD.private_segment_fixed_size = Val;
+    } else if (ID == ".amdhsa_kernarg_size") {
+      if (!isUInt<sizeof(KD.kernarg_size) * CHAR_BIT>(Val))
+        return OutOfRangeError(ValRange);
+      KD.kernarg_size = Val;
     } else if (ID == ".amdhsa_user_sgpr_private_segment_buffer") {
       PARSE_BITS_ENTRY(KD.kernel_code_properties,
                        KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER,
                        Val, ValRange);
       if (Val)
         UserSGPRCount += 4;
     } else if (ID == ".amdhsa_user_sgpr_dispatch_ptr") {
       PARSE_BITS_ENTRY(KD.kernel_code_properties,
if (ID == ".amdhsa_group_segment_fixed_size") {
       if (!isUInt<1>(Val))
         return OutOfRangeError(ValRange);
       ReserveFlatScr = Val;
     } else if (ID == ".amdhsa_reserve_xnack_mask") {
       if (IVersion.Major < 8)
         return Error(IDRange.Start, "directive requires gfx8+", IDRange);
       if (!isUInt<1>(Val))
         return OutOfRangeError(ValRange);
-      ReserveXNACK = Val;
+      if (Val != getTargetStreamer().getTargetID()->isXnackOnOrAny())
+        return getParser().Error(IDRange.Start, ".amdhsa_reserve_xnack_mask does not match target id",
+                                 IDRange);
     } else if (ID == ".amdhsa_float_round_mode_32") {
       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
                        COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32, Val, ValRange);
     } else if (ID == ".amdhsa_float_round_mode_16_64") {
       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
                        COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64, Val, ValRange);
     } else if (ID == ".amdhsa_float_denorm_mode_32") {
       PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
if (Seen.find(".amdhsa_next_free_vgpr") == Seen.end())
     return TokError(".amdhsa_next_free_vgpr directive is required");
 
   if (Seen.find(".amdhsa_next_free_sgpr") == Seen.end())
     return TokError(".amdhsa_next_free_sgpr directive is required");
 
   unsigned VGPRBlocks;
   unsigned SGPRBlocks;
   if (calculateGPRBlocks(getFeatureBits(), ReserveVCC, ReserveFlatScr,
-                         ReserveXNACK, EnableWavefrontSize32, NextFreeVGPR,
+                         getTargetStreamer().getTargetID()->isXnackOnOrAny(),
+                         EnableWavefrontSize32, NextFreeVGPR,
                          VGPRRange, NextFreeSGPR, SGPRRange, VGPRBlocks,
                          SGPRBlocks))
     return true;
 
   if (!isUInt<COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_WIDTH>(
           VGPRBlocks))
     return OutOfRangeError(VGPRRange);
   AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,
                   COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT, VGPRBlocks);
 
   if (!isUInt<COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_WIDTH>(
           SGPRBlocks))
     return OutOfRangeError(SGPRRange);
   AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,
                   COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT,
                   SGPRBlocks);
 
   if (!isUInt<COMPUTE_PGM_RSRC2_USER_SGPR_COUNT_WIDTH>(UserSGPRCount))
     return TokError("too many user SGPRs enabled");
   AMDHSA_BITS_SET(KD.compute_pgm_rsrc2, COMPUTE_PGM_RSRC2_USER_SGPR_COUNT,
                   UserSGPRCount);
 
   getTargetStreamer().EmitAmdhsaKernelDescriptor(
       getSTI(), KernelName, KD, NextFreeVGPR, NextFreeSGPR, ReserveVCC,
-      ReserveFlatScr, ReserveXNACK);
+      ReserveFlatScr);
   return false;
 }
 
 bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectVersion() {
   uint32_t Major;
   uint32_t Minor;
 
   if (ParseDirectiveMajorMinor(Major, Minor))
bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {
   uint32_t Stepping;
   StringRef VendorName;
   StringRef ArchName;
 
   // If this directive has no arguments, then use the ISA version for the
   // targeted GPU.
   if (isToken(AsmToken::EndOfStatement)) {
     AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());
-    getTargetStreamer().EmitDirectiveHSACodeObjectISA(ISA.Major, ISA.Minor,
+    getTargetStreamer().EmitDirectiveHSACodeObjectISAV2(ISA.Major, ISA.Minor,
                                                         ISA.Stepping,
                                                         "AMD", "AMDGPU");
     return false;
   }
 
   if (ParseDirectiveMajorMinor(Major, Minor))
     return true;
 
   if (!trySkipToken(AsmToken::Comma))
     return TokError("stepping version number required, comma expected");
 
   if (ParseAsAbsoluteExpression(Stepping))
     return TokError("invalid stepping version");
 
   if (!trySkipToken(AsmToken::Comma))
     return TokError("vendor name required, comma expected");
 
   if (!parseString(VendorName, "invalid vendor name"))
     return true;
 
   if (!trySkipToken(AsmToken::Comma))
     return TokError("arch name required, comma expected");
 
   if (!parseString(ArchName, "invalid arch name"))
     return true;
 
-  getTargetStreamer().EmitDirectiveHSACodeObjectISA(Major, Minor, Stepping,
+  getTargetStreamer().EmitDirectiveHSACodeObjectISAV2(Major, Minor, Stepping,
                                                       VendorName, ArchName);
   return false;
 }
 
 bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,
                                                amd_kernel_code_t &Header) {
   // max_scratch_backing_memory_byte_size is deprecated. Ignore it while parsing
   // assembly for backwards compatibility.
   if (ID == "max_scratch_backing_memory_byte_size") {

 
 bool AMDGPUAsmParser::ParseDirectiveISAVersion() {
   if (getSTI().getTargetTriple().getArch() != Triple::amdgcn) {
     return Error(getLoc(),
                  ".amd_amdgpu_isa directive is not available on non-amdgcn "
                  "architectures");
   }
 
-  auto ISAVersionStringFromASM = getToken().getStringContents();
+  auto TargetIDDirective = getLexer().getTok().getStringContents();
+  if (getTargetStreamer().getTargetID()->toString() != TargetIDDirective)
+    return Error(getParser().getTok().getLoc(), "target id must match options");
 
-  std::string ISAVersionStringFromSTI;
-  raw_string_ostream ISAVersionStreamFromSTI(ISAVersionStringFromSTI);
-  IsaInfo::streamIsaVersion(&getSTI(), ISAVersionStreamFromSTI);
-
-  if (ISAVersionStringFromASM != ISAVersionStreamFromSTI.str()) {
-    return Error(getLoc(),
-                 ".amd_amdgpu_isa directive does not match triple and/or mcpu "
-                 "arguments specified through the command line");
-  }
-
-  getTargetStreamer().EmitISAVersion(ISAVersionStreamFromSTI.str());
+  getTargetStreamer().EmitISAVersion();
   Lex();
 
   return false;
 }
 
 bool AMDGPUAsmParser::ParseDirectiveHSAMetadata() {
   const char *AssemblerDirectiveBegin;
   const char *AssemblerDirectiveEnd;
   std::tie(AssemblerDirectiveBegin, AssemblerDirectiveEnd) =
-      isHsaAbiVersion3(&getSTI())
+      isHsaAbiVersion3Or4(&getSTI())
           ? std::make_tuple(HSAMD::V3::AssemblerDirectiveBegin,
                             HSAMD::V3::AssemblerDirectiveEnd)
           : std::make_tuple(HSAMD::AssemblerDirectiveBegin,
                             HSAMD::AssemblerDirectiveEnd);
 
   if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA) {
     return Error(getLoc(),
                  (Twine(AssemblerDirectiveBegin) + Twine(" directive is "
                  "not available on non-amdhsa OSes")).str());
   }
 
   std::string HSAMetadataString;
   if (ParseToEndDirective(AssemblerDirectiveBegin, AssemblerDirectiveEnd,
                           HSAMetadataString))
     return true;
 
-  if (isHsaAbiVersion3(&getSTI())) {
+  if (isHsaAbiVersion3Or4(&getSTI())) {
     if (!getTargetStreamer().EmitHSAMetadataV3(HSAMetadataString))
       return Error(getLoc(), "invalid HSA metadata");
   } else {
     if (!getTargetStreamer().EmitHSAMetadataV2(HSAMetadataString))
       return Error(getLoc(), "invalid HSA metadata");
   }
 
   return false;
bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() {
 
   getTargetStreamer().emitAMDGPULDS(Symbol, Size, Align(Alignment));
   return false;
 }
 
 bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
   StringRef IDVal = DirectiveID.getString();
 
-  if (isHsaAbiVersion3(&getSTI())) {
-    if (IDVal == ".amdgcn_target")
-      return ParseDirectiveAMDGCNTarget();
-
+  if (isHsaAbiVersion3Or4(&getSTI())) {
     if (IDVal == ".amdhsa_kernel")
-      return ParseDirectiveAMDHSAKernel();
 
     // TODO: Restructure/combine with PAL metadata directive.
     if (IDVal == AMDGPU::HSAMD::V3::AssemblerDirectiveBegin)
       return ParseDirectiveHSAMetadata();
   } else {
     if (IDVal == ".hsa_code_object_version")
       return ParseDirectiveHSACodeObjectVersion();
 
     if (IDVal == ".hsa_code_object_isa")
       return ParseDirectiveHSACodeObjectISA();
 
     if (IDVal == ".amd_kernel_code_t")
       return ParseDirectiveAMDKernelCodeT();
 
     if (IDVal == ".amdgpu_hsa_kernel")
       return ParseDirectiveAMDGPUHsaKernel();
 
     if (IDVal == ".amd_amdgpu_isa")
       return ParseDirectiveISAVersion();
 
     if (IDVal == AMDGPU::HSAMD::AssemblerDirectiveBegin)
       return ParseDirectiveHSAMetadata();
   }
 
+  if (IDVal == ".amdgcn_target")
+    return ParseDirectiveAMDGCNTarget();
+
   if (IDVal == ".amdgpu_lds")
     return ParseDirectiveAMDGPULDS();
 
   if (IDVal == PALMD::AssemblerDirectiveBegin)
     return ParseDirectivePALMetadataBegin();
 
   if (IDVal == PALMD::AssemblerDirective)
     return ParseDirectivePALMetadata();
 
   return true;
 }
 
 bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
-                                           unsigned RegNo) const {
+                                           unsigned RegNo) {
 
   for (MCRegAliasIterator R(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, &MRI, true);
        R.isValid(); ++R) {
     if (*R == RegNo)
       return isGFX9Plus();
   }
 
   // GFX10 has 2 more SGPRs 104 and 105.
bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
   case AMDGPU::TBA_HI:
   case AMDGPU::TMA:
   case AMDGPU::TMA_LO:
   case AMDGPU::TMA_HI:
     return !isGFX9Plus();
   case AMDGPU::XNACK_MASK:
   case AMDGPU::XNACK_MASK_LO:
   case AMDGPU::XNACK_MASK_HI:
-    return (isVI() || isGFX9()) && hasXNACK();
+    return (isVI() || isGFX9()) && getTargetStreamer().getTargetID()->isXnackSupported();
   case AMDGPU::SGPR_NULL:
     return isGFX10Plus();
   default:
     break;
   }
 
   if (isCI())
     return true;
static const OptionalOperand AMDGPUOptionalOperandTable[] = {
   {"op_sel_hi", AMDGPUOperand::ImmTyOpSelHi, false, nullptr},
   {"neg_lo", AMDGPUOperand::ImmTyNegLo, false, nullptr},
   {"neg_hi", AMDGPUOperand::ImmTyNegHi, false, nullptr},
   {"blgp", AMDGPUOperand::ImmTyBLGP, false, nullptr},
   {"cbsz", AMDGPUOperand::ImmTyCBSZ, false, nullptr},
   {"abid", AMDGPUOperand::ImmTyABID, false, nullptr}
 };
 
+void AMDGPUAsmParser::onBeginOfFile() {
+  if (getSTI().getTargetTriple().getArch() == Triple::r600)
+    return;
+
+  if (!getTargetStreamer().getTargetID())
+    getTargetStreamer().initializeTargetID(getSTI(), getSTI().getFeatureString());
+
+  if (isHsaAbiVersion3Or4(&getSTI()))
+    getTargetStreamer().EmitDirectiveAMDGCNTarget();
+}
+
 OperandMatchResultTy AMDGPUAsmParser::parseOptionalOperand(OperandVector &Operands) {
 
   OperandMatchResultTy res = parseOptionalOpr(Operands);
 
   // This is a hack to enable hardcoded mandatory operands which follow
   // optional operands.
   //
   // Current design assumes that all operands after the first optional operand

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

 #define PRINT_DIRECTIVE(DIRECTIVE, MASK)                                       \
   do {                                                                         \
     KdStream << Indent << DIRECTIVE " "                                        \
              << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n';            \
   } while (0)
 
   uint16_t TwoByteBuffer = 0;
   uint32_t FourByteBuffer = 0;
-  uint64_t EightByteBuffer = 0;
 
   StringRef ReservedBytes;
   StringRef Indent = "\t";
 
   assert(Bytes.size() == 64);
   DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8);
 
   switch (Cursor.tell()) {
   case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET:
     FourByteBuffer = DE.getU32(Cursor);
     KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer
              << '\n';
     return MCDisassembler::Success;
 
   case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET:
     FourByteBuffer = DE.getU32(Cursor);
     KdStream << Indent << ".amdhsa_private_segment_fixed_size "
              << FourByteBuffer << '\n';
     return MCDisassembler::Success;
 
+  case amdhsa::KERNARG_SIZE_OFFSET:
+    FourByteBuffer = DE.getU32(Cursor);
+    KdStream << Indent << ".amdhsa_kernarg_size "
+             << FourByteBuffer << '\n';
+    return MCDisassembler::Success;
+
   case amdhsa::RESERVED0_OFFSET:
-    // 8 reserved bytes, must be 0.
-    EightByteBuffer = DE.getU64(Cursor);
-    if (EightByteBuffer) {
+    // 4 reserved bytes, must be 0.
+    ReservedBytes = DE.getBytes(Cursor, 4);
+    for (int I = 0; I < 4; ++I) {
+      if (ReservedBytes[I] != 0) {
         return MCDisassembler::Fail;
       }
+    }
     return MCDisassembler::Success;
 
   case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET:
     // KERNEL_CODE_ENTRY_BYTE_OFFSET
     // So far no directive controls this for Code Object V3, so simply skip for
     // disassembly.
     DE.skip(Cursor, 8);
     return MCDisassembler::Success;

llvm/lib/Target/AMDGPU/GCNSubtarget.h

 class GCNTargetMachine;
 
 class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
                            public AMDGPUSubtarget {
 
   using AMDGPUSubtarget::getMaxWavesPerEU;
 
 public:
-  enum TrapHandlerAbi {
-    TrapHandlerAbiNone = 0,
-    TrapHandlerAbiHsa = 1
+  // Following 2 enums are documented at:
+  //   - https://llvm.org/docs/AMDGPUUsage.html#trap-handler-abi
+  enum class TrapHandlerAbi {
+    NONE   = 0x00,
+    AMDHSA = 0x01,
   };
 
-  enum TrapID {
-    TrapIDHardwareReserved = 0,
-    TrapIDHSADebugTrap = 1,
-    TrapIDLLVMTrap = 2,
-    TrapIDLLVMDebugTrap = 3,
-    TrapIDDebugBreakpoint = 7,
-    TrapIDDebugReserved8 = 8,
-    TrapIDDebugReservedFE = 0xfe,
-    TrapIDDebugReservedFF = 0xff
-  };
-
-  enum TrapRegValues {
-    LLVMTrapHandlerRegValue = 1
+  enum class TrapID {
+    LLVMAMDHSATrap      = 0x02,
+    LLVMAMDHSADebugTrap = 0x03,
   };
 
 private:
   /// GlobalISel related APIs.
   std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
   std::unique_ptr<InlineAsmLowering> InlineAsmLoweringInfo;
   std::unique_ptr<InstructionSelector> InstSelector;
   std::unique_ptr<LegalizerInfo> Legalizer;
public:
   const LegalizerInfo *getLegalizerInfo() const override {
     return Legalizer.get();
   }
 
   const RegisterBankInfo *getRegBankInfo() const override {
     return RegBankInfo.get();
   }
 
+  const AMDGPU::IsaInfo::AMDGPUTargetID &getTargetID() const {
+    return TargetID;
+  }
+
   // Nothing implemented, just prevent crashes on use.
   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
     return &TSInfo;
   }
 
   const InstrItineraryData *getInstrItineraryData() const override {
     return &InstrItins;
   }
bool hasScalarPackInsts() const {
     return GFX9Insts;
   }
 
   bool hasScalarMulHiInsts() const {
     return GFX9Insts;
   }
 
   TrapHandlerAbi getTrapHandlerAbi() const {
-    return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone;
+    return isAmdHsaOS() ? TrapHandlerAbi::AMDHSA : TrapHandlerAbi::NONE;
+  }
+
+  bool supportsGetDoorbellID() const {
+    // The S_GETREG DOORBELL_ID is supported by all GFX9 onward targets.
+    return getGeneration() >= GFX9;
   }
 
   /// True if the offset field of DS instructions works as expected. On SI, the
   /// offset uses a 16-bit adder and does not always wrap properly.
   bool hasUsableDSOffset() const {
     return getGeneration() >= SEA_ISLANDS;
   }
 

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h

 //===-- AMDGPUTargetStreamer.h - AMDGPU Target Streamer --------*- C++ -*--===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUTARGETSTREAMER_H
 #define LLVM_LIB_TARGET_AMDGPU_MCTARGETDESC_AMDGPUTARGETSTREAMER_H
 
+#include "Utils/AMDGPUBaseInfo.h"
 #include "Utils/AMDGPUPALMetadata.h"
 #include "llvm/MC/MCStreamer.h"
 
 struct amd_kernel_code_t;
 
 namespace llvm {
 
 class DataLayout;

 namespace amdhsa {
 struct kernel_descriptor_t;
 }
 
 class AMDGPUTargetStreamer : public MCTargetStreamer {
   AMDGPUPALMetadata PALMetadata;
 
 protected:
+  // TODO: Move HSAMetadataStream to AMDGPUTargetStreamer.
+  Optional<AMDGPU::IsaInfo::AMDGPUTargetID> TargetID;
+
   MCContext &getContext() const { return Streamer.getContext(); }
 
 public:
   AMDGPUTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
 
   AMDGPUPALMetadata *getPALMetadata() { return &PALMetadata; }
 
-  virtual void EmitDirectiveAMDGCNTarget(StringRef Target) = 0;
+  virtual void EmitDirectiveAMDGCNTarget() = 0;
 
   virtual void EmitDirectiveHSACodeObjectVersion(uint32_t Major,
                                                  uint32_t Minor) = 0;
 
-  virtual void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor,
+  virtual void EmitDirectiveHSACodeObjectISAV2(uint32_t Major, uint32_t Minor,
                                                uint32_t Stepping,
                                                StringRef VendorName,
                                                StringRef ArchName) = 0;
 
   virtual void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) = 0;
 
   virtual void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) = 0;
 
   virtual void emitAMDGPULDS(MCSymbol *Symbol, unsigned Size,
                              Align Alignment) = 0;
 
   /// \returns True on success, false on failure.
-  virtual bool EmitISAVersion(StringRef IsaVersionString) = 0;
+  virtual bool EmitISAVersion() = 0;
 
   /// \returns True on success, false on failure.
   virtual bool EmitHSAMetadataV2(StringRef HSAMetadataString);
 
   /// \returns True on success, false on failure.
   virtual bool EmitHSAMetadataV3(StringRef HSAMetadataString);
 
   /// Emit HSA Metadata
public:
   virtual bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) = 0;
 
   /// \returns True on success, false on failure.
   virtual bool EmitCodeEnd() = 0;
 
   virtual void EmitAmdhsaKernelDescriptor(
       const MCSubtargetInfo &STI, StringRef KernelName,
       const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
-      uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
-      bool ReserveXNACK) = 0;
+      uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) = 0;
 
   static StringRef getArchNameFromElfMach(unsigned ElfMach);
   static unsigned getElfMach(StringRef GPU);
+
+  const Optional<AMDGPU::IsaInfo::AMDGPUTargetID> &getTargetID() const {
+    return TargetID;
+  }
+  Optional<AMDGPU::IsaInfo::AMDGPUTargetID> &getTargetID() {
+    return TargetID;
+  }
+  void initializeTargetID(const MCSubtargetInfo &STI) {
+    assert(TargetID == None && "TargetID can only be initialized once");
+    TargetID.emplace(STI);
+  }
+  void initializeTargetID(const MCSubtargetInfo &STI, StringRef FeatureString) {
+    initializeTargetID(STI);
+
+    assert(getTargetID() != None && "TargetID is None");
+    getTargetID()->setTargetIDFromFeaturesString(FeatureString);
+  }
 };
 
 class AMDGPUTargetAsmStreamer final : public AMDGPUTargetStreamer {
   formatted_raw_ostream &OS;
 public:
   AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
 
   void finish() override;
 
-  void EmitDirectiveAMDGCNTarget(StringRef Target) override;
+  void EmitDirectiveAMDGCNTarget() override;
 
   void EmitDirectiveHSACodeObjectVersion(uint32_t Major,
                                          uint32_t Minor) override;
 
-  void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor,
+  void EmitDirectiveHSACodeObjectISAV2(uint32_t Major, uint32_t Minor,
                                        uint32_t Stepping, StringRef VendorName,
                                        StringRef ArchName) override;
 
   void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override;
 
   void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override;
 
   void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override;
 
   /// \returns True on success, false on failure.
-  bool EmitISAVersion(StringRef IsaVersionString) override;
+  bool EmitISAVersion() override;
 
   /// \returns True on success, false on failure.
   bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override;
 
   /// \returns True on success, false on failure.
   bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) override;
 
   /// \returns True on success, false on failure.
   bool EmitCodeEnd() override;
 
   void EmitAmdhsaKernelDescriptor(
       const MCSubtargetInfo &STI, StringRef KernelName,
       const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
-      uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
-      bool ReserveXNACK) override;
+      uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) override;
 };
 
 class AMDGPUTargetELFStreamer final : public AMDGPUTargetStreamer {
+  const MCSubtargetInfo &STI;
   MCStreamer &Streamer;
-  Triple::OSType Os;
 
   void EmitNote(StringRef Name, const MCExpr *DescSize, unsigned NoteType,
                 function_ref<void(MCELFStreamer &)> EmitDesc);
 
+  unsigned getEFlags();
+
+  unsigned getEFlagsR600();
+  unsigned getEFlagsAMDGCN();
+
+  unsigned getEFlagsUnknownOS();
+  unsigned getEFlagsAMDHSA();
+  unsigned getEFlagsAMDPAL();
+  unsigned getEFlagsMesa3D();
+
+  unsigned getEFlagsV3();
+  unsigned getEFlagsV4();
+
 public:
   AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI);
 
   MCELFStreamer &getStreamer();
 
   void finish() override;
 
-  void EmitDirectiveAMDGCNTarget(StringRef Target) override;
+  void EmitDirectiveAMDGCNTarget() override;
 
   void EmitDirectiveHSACodeObjectVersion(uint32_t Major,
                                          uint32_t Minor) override;
 
-  void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor,
+  void EmitDirectiveHSACodeObjectISAV2(uint32_t Major, uint32_t Minor,
                                        uint32_t Stepping, StringRef VendorName,
                                        StringRef ArchName) override;
 
   void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override;
 
   void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override;
 
   void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override;
 
   /// \returns True on success, false on failure.
-  bool EmitISAVersion(StringRef IsaVersionString) override;
+  bool EmitISAVersion() override;
 
   /// \returns True on success, false on failure.
   bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override;
 
   /// \returns True on success, false on failure.
   bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) override;
 
   /// \returns True on success, false on failure.
   bool EmitCodeEnd() override;
 
   void EmitAmdhsaKernelDescriptor(
       const MCSubtargetInfo &STI, StringRef KernelName,
       const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
-      uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
-      bool ReserveXNACK) override;
+      uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) override;
 };
 
 }
 #endif

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

 
 using namespace llvm;
 using namespace llvm::AMDGPU;
 
 //===----------------------------------------------------------------------===//
 // AMDGPUTargetStreamer
 //===----------------------------------------------------------------------===//
 
+static void convertIsaVersionV2(uint32_t &Major, uint32_t &Minor,
+                                uint32_t &Stepping, bool Sramecc, bool Xnack) {
+  if (Major == 9 && Minor == 0) {
+    switch (Stepping) {
+      case 0:
+      case 2:
+      case 4:
+      case 6:
+        if (Xnack)
+          Stepping++;
+    }
+  }
+}
+
 bool AMDGPUTargetStreamer::EmitHSAMetadataV2(StringRef HSAMetadataString) {
   HSAMD::Metadata HSAMetadata;
   if (HSAMD::fromString(HSAMetadataString, HSAMetadata))
     return false;
   return EmitHSAMetadata(HSAMetadata);
 }
 
 bool AMDGPUTargetStreamer::EmitHSAMetadataV3(StringRef HSAMetadataString) {
void AMDGPUTargetAsmStreamer::finish() {
   getPALMetadata()->toString(S);
   OS << S;
 
   // Reset the pal metadata so its data will not affect a compilation that
   // reuses this object.
   getPALMetadata()->reset();
 }
 
-void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {
-  OS << "\t.amdgcn_target \"" << Target << "\"\n";
+void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget() {
+  OS << "\t.amdgcn_target \"" << getTargetID()->toString() << "\"\n";
 }
 
 void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion(
     uint32_t Major, uint32_t Minor) {
   OS << "\t.hsa_code_object_version " <<
         Twine(Major) << "," << Twine(Minor) << '\n';
 }
 
 void
-AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major,
+AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major,
                                                          uint32_t Minor,
                                                          uint32_t Stepping,
                                                          StringRef VendorName,
                                                          StringRef ArchName) {
-  OS << "\t.hsa_code_object_isa " <<
-        Twine(Major) << "," << Twine(Minor) << "," << Twine(Stepping) <<
-        ",\"" << VendorName << "\",\"" << ArchName << "\"\n";
-
+  convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny());
+  OS << "\t.hsa_code_object_isa " << Twine(Major) << "," << Twine(Minor) << ","
+     << Twine(Stepping) << ",\"" << VendorName << "\",\"" << ArchName << "\"\n";
 }
 
 void
 AMDGPUTargetAsmStreamer::EmitAMDKernelCodeT(const amd_kernel_code_t &Header) {
   OS << "\t.amd_kernel_code_t\n";
   dumpAmdKernelCode(&Header, OS, "\t\t");
   OS << "\t.end_amd_kernel_code_t\n";
 }

 }
 
 void AMDGPUTargetAsmStreamer::emitAMDGPULDS(MCSymbol *Symbol, unsigned Size,
                                             Align Alignment) {
   OS << "\t.amdgpu_lds " << Symbol->getName() << ", " << Size << ", "
      << Alignment.value() << '\n';
 }
 
-bool AMDGPUTargetAsmStreamer::EmitISAVersion(StringRef IsaVersionString) {
-  OS << "\t.amd_amdgpu_isa \"" << IsaVersionString << "\"\n";
+bool AMDGPUTargetAsmStreamer::EmitISAVersion() {
+  OS << "\t.amd_amdgpu_isa \"" << getTargetID()->toString() << "\"\n";
   return true;
 }
 
 bool AMDGPUTargetAsmStreamer::EmitHSAMetadata(
     const AMDGPU::HSAMD::Metadata &HSAMetadata) {
   std::string HSAMetadataString;
   if (HSAMD::toString(HSAMetadata, HSAMetadataString))
     return false;
bool AMDGPUTargetAsmStreamer::EmitCodeEnd() {
   OS << "\t.p2alignl 6, " << Encoded_s_code_end << '\n';
   OS << "\t.fill 48, 4, " << Encoded_s_code_end << '\n';
   return true;
 }
 
 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
     const MCSubtargetInfo &STI, StringRef KernelName,
     const amdhsa::kernel_descriptor_t &KD, uint64_t NextVGPR, uint64_t NextSGPR,
-    bool ReserveVCC, bool ReserveFlatScr, bool ReserveXNACK) {
+    bool ReserveVCC, bool ReserveFlatScr) {
   IsaVersion IVersion = getIsaVersion(STI.getCPU());
 
   OS << "\t.amdhsa_kernel " << KernelName << '\n';
 
 #define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME)   \
   STREAM << "\t\t" << DIRECTIVE << " "                                         \
          << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n';
 
   OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size
      << '\n';
   OS << "\t\t.amdhsa_private_segment_fixed_size "
      << KD.private_segment_fixed_size << '\n';
+  OS << "\t\t.amdhsa_kernarg_size " << KD.kernarg_size << '\n';
 
   PRINT_FIELD(OS, ".amdhsa_user_sgpr_private_segment_buffer", KD,
               kernel_code_properties,
               amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
   PRINT_FIELD(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD,
               kernel_code_properties,
               amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
   PRINT_FIELD(OS, ".amdhsa_user_sgpr_queue_ptr", KD,
#define PRINT_FIELD(STREAM, DIRECTIVE, KERNEL_DESC, MEMBER_NAME, FIELD_NAME)   \
   // These directives are required.
   OS << "\t\t.amdhsa_next_free_vgpr " << NextVGPR << '\n';
   OS << "\t\t.amdhsa_next_free_sgpr " << NextSGPR << '\n';
 
   if (!ReserveVCC)
     OS << "\t\t.amdhsa_reserve_vcc " << ReserveVCC << '\n';
   if (IVersion.Major >= 7 && !ReserveFlatScr)
     OS << "\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr << '\n';
-  if (IVersion.Major >= 8 && ReserveXNACK != hasXNACK(STI))
-    OS << "\t\t.amdhsa_reserve_xnack_mask " << ReserveXNACK << '\n';
+
+  if (const auto &&HsaAbiVer = getHsaAbiVersion(&STI)) {
+    switch (HsaAbiVer.getValue()) {
+    default:
+      break;
+    case ELF::ELFABIVERSION_AMDGPU_HSA_V2:
+      break;
+    case ELF::ELFABIVERSION_AMDGPU_HSA_V3:
+    case ELF::ELFABIVERSION_AMDGPU_HSA_V4:
+      if (getTargetID()->isXnackSupported())
+        OS << "\t\t.amdhsa_reserve_xnack_mask " << getTargetID()->isXnackOnOrAny() << '\n';
+      break;
+    }
+  }
 
   PRINT_FIELD(OS, ".amdhsa_float_round_mode_32", KD,
               compute_pgm_rsrc1,
               amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
   PRINT_FIELD(OS, ".amdhsa_float_round_mode_16_64", KD,
               compute_pgm_rsrc1,
               amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
   PRINT_FIELD(OS, ".amdhsa_float_denorm_mode_32", KD,

 }
 
 //===----------------------------------------------------------------------===//
 // AMDGPUTargetELFStreamer
 //===----------------------------------------------------------------------===//
 
 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(MCStreamer &S,
                                                  const MCSubtargetInfo &STI)
-    : AMDGPUTargetStreamer(S), Streamer(S), Os(STI.getTargetTriple().getOS()) {
-  MCAssembler &MCA = getStreamer().getAssembler();
-  unsigned EFlags = MCA.getELFHeaderEFlags();
-
-  EFlags &= ~ELF::EF_AMDGPU_MACH;
-  EFlags |= getElfMach(STI.getCPU());
-
-  EFlags &= ~ELF::EF_AMDGPU_XNACK;
-  if (AMDGPU::hasXNACK(STI))
-    EFlags |= ELF::EF_AMDGPU_XNACK;
-
-  EFlags &= ~ELF::EF_AMDGPU_SRAM_ECC;
-  if (AMDGPU::hasSRAMECC(STI))
-    EFlags |= ELF::EF_AMDGPU_SRAM_ECC;
-
-  MCA.setELFHeaderEFlags(EFlags);
-}
+    : AMDGPUTargetStreamer(S), STI(STI), Streamer(S) {}
 
 MCELFStreamer &AMDGPUTargetELFStreamer::getStreamer() {
   return static_cast<MCELFStreamer &>(Streamer);
 }
 
 // A hook for emitting stuff at the end.
 // We use it for emitting the accumulated PAL metadata as a .note record.
 // The PAL metadata is reset after it is emitted.
 void AMDGPUTargetELFStreamer::finish() {
+  MCAssembler &MCA = getStreamer().getAssembler();
+  MCA.setELFHeaderEFlags(getEFlags());
+
   std::string Blob;
   const char *Vendor = getPALMetadata()->getVendor();
   unsigned Type = getPALMetadata()->getType();
   getPALMetadata()->toBlob(Type, Blob);
   if (Blob.empty())
     return;
   EmitNote(Vendor, MCConstantExpr::create(Blob.size(), getContext()), Type,
            [&](MCELFStreamer &OS) { OS.emitBytes(Blob); });
void AMDGPUTargetELFStreamer::EmitNote(
   auto &S = getStreamer();
   auto &Context = S.getContext();
 
   auto NameSZ = Name.size() + 1;
 
   unsigned NoteFlags = 0;
   // TODO Apparently, this is currently needed for OpenCL as mentioned in
   // https://reviews.llvm.org/D74995
-  if (Os == Triple::AMDHSA)
+  if (STI.getTargetTriple().getOS() == Triple::AMDHSA)
     NoteFlags = ELF::SHF_ALLOC;
 
   S.PushSection();
   S.SwitchSection(
       Context.getELFSection(ElfNote::SectionName, ELF::SHT_NOTE, NoteFlags));
   S.emitInt32(NameSZ);                                        // namesz
   S.emitValue(DescSZ, 4);                                     // descz
   S.emitInt32(NoteType);                                      // type
   S.emitBytes(Name);                                          // name
   S.emitValueToAlignment(4, 0, 1, 0);                         // padding 0
   EmitDesc(S);                                                // desc
   S.emitValueToAlignment(4, 0, 1, 0);                         // padding 0
   S.PopSection();
 }
 
-void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {}
+unsigned AMDGPUTargetELFStreamer::getEFlags() {
+  switch (STI.getTargetTriple().getArch()) {
+  default:
+    llvm_unreachable("Unsupported Arch");
+  case Triple::r600:
+    return getEFlagsR600();
+  case Triple::amdgcn:
+    return getEFlagsAMDGCN();
+  }
+}
+
+unsigned AMDGPUTargetELFStreamer::getEFlagsR600() {
+  assert(STI.getTargetTriple().getArch() == Triple::r600);
+
+  return getElfMach(STI.getCPU());
+}
+
+unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() {
+  assert(STI.getTargetTriple().getArch() == Triple::amdgcn);
+
+  switch (STI.getTargetTriple().getOS()) {
+  default:
+    // TODO: Why are some tests have "mingw" listed as OS?
+    // llvm_unreachable("Unsupported OS");
+  case Triple::UnknownOS:
+    return getEFlagsUnknownOS();
+  case Triple::AMDHSA:
+    return getEFlagsAMDHSA();
+  case Triple::AMDPAL:
+    return getEFlagsAMDPAL();
+  case Triple::Mesa3D:
+    return getEFlagsMesa3D();
+  }
+}
+
+unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() {
+  // TODO: Why are some tests have "mingw" listed as OS?
+  // assert(STI.getTargetTriple().getOS() == Triple::UnknownOS);
+
+  return getEFlagsV3();
+}
+
+unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() {
+  assert(STI.getTargetTriple().getOS() == Triple::AMDHSA);
+
+  if (const auto &&HsaAbiVer = getHsaAbiVersion(&STI)) {
+    switch (HsaAbiVer.getValue()) {
+    case ELF::ELFABIVERSION_AMDGPU_HSA_V2:
+    case ELF::ELFABIVERSION_AMDGPU_HSA_V3:
+      return getEFlagsV3();
+    case ELF::ELFABIVERSION_AMDGPU_HSA_V4:
+      return getEFlagsV4();
+    }
+  }
+
+  llvm_unreachable("HSA OS ABI Version identification must be defined");
+}
+
+unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() {
+  assert(STI.getTargetTriple().getOS() == Triple::AMDPAL);
+
+  return getEFlagsV3();
+}
+
+unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() {
+  assert(STI.getTargetTriple().getOS() == Triple::Mesa3D);
+
+  return getEFlagsV3();
+}
+
+unsigned AMDGPUTargetELFStreamer::getEFlagsV3() {
+  unsigned EFlagsV3 = 0;
+
+  // mach.
+  EFlagsV3 |= getElfMach(STI.getCPU());
+
+  // xnack.
+  if (getTargetID()->isXnackOnOrAny())
+    EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_XNACK_V3;
+  // sramecc.
+  if (getTargetID()->isSramEccOnOrAny())
+    EFlagsV3 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_V3;
+
+  return EFlagsV3;
+}
+
+unsigned AMDGPUTargetELFStreamer::getEFlagsV4() {
+  unsigned EFlagsV4 = 0;
+
+  // mach.
+  EFlagsV4 |= getElfMach(STI.getCPU());
+
+  // xnack.
+  switch (getTargetID()->getXnackSetting()) {
+  case AMDGPU::IsaInfo::TargetIDSetting::Unsupported:
+    EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4;
+    break;
+  case AMDGPU::IsaInfo::TargetIDSetting::Any:
+    EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ANY_V4;
+    break;
+  case AMDGPU::IsaInfo::TargetIDSetting::Off:
+    EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_OFF_V4;
+    break;
+  case AMDGPU::IsaInfo::TargetIDSetting::On:
+    EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_XNACK_ON_V4;
+    break;
+  }
+  // sramecc.
+  switch (getTargetID()->getSramEccSetting()) {
+  case AMDGPU::IsaInfo::TargetIDSetting::Unsupported:
+    EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4;
+    break;
+  case AMDGPU::IsaInfo::TargetIDSetting::Any:
+    EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ANY_V4;
+    break;
+  case AMDGPU::IsaInfo::TargetIDSetting::Off:
+    EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_OFF_V4;
+    break;
+  case AMDGPU::IsaInfo::TargetIDSetting::On:
+    EFlagsV4 |= ELF::EF_AMDGPU_FEATURE_SRAMECC_ON_V4;
+    break;
+  }
+
+  return EFlagsV4;
+}
+
+void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget() {}
 
 void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion(
     uint32_t Major, uint32_t Minor) {
 
   EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(8, getContext()),
-           ElfNote::NT_AMDGPU_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) {
+           ELF::NT_AMD_HSA_CODE_OBJECT_VERSION, [&](MCELFStreamer &OS) {
              OS.emitInt32(Major);
              OS.emitInt32(Minor);
            });
 }
 
 void
-AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major,
+AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectISAV2(uint32_t Major,
                                                          uint32_t Minor,
                                                          uint32_t Stepping,
                                                          StringRef VendorName,
                                                          StringRef ArchName) {
   uint16_t VendorNameSize = VendorName.size() + 1;
   uint16_t ArchNameSize = ArchName.size() + 1;
 
   unsigned DescSZ = sizeof(VendorNameSize) + sizeof(ArchNameSize) +
     sizeof(Major) + sizeof(Minor) + sizeof(Stepping) +
     VendorNameSize + ArchNameSize;
 
+  convertIsaVersionV2(Major, Minor, Stepping, TargetID->isSramEccOnOrAny(), TargetID->isXnackOnOrAny());
   EmitNote(ElfNote::NoteNameV2, MCConstantExpr::create(DescSZ, getContext()),
-           ElfNote::NT_AMDGPU_HSA_ISA, [&](MCELFStreamer &OS) {
+           ELF::NT_AMD_HSA_ISA_VERSION, [&](MCELFStreamer &OS) {
              OS.emitInt16(VendorNameSize);
              OS.emitInt16(ArchNameSize);
              OS.emitInt32(Major);
              OS.emitInt32(Minor);
              OS.emitInt32(Stepping);
              OS.emitBytes(VendorName);
              OS.emitInt8(0); // NULL terminate VendorName
              OS.emitBytes(ArchName);
if (SymbolELF->declareCommon(Size, Alignment.value(), true)) {
     report_fatal_error("Symbol: " + Symbol->getName() +
                        " redeclared as different type");
   }
 
   SymbolELF->setIndex(ELF::SHN_AMDGPU_LDS);
   SymbolELF->setSize(MCConstantExpr::create(Size, getContext()));
 }
 
-bool AMDGPUTargetELFStreamer::EmitISAVersion(StringRef IsaVersionString) {
+bool AMDGPUTargetELFStreamer::EmitISAVersion() {
   // Create two labels to mark the beginning and end of the desc field
   // and a MCExpr to calculate the size of the desc field.
   auto &Context = getContext();
   auto *DescBegin = Context.createTempSymbol();
   auto *DescEnd = Context.createTempSymbol();
   auto *DescSZ = MCBinaryExpr::createSub(
     MCSymbolRefExpr::create(DescEnd, Context),
     MCSymbolRefExpr::create(DescBegin, Context), Context);
 
-  EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_ISA,
+  EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_ISA_NAME,
            [&](MCELFStreamer &OS) {
              OS.emitLabel(DescBegin);
-             OS.emitBytes(IsaVersionString);
+             OS.emitBytes(getTargetID()->toString());
              OS.emitLabel(DescEnd);
            });
   return true;
 }
 
 bool AMDGPUTargetELFStreamer::EmitHSAMetadata(msgpack::Document &HSAMetadataDoc,
                                               bool Strict) {
   HSAMD::V3::MetadataVerifier Verifier(Strict);
bool AMDGPUTargetELFStreamer::EmitHSAMetadata(
   // and a MCExpr to calculate the size of the desc field.
   auto &Context = getContext();
   auto *DescBegin = Context.createTempSymbol();
   auto *DescEnd = Context.createTempSymbol();
   auto *DescSZ = MCBinaryExpr::createSub(
     MCSymbolRefExpr::create(DescEnd, Context),
     MCSymbolRefExpr::create(DescBegin, Context), Context);
 
-  EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_AMDGPU_HSA_METADATA,
+  EmitNote(ElfNote::NoteNameV2, DescSZ, ELF::NT_AMD_HSA_METADATA,
            [&](MCELFStreamer &OS) {
              OS.emitLabel(DescBegin);
              OS.emitBytes(HSAMetadataString);
              OS.emitLabel(DescEnd);
            });
   return true;
 }
 
 bool AMDGPUTargetELFStreamer::EmitCodeEnd() {
   const uint32_t Encoded_s_code_end = 0xbf9f0000;
 
   MCStreamer &OS = getStreamer();
   OS.PushSection();
   OS.emitValueToAlignment(64, Encoded_s_code_end, 4);
   for (unsigned I = 0; I < 48; ++I)
     OS.emitInt32(Encoded_s_code_end);
   OS.PopSection();
   return true;
 }
 
 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor(
     const MCSubtargetInfo &STI, StringRef KernelName,
     const amdhsa::kernel_descriptor_t &KernelDescriptor, uint64_t NextVGPR,
-    uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr,
-    bool ReserveXNACK) {
+    uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) {
   auto &Streamer = getStreamer();
   auto &Context = Streamer.getContext();
 
   MCSymbolELF *KernelCodeSymbol = cast<MCSymbolELF>(
       Context.getOrCreateSymbol(Twine(KernelName)));
   MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>(
       Context.getOrCreateSymbol(Twine(KernelName) + Twine(".kd")));
 
void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor(
   // The visibility of the kernel code symbol must be protected or less to allow
   // static relocations from the kernel descriptor to be used.
   if (KernelCodeSymbol->getVisibility() == ELF::STV_DEFAULT)
     KernelCodeSymbol->setVisibility(ELF::STV_PROTECTED);
 
   Streamer.emitLabel(KernelDescriptorSymbol);
   Streamer.emitInt32(KernelDescriptor.group_segment_fixed_size);
   Streamer.emitInt32(KernelDescriptor.private_segment_fixed_size);
+  Streamer.emitInt32(KernelDescriptor.kernarg_size);
+
   for (uint8_t Res : KernelDescriptor.reserved0)
     Streamer.emitInt8(Res);
+
   // FIXME: Remove the use of VK_AMDGPU_REL64 in the expression below. The
   // expression being created is:
   //   (start of kernel code) - (start of kernel descriptor)
   // It implies R_AMDGPU_REL64, but ends up being R_AMDGPU_ABS64.
   Streamer.emitValue(MCBinaryExpr::createSub(
       MCSymbolRefExpr::create(
           KernelCodeSymbol, MCSymbolRefExpr::VK_AMDGPU_REL64, Context),
       MCSymbolRefExpr::create(

llvm/lib/Target/AMDGPU/SIISelLowering.h

SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
                              SelectionDAG &DAG) const;
 
   SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
+
   SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerTrapEndpgm(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerTrapHsaQueuePtr(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerTrapHsa(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const;
 
   SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
 
   SDValue performUCharToFloatCombine(SDNode *N,
                                      DAGCombinerInfo &DCI) const;
   SDValue performSHLPtrCombine(SDNode *N,
                                unsigned AS,

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

 #include "SIISelLowering.h"
 #include "AMDGPU.h"
 #include "AMDGPUInstrInfo.h"
 #include "AMDGPUTargetMachine.h"
 #include "SIMachineFunctionInfo.h"
 #include "SIRegisterInfo.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Analysis/LegacyDivergenceAnalysis.h"
+#include "llvm/BinaryFormat/ELF.h"
 #include "llvm/CodeGen/Analysis.h"
 #include "llvm/CodeGen/FunctionLoweringInfo.h"
 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/IR/IntrinsicsAMDGPU.h"
 #include "llvm/IR/IntrinsicsR600.h"
 #include "llvm/Support/CommandLine.h"
? DAG.getNode(ISD::SRA, SL, VT, Result,
                   DAG.getConstant(VT.getScalarSizeInBits() - 1, SL, MVT::i32))
     : DAG.getConstant(0, SL, VT);
   SDValue Overflow = DAG.getSetCC(SL, MVT::i1, Top, Sign, ISD::SETNE);
 
   return DAG.getMergeValues({ Result, Overflow }, SL);
 }
 
 SDValue SITargetLowering::lowerTRAP(SDValue Op, SelectionDAG &DAG) const {
+  if (!Subtarget->isTrapHandlerEnabled() ||
+      Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA)
+    return lowerTrapEndpgm(Op, DAG);
+
+  if (const auto &&HsaAbiVer = AMDGPU::getHsaAbiVersion(Subtarget)) {
+    switch (HsaAbiVer.getValue()) {
+    case ELF::ELFABIVERSION_AMDGPU_HSA_V2:
+    case ELF::ELFABIVERSION_AMDGPU_HSA_V3:
+      return lowerTrapHsaQueuePtr(Op, DAG);
+    case ELF::ELFABIVERSION_AMDGPU_HSA_V4:
+      return Subtarget->supportsGetDoorbellID() ?
+          lowerTrapHsa(Op, DAG) : lowerTrapHsaQueuePtr(Op, DAG);
+    }
+  }
+
+  llvm_unreachable("Unknown trap handler");
+}
+
+SDValue SITargetLowering::lowerTrapEndpgm(
+    SDValue Op, SelectionDAG &DAG) const {
   SDLoc SL(Op);
   SDValue Chain = Op.getOperand(0);
-
-  if (Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa ||
-      !Subtarget->isTrapHandlerEnabled())
-    return DAG.getNode(AMDGPUISD::ENDPGM, SL, MVT::Other, Chain);
+}
+
+SDValue SITargetLowering::lowerTrapHsaQueuePtr(
+    SDValue Op, SelectionDAG &DAG) const {
+  SDLoc SL(Op);
+  SDValue Chain = Op.getOperand(0);
 
   MachineFunction &MF = DAG.getMachineFunction();
   SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
   Register UserSGPR = Info->getQueuePtrUserSGPR();
   assert(UserSGPR != AMDGPU::NoRegister);
   SDValue QueuePtr = CreateLiveInRegister(
     DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
   SDValue SGPR01 = DAG.getRegister(AMDGPU::SGPR0_SGPR1, MVT::i64);
   SDValue ToReg = DAG.getCopyToReg(Chain, SL, SGPR01,
                                    QueuePtr, SDValue());
+
+  uint64_t TrapID = static_cast<uint64_t>(GCNSubtarget::TrapID::LLVMAMDHSATrap);
   SDValue Ops[] = {
     ToReg,
-    DAG.getTargetConstant(GCNSubtarget::TrapIDLLVMTrap, SL, MVT::i16),
+    DAG.getTargetConstant(TrapID, SL, MVT::i16),
     SGPR01,
     ToReg.getValue(1)
   };
   return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
 }
 
+SDValue SITargetLowering::lowerTrapHsa(
+    SDValue Op, SelectionDAG &DAG) const {
+  SDLoc SL(Op);
+  SDValue Chain = Op.getOperand(0);
+
+  uint64_t TrapID = static_cast<uint64_t>(GCNSubtarget::TrapID::LLVMAMDHSATrap);
+  SDValue Ops[] = {
+    Chain,
+    DAG.getTargetConstant(TrapID, SL, MVT::i16)
+  };
+  return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
+}
+
 SDValue SITargetLowering::lowerDEBUGTRAP(SDValue Op, SelectionDAG &DAG) const {
   SDLoc SL(Op);
   SDValue Chain = Op.getOperand(0);
   MachineFunction &MF = DAG.getMachineFunction();
 
-  if (Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa ||
-      !Subtarget->isTrapHandlerEnabled()) {
+  if (!Subtarget->isTrapHandlerEnabled() ||
+      Subtarget->getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbi::AMDHSA) {
     DiagnosticInfoUnsupported NoTrap(MF.getFunction(),
                                      "debugtrap handler not supported",
                                      Op.getDebugLoc(),
                                      DS_Warning);
     LLVMContext &Ctx = MF.getFunction().getContext();
     Ctx.diagnose(NoTrap);
     return Chain;
   }
 
+  uint64_t TrapID = static_cast<uint64_t>(GCNSubtarget::TrapID::LLVMAMDHSADebugTrap);
   SDValue Ops[] = {
     Chain,
-    DAG.getTargetConstant(GCNSubtarget::TrapIDLLVMDebugTrap, SL, MVT::i16)
+    DAG.getTargetConstant(TrapID, SL, MVT::i16)
   };
   return DAG.getNode(AMDGPUISD::TRAP, SL, MVT::Other, Ops);
 }
 
 SDValue SITargetLowering::getSegmentAperture(unsigned AS, const SDLoc &DL,
                                              SelectionDAG &DAG) const {
   // FIXME: Use inline constants (src_{shared, private}_base) instead.
   if (Subtarget->hasApertureRegs()) {

llvm/lib/Target/AMDGPU/SIInstrInfo.td

def DSTCLAMP {
   int NONE = 0;
   int ENABLE = 1;
 }
 
 def DSTOMOD {
   int NONE = 0;
 }
 
-def TRAPID{
-  int LLVM_TRAP = 2;
-  int LLVM_DEBUG_TRAP = 3;
-}
-
 def HWREG {
   int MODE = 1;
   int STATUS = 2;
   int TRAPSTS = 3;
   int HW_ID = 4;
   int GPR_ALLOC = 5;
   int LDS_ALLOC = 6;
   int IB_STS = 7;

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

 /// \returns HSA OS ABI Version identification.
 Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI);
 /// \returns True if HSA OS ABI Version identification is 2,
 /// false otherwise.
 bool isHsaAbiVersion2(const MCSubtargetInfo *STI);
 /// \returns True if HSA OS ABI Version identification is 3,
 /// false otherwise.
 bool isHsaAbiVersion3(const MCSubtargetInfo *STI);
+/// \returns True if HSA OS ABI Version identification is 4,
+/// false otherwise.
+bool isHsaAbiVersion4(const MCSubtargetInfo *STI);
+/// \returns True if HSA OS ABI Version identification is 3 or 4,
+/// false otherwise.
+bool isHsaAbiVersion3Or4(const MCSubtargetInfo *STI);
 
 struct GcnBufferFormatInfo {
   unsigned Format;
   unsigned BitsPerComp;
   unsigned NumComponents;
   unsigned NumFormat;
   unsigned DataFormat;
 };
enum class TargetIDSetting {
   Unsupported,
   Any,
   Off,
   On
 };
 
 class AMDGPUTargetID {
 private:
+  const MCSubtargetInfo &STI;
   TargetIDSetting XnackSetting;
   TargetIDSetting SramEccSetting;
 
 public:
   explicit AMDGPUTargetID(const MCSubtargetInfo &STI);
   ~AMDGPUTargetID() = default;
 
   /// \return True if the current xnack setting is not "Unsupported".
public:
 
   /// Sets sramecc setting to \p NewSramEccSetting.
   void setSramEccSetting(TargetIDSetting NewSramEccSetting) {
     SramEccSetting = NewSramEccSetting;
   }
 
   void setTargetIDFromFeaturesString(StringRef FS);
   void setTargetIDFromTargetIDStream(StringRef TargetID);
-};
 
-/// Streams isa version string for given subtarget \p STI into \p Stream.
-void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);
+  /// \returns String representation of an object.
+  std::string toString() const;
+};
 
 /// \returns Wavefront size for given subtarget \p STI.
 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
 
 /// \returns Local memory size in bytes for given subtarget \p STI.
 unsigned getLocalMemorySize(const MCSubtargetInfo *STI);
 
 /// \returns Number of execution units per compute unit for given subtarget \p

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

 #include "llvm/Support/TargetParser.h"
 
 #define GET_INSTRINFO_NAMED_OPS
 #define GET_INSTRMAP_INFO
 #include "AMDGPUGenInstrInfo.inc"
 
 static llvm::cl::opt<unsigned> AmdhsaCodeObjectVersion(
   "amdhsa-code-object-version", llvm::cl::Hidden,
-  llvm::cl::desc("AMDHSA Code Object Version"), llvm::cl::init(3));
+  llvm::cl::desc("AMDHSA Code Object Version"), llvm::cl::init(4),
+  llvm::cl::ZeroOrMore);
 
 namespace {
 
 /// \returns Bit mask for given bit \p Shift and bit \p Width.
 unsigned getBitMask(unsigned Shift, unsigned Width) {
   return ((1 << Width) - 1) << Shift;
 }
 
Optional<uint8_t> getHsaAbiVersion(const MCSubtargetInfo *STI) {
   if (STI && STI->getTargetTriple().getOS() != Triple::AMDHSA)
     return None;
 
   switch (AmdhsaCodeObjectVersion) {
   case 2:
     return ELF::ELFABIVERSION_AMDGPU_HSA_V2;
   case 3:
     return ELF::ELFABIVERSION_AMDGPU_HSA_V3;
+  case 4:
+    return ELF::ELFABIVERSION_AMDGPU_HSA_V4;
   default:
-    return ELF::ELFABIVERSION_AMDGPU_HSA_V3;
+    report_fatal_error(Twine("Unsupported AMDHSA Code Object Version ") +
+                       Twine(AmdhsaCodeObjectVersion));
   }
 }
 
 bool isHsaAbiVersion2(const MCSubtargetInfo *STI) {
   if (const auto &&HsaAbiVer = getHsaAbiVersion(STI))
     return HsaAbiVer.getValue() == ELF::ELFABIVERSION_AMDGPU_HSA_V2;
   return false;
 }
 
 bool isHsaAbiVersion3(const MCSubtargetInfo *STI) {
   if (const auto &&HsaAbiVer = getHsaAbiVersion(STI))
     return HsaAbiVer.getValue() == ELF::ELFABIVERSION_AMDGPU_HSA_V3;
   return false;
 }
 
+bool isHsaAbiVersion4(const MCSubtargetInfo *STI) {
+  if (const auto &&HsaAbiVer = getHsaAbiVersion(STI))
+    return HsaAbiVer.getValue() == ELF::ELFABIVERSION_AMDGPU_HSA_V4;
+  return false;
+}
+
+bool isHsaAbiVersion3Or4(const MCSubtargetInfo *STI) {
+  return isHsaAbiVersion3(STI) || isHsaAbiVersion4(STI);
+}
+
 #define GET_MIMGBaseOpcodesTable_IMPL
 #define GET_MIMGDimInfoTable_IMPL
 #define GET_MIMGInfoTable_IMPL
 #define GET_MIMGLZMappingTable_IMPL
 #define GET_MIMGMIPMappingTable_IMPL
 #define GET_MIMGG16MappingTable_IMPL
 #include "AMDGPUGenSearchableTables.inc"
 

 // instead.
 int getMCOpcode(uint16_t Opcode, unsigned Gen) {
   return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
 }
 
 namespace IsaInfo {
 
 AMDGPUTargetID::AMDGPUTargetID(const MCSubtargetInfo &STI)
-    : XnackSetting(TargetIDSetting::Any), SramEccSetting(TargetIDSetting::Any) {
+    : STI(STI), XnackSetting(TargetIDSetting::Any),
+      SramEccSetting(TargetIDSetting::Any) {
   if (!STI.getFeatureBits().test(FeatureSupportsXNACK))
     XnackSetting = TargetIDSetting::Unsupported;
   if (!STI.getFeatureBits().test(FeatureSupportsSRAMECC))
     SramEccSetting = TargetIDSetting::Unsupported;
 }
 
 void AMDGPUTargetID::setTargetIDFromFeaturesString(StringRef FS) {
   // Check if xnack or sramecc is explicitly enabled or disabled.  In the
void AMDGPUTargetID::setTargetIDFromTargetIDStream(StringRef TargetID) {
   for (const auto &FeatureString : TargetIDSplit) {
     if (FeatureString.startswith("xnack"))
       XnackSetting = getTargetIDSettingFromFeatureString(FeatureString);
     if (FeatureString.startswith("sramecc"))
       SramEccSetting = getTargetIDSettingFromFeatureString(FeatureString);
   }
 }
 
-void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream) {
-  auto TargetTriple = STI->getTargetTriple();
-  auto Version = getIsaVersion(STI->getCPU());
+std::string AMDGPUTargetID::toString() const {
+  std::string StringRep = "";
+  raw_string_ostream StreamRep(StringRep);
+
+  auto TargetTriple = STI.getTargetTriple();
+  auto Version = getIsaVersion(STI.getCPU());
 
-  Stream << TargetTriple.getArchName() << '-'
+  StreamRep << TargetTriple.getArchName() << '-'
             << TargetTriple.getVendorName() << '-'
             << TargetTriple.getOSName() << '-'
-         << TargetTriple.getEnvironmentName() << '-'
-         << "gfx"
-         << Version.Major
-         << Version.Minor
-         << Version.Stepping;
-
-  if (hasXNACK(*STI))
-    Stream << "+xnack";
-  if (hasSRAMECC(*STI))
-    Stream << "+sramecc";
+            << TargetTriple.getEnvironmentName() << '-';
+
+  std::string Processor = "";
+  // TODO: Following else statement is present here because we used various
+  // alias names for GPUs up until GFX9 (e.g. 'fiji' is same as 'gfx803').
+  // Remove once all aliases are removed from GCNProcessors.td.
+  if (Version.Major >= 9)
+    Processor = STI.getCPU().str();
+  else
+    Processor = (Twine("gfx") + Twine(Version.Major) + Twine(Version.Minor) +
+                 Twine(Version.Stepping))
+                    .str();
+
+  std::string Features = "";
+  if (const auto &&HsaAbiVersion = getHsaAbiVersion(&STI)) {
+    switch (HsaAbiVersion.getValue()) {
+    case ELF::ELFABIVERSION_AMDGPU_HSA_V2:
+      // Code object V2 only supported specific processors and had fixed
+      // settings for the XNACK.
+      if (Processor == "gfx600") {
+      } else if (Processor == "gfx601") {
+      } else if (Processor == "gfx602") {
+      } else if (Processor == "gfx700") {
+      } else if (Processor == "gfx701") {
+      } else if (Processor == "gfx702") {
+      } else if (Processor == "gfx703") {
+      } else if (Processor == "gfx704") {
+      } else if (Processor == "gfx705") {
+      } else if (Processor == "gfx801") {
+        if (!isXnackOnOrAny())
+          report_fatal_error(
+              "AMD GPU code object V2 does not support processor " + Processor +
+              " without XNACK");
+      } else if (Processor == "gfx802") {
+      } else if (Processor == "gfx803") {
+      } else if (Processor == "gfx805") {
+      } else if (Processor == "gfx810") {
+        if (!isXnackOnOrAny())
+          report_fatal_error(
+              "AMD GPU code object V2 does not support processor " + Processor +
+              " without XNACK");
+      } else if (Processor == "gfx900") {
+        if (isXnackOnOrAny())
+          Processor = "gfx901";
+      } else if (Processor == "gfx902") {
+        if (isXnackOnOrAny())
+          Processor = "gfx903";
+      } else if (Processor == "gfx904") {
+        if (isXnackOnOrAny())
+          Processor = "gfx905";
+      } else if (Processor == "gfx906") {
+        if (isXnackOnOrAny())
+          Processor = "gfx907";
+      } else {
+        report_fatal_error(
+            "AMD GPU code object V2 does not support processor " + Processor);
+      }
+      break;
+    case ELF::ELFABIVERSION_AMDGPU_HSA_V3:
+      // xnack.
+      if (isXnackOnOrAny())
+        Features += "+xnack";
+      // In code object v2 and v3, "sramecc" feature was spelled with a
+      // hyphen ("sram-ecc").
+      if (isSramEccOnOrAny())
+        Features += "+sram-ecc";
+      break;
+    case ELF::ELFABIVERSION_AMDGPU_HSA_V4:
+      // sramecc.
+      if (getSramEccSetting() == TargetIDSetting::Off)
+        Features += ":sramecc-";
+      else if (getSramEccSetting() == TargetIDSetting::On)
+        Features += ":sramecc+";
+      // xnack.
+      if (getXnackSetting() == TargetIDSetting::Off)
+        Features += ":xnack-";
+      else if (getXnackSetting() == TargetIDSetting::On)
+        Features += ":xnack+";
+      break;
+    default:
+      break;
+    }
+  }
+
+  StreamRep << Processor << Features;
 
-  Stream.flush();
+  StreamRep.flush();
+  return StringRep;
 }
 
 unsigned getWavefrontSize(const MCSubtargetInfo *STI) {
   if (STI->getFeatureBits().test(FeatureWavefrontSize16))
     return 16;
   if (STI->getFeatureBits().test(FeatureWavefrontSize32))
     return 32;
 

llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.h

public:
 
   // Set PAL metadata from YAML text.
   bool setFromString(StringRef S);
 
   // Get .note record vendor name of metadata blob to be emitted.
   const char *getVendor() const;
 
   // Get .note record type of metadata blob to be emitted:
-  // ELF::NT_AMD_AMDGPU_PAL_METADATA (legacy key=val format), or
+  // ELF::NT_AMD_PAL_METADATA (legacy key=val format), or
   // ELF::NT_AMDGPU_METADATA (MsgPack format), or
   // 0 (no PAL metadata).
   unsigned getType() const;
 
   // Emit the accumulated PAL metadata as a binary blob.
   // This is called from AMDGPUTargetELFStreamer::Finish().
   void toBlob(unsigned Type, std::string &S);
 

llvm/lib/Target/AMDGPU/Utils/AMDGPUPALMetadata.cpp

if (NamedMD && NamedMD->getNumOperands()) {
     BlobType = ELF::NT_AMDGPU_METADATA;
     auto MDN = dyn_cast<MDTuple>(NamedMD->getOperand(0));
     if (MDN && MDN->getNumOperands()) {
       if (auto MDS = dyn_cast<MDString>(MDN->getOperand(0)))
         setFromMsgPackBlob(MDS->getString());
     }
     return;
   }
-  BlobType = ELF::NT_AMD_AMDGPU_PAL_METADATA;
+  BlobType = ELF::NT_AMD_PAL_METADATA;
   NamedMD = M.getNamedMetadata("amdgpu.pal.metadata");
   if (!NamedMD || !NamedMD->getNumOperands()) {
     // Emit msgpack metadata by default
     BlobType = ELF::NT_AMDGPU_METADATA;
     return;
   }
   // This is the old reg=value pair format for metadata. It is a NamedMD
   // containing an MDTuple containing a number of MDNodes each of which is an
void AMDGPUPALMetadata::readFromIR(Module &M) {
   }
 }
 
 // Set PAL metadata from a binary blob from the applicable .note record.
 // Returns false if bad format.  Blob must remain valid for the lifetime of the
 // Metadata.
 bool AMDGPUPALMetadata::setFromBlob(unsigned Type, StringRef Blob) {
   BlobType = Type;
-  if (Type == ELF::NT_AMD_AMDGPU_PAL_METADATA)
+  if (Type == ELF::NT_AMD_PAL_METADATA)
     return setFromLegacyBlob(Blob);
   return setFromMsgPackBlob(Blob);
 }
 
 // Set PAL metadata from legacy (array of key=value pairs) blob.
 bool AMDGPUPALMetadata::setFromLegacyBlob(StringRef Blob) {
   auto Data = reinterpret_cast<const uint32_t *>(Blob.data());
   for (unsigned I = 0; I != Blob.size() / sizeof(uint32_t) / 2; ++I)
void AMDGPUPALMetadata::toString(std::string &String) {
   // Restore original registers map.
   RegsObj = OrigRegs;
 }
 
 // Convert the accumulated PAL metadata into a binary blob for writing as
 // a .note record of the specified AMD type. Returns an empty blob if
 // there is no PAL metadata,
 void AMDGPUPALMetadata::toBlob(unsigned Type, std::string &Blob) {
-  if (Type == ELF::NT_AMD_AMDGPU_PAL_METADATA)
+  if (Type == ELF::NT_AMD_PAL_METADATA)
     toLegacyBlob(Blob);
   else if (Type)
     toMsgPackBlob(Blob);
 }
 
 void AMDGPUPALMetadata::toLegacyBlob(std::string &Blob) {
   Blob.clear();
   auto Registers = getRegisters();

 }
 
 // Get .note record vendor name of metadata blob to be emitted.
 const char *AMDGPUPALMetadata::getVendor() const {
   return isLegacy() ? ElfNote::NoteNameV2 : ElfNote::NoteNameV3;
 }
 
 // Get .note record type of metadata blob to be emitted:
-// ELF::NT_AMD_AMDGPU_PAL_METADATA (legacy key=val format), or
+// ELF::NT_AMD_PAL_METADATA (legacy key=val format), or
 // ELF::NT_AMDGPU_METADATA (MsgPack format), or
 // 0 (no PAL metadata).
 unsigned AMDGPUPALMetadata::getType() const {
   return BlobType;
 }
 
 // Return whether the blob type is legacy PAL metadata.
 bool AMDGPUPALMetadata::isLegacy() const {
-  return BlobType == ELF::NT_AMD_AMDGPU_PAL_METADATA;
+  return BlobType == ELF::NT_AMD_PAL_METADATA;
 }
 
 // Set legacy PAL metadata format.
 void AMDGPUPALMetadata::setLegacy() {
-  BlobType = ELF::NT_AMD_AMDGPU_PAL_METADATA;
+  BlobType = ELF::NT_AMD_PAL_METADATA;
 }
 
 // Erase all PAL metadata.
 void AMDGPUPALMetadata::reset() {
   MsgPackDoc.clear();
   Registers = MsgPackDoc.getEmptyNode();
   HwStages = MsgPackDoc.getEmptyNode();
 }

llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-non-entry-func.ll

 ; GFX8-NEXT:    ds_write_b32 v0, v0
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: func_use_lds_global:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
-; GFX9-NEXT:    s_mov_b64 s[0:1], s[4:5]
 ; GFX9-NEXT:    s_trap 2
 ; GFX9-NEXT:    ds_write_b32 v0, v0
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
   store float 0.0, float addrspace(3)* @lds, align 4
   ret void
 }
 
 ; ERR: warning: <unknown>:0:0: in function func_use_lds_global_constexpr_cast void (): local memory global used by non-kernel function
 define void @func_use_lds_global_constexpr_cast() {
 ; GFX8-LABEL: func_use_lds_global_constexpr_cast:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX8-NEXT:    s_mov_b64 s[0:1], s[4:5]
 ; GFX8-NEXT:    s_trap 2
 ; GFX8-NEXT:    flat_store_dword v[0:1], v0
 ; GFX8-NEXT:    s_waitcnt vmcnt(0)
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: func_use_lds_global_constexpr_cast:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT:    s_mov_b64 s[0:1], s[4:5]
 ; GFX9-NEXT:    s_trap 2
 ; GFX9-NEXT:    global_store_dword v[0:1], v0, off
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
   store i32 ptrtoint (float addrspace(3)* @lds to i32), i32 addrspace(1)* undef, align 4
   ret void
 }

llvm/test/CodeGen/AMDGPU/and.ll

 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global,-xnack -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=FUNC %s
 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
 
 declare i32 @llvm.amdgcn.workitem.id.x() #0
 
 ; FUNC-LABEL: {{^}}test2:
 ; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 

llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size-v3.ll

-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck --check-prefix=CHECK %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -amdgpu-verify-hsa-metadata -filetype=obj -o /dev/null < %s 2>&1 | FileCheck --check-prefix=PARSER %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 --amdhsa-code-object-version=3 < %s | FileCheck --check-prefix=CHECK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 --amdhsa-code-object-version=3 -amdgpu-verify-hsa-metadata -filetype=obj -o /dev/null < %s 2>&1 | FileCheck --check-prefix=PARSER %s
 
 ; CHECK-LABEL: {{^}}min_64_max_64:
 ; CHECK: SGPRBlocks: 0
 ; CHECK: VGPRBlocks: 0
 ; CHECK: NumSGPRsForWavesPerEU: 1
 ; CHECK: NumVGPRsForWavesPerEU: 1
 define amdgpu_kernel void @min_64_max_64() #0 {
 entry:

llvm/test/CodeGen/AMDGPU/attr-amdgpu-flat-work-group-size.ll

-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck --check-prefix=CHECK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 --amdhsa-code-object-version=2 < %s | FileCheck --check-prefix=CHECK %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 --amdhsa-code-object-version=2 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=HSAMD %s
 
 ; CHECK-LABEL: {{^}}min_64_max_64:
 ; CHECK: SGPRBlocks: 0
 ; CHECK: VGPRBlocks: 0
 ; CHECK: NumSGPRsForWavesPerEU: 1
 ; CHECK: NumVGPRsForWavesPerEU: 1
 define amdgpu_kernel void @min_64_max_64() #0 {
define amdgpu_kernel void @min_1024_max_1024() #3 {
   store volatile float %val38, float addrspace(1)* @var
   store volatile float %val39, float addrspace(1)* @var
   store volatile float %val40, float addrspace(1)* @var
 
   ret void
 }
 attributes #3 = {"amdgpu-flat-work-group-size"="1024,1024"}
 
-; HSAMD: NT_AMD_AMDGPU_HSA_METADATA (HSA Metadata)
+; HSAMD: NT_AMD_HSA_METADATA (AMD HSA Metadata)
 ; HSAMD: Version: [ 1, 0 ]
 ; HSAMD: Kernels:
 ; HSAMD: - Name:                 min_64_max_64
 ; HSAMD:   MaxFlatWorkGroupSize: 64
 ; HSAMD: - Name:                 min_64_max_128
 ; HSAMD:   MaxFlatWorkGroupSize: 128
 ; HSAMD: - Name:                 min_128_max_128
 ; HSAMD:   MaxFlatWorkGroupSize: 128
 ; HSAMD: - Name:                 min_1024_max_1024
 ; HSAMD:   MaxFlatWorkGroupSize: 1024

llvm/test/CodeGen/AMDGPU/break-smem-soft-clauses.mir

 # RUN: llc -march=amdgcn -mcpu=carrizo -verify-machineinstrs -run-pass  post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN,XNACK %s
-# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass  post-RA-hazard-rec %s -o - | FileCheck --check-prefix=GCN %s
+# RUN: llc -march=amdgcn -mcpu=fiji -mattr=-xnack -verify-machineinstrs -run-pass  post-RA-hazard-rec %s -o - | FileCheck -check-prefixes=GCN %s
 
 ---
 # Trivial clause at beginning of program
 name: trivial_smem_clause_load_smrd4_x1
 
 body: |
   bb.0:
     ; GCN-LABEL: name: trivial_smem_clause_load_smrd4_x1

llvm/test/CodeGen/AMDGPU/cluster-flat-loads-postra.mir

-# RUN: llc -march=amdgcn -mcpu=tonga -run-pass post-RA-sched -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
+# RUN: llc -march=amdgcn -mcpu=tonga -mattr=-xnack -run-pass post-RA-sched -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s
 
 # GCN:      FLAT_LOAD_DWORD
 # GCN-NEXT: FLAT_LOAD_DWORD
 # GCN:      FLAT_STORE_DWORD
 # GCN-NEXT: FLAT_STORE_DWORD
 
 ---
 name:            cluster_loads_post_ra

llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx600 < %s | FileCheck --check-prefixes=V3-GFX600 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=tahiti < %s | FileCheck --check-prefixes=V3-GFX600 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx601 < %s | FileCheck --check-prefixes=V3-GFX601 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=pitcairn < %s | FileCheck --check-prefixes=V3-GFX601 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=verde < %s | FileCheck --check-prefixes=V3-GFX601 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx602 < %s | FileCheck --check-prefixes=V3-GFX602 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=hainan < %s | FileCheck --check-prefixes=V3-GFX602 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=oland < %s | FileCheck --check-prefixes=V3-GFX602 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx700 < %s | FileCheck --check-prefixes=V3-GFX700 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=kaveri < %s | FileCheck --check-prefixes=V3-GFX700 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx701 < %s | FileCheck --check-prefixes=V3-GFX701 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=hawaii < %s | FileCheck --check-prefixes=V3-GFX701 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx702 < %s | FileCheck --check-prefixes=V3-GFX702 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx703 < %s | FileCheck --check-prefixes=V3-GFX703 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=kabini < %s | FileCheck --check-prefixes=V3-GFX703 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=mullins < %s | FileCheck --check-prefixes=V3-GFX703 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx704 < %s | FileCheck --check-prefixes=V3-GFX704 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=bonaire < %s | FileCheck --check-prefixes=V3-GFX704 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx705 < %s | FileCheck --check-prefixes=V3-GFX705 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx801 < %s | FileCheck --check-prefixes=V3-GFX801-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx801 -mattr=-xnack < %s | FileCheck --check-prefixes=V3-GFX801-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx801 -mattr=+xnack < %s | FileCheck --check-prefixes=V3-GFX801-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=carrizo < %s | FileCheck --check-prefixes=V3-GFX801-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=carrizo -mattr=-xnack < %s | FileCheck --check-prefixes=V3-GFX801-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=carrizo -mattr=+xnack < %s | FileCheck --check-prefixes=V3-GFX801-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx802 < %s | FileCheck --check-prefixes=V3-GFX802 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=iceland < %s | FileCheck --check-prefixes=V3-GFX802 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=tonga < %s | FileCheck --check-prefixes=V3-GFX802 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx803 < %s | FileCheck --check-prefixes=V3-GFX803 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=fiji < %s | FileCheck --check-prefixes=V3-GFX803 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=polaris10 < %s | FileCheck --check-prefixes=V3-GFX803 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=polaris11 < %s | FileCheck --check-prefixes=V3-GFX803 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx805 < %s | FileCheck --check-prefixes=V3-GFX805 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=tongapro < %s | FileCheck --check-prefixes=V3-GFX805 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx810 < %s | FileCheck --check-prefixes=V3-GFX810-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx810 -mattr=-xnack < %s | FileCheck --check-prefixes=V3-GFX810-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx810 -mattr=+xnack < %s | FileCheck --check-prefixes=V3-GFX810-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=stoney < %s | FileCheck --check-prefixes=V3-GFX810-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=stoney -mattr=-xnack < %s | FileCheck --check-prefixes=V3-GFX810-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=stoney -mattr=+xnack < %s | FileCheck --check-prefixes=V3-GFX810-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx900 < %s | FileCheck --check-prefixes=V3-GFX900-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx900 -mattr=-xnack < %s | FileCheck --check-prefixes=V3-GFX900-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx900 -mattr=+xnack < %s | FileCheck --check-prefixes=V3-GFX900-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx902 < %s | FileCheck --check-prefixes=V3-GFX902-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx902 -mattr=-xnack < %s | FileCheck --check-prefixes=V3-GFX902-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx902 -mattr=+xnack < %s | FileCheck --check-prefixes=V3-GFX902-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx904 < %s | FileCheck --check-prefixes=V3-GFX904-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx904 -mattr=-xnack < %s | FileCheck --check-prefixes=V3-GFX904-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx904 -mattr=+xnack < %s | FileCheck --check-prefixes=V3-GFX904-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx906 < %s | FileCheck --check-prefixes=V3-GFX906-SRAMECC-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx906 -mattr=-sramecc < %s | FileCheck --check-prefixes=V3-GFX906-NOSRAMECC-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx906 -mattr=+sramecc < %s | FileCheck --check-prefixes=V3-GFX906-SRAMECC-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx906 -mattr=-xnack < %s | FileCheck --check-prefixes=V3-GFX906-SRAMECC-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx906 -mattr=+xnack < %s | FileCheck --check-prefixes=V3-GFX906-SRAMECC-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx906 -mattr=-sramecc,-xnack < %s | FileCheck --check-prefixes=V3-GFX906-NOSRAMECC-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx906 -mattr=+sramecc,-xnack < %s | FileCheck --check-prefixes=V3-GFX906-SRAMECC-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx906 -mattr=-sramecc,+xnack < %s | FileCheck --check-prefixes=V3-GFX906-NOSRAMECC-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx906 -mattr=+sramecc,+xnack < %s | FileCheck --check-prefixes=V3-GFX906-SRAMECC-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx908 < %s | FileCheck --check-prefixes=V3-GFX908-SRAMECC-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx908 -mattr=-sramecc < %s | FileCheck --check-prefixes=V3-GFX908-NOSRAMECC-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx908 -mattr=+sramecc < %s | FileCheck --check-prefixes=V3-GFX908-SRAMECC-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx908 -mattr=-xnack < %s | FileCheck --check-prefixes=V3-GFX908-SRAMECC-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx908 -mattr=+xnack < %s | FileCheck --check-prefixes=V3-GFX908-SRAMECC-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx908 -mattr=-sramecc,-xnack < %s | FileCheck --check-prefixes=V3-GFX908-NOSRAMECC-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx908 -mattr=+sramecc,-xnack < %s | FileCheck --check-prefixes=V3-GFX908-SRAMECC-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx908 -mattr=-sramecc,+xnack < %s | FileCheck --check-prefixes=V3-GFX908-NOSRAMECC-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx908 -mattr=+sramecc,+xnack < %s | FileCheck --check-prefixes=V3-GFX908-SRAMECC-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx909 < %s | FileCheck --check-prefixes=V3-GFX909-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx909 -mattr=-xnack < %s | FileCheck --check-prefixes=V3-GFX909-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx909 -mattr=+xnack < %s | FileCheck --check-prefixes=V3-GFX909-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx90c < %s | FileCheck --check-prefixes=V3-GFX90C-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx90c -mattr=-xnack < %s | FileCheck --check-prefixes=V3-GFX90C-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx90c -mattr=+xnack < %s | FileCheck --check-prefixes=V3-GFX90C-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx1010 < %s | FileCheck --check-prefixes=V3-GFX1010-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx1010 -mattr=-xnack < %s | FileCheck --check-prefixes=V3-GFX1010-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx1010 -mattr=+xnack < %s | FileCheck --check-prefixes=V3-GFX1010-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx1011 < %s | FileCheck --check-prefixes=V3-GFX1011-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx1011 -mattr=-xnack < %s | FileCheck --check-prefixes=V3-GFX1011-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx1011 -mattr=+xnack < %s | FileCheck --check-prefixes=V3-GFX1011-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx1012 < %s | FileCheck --check-prefixes=V3-GFX1012-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx1012 -mattr=-xnack < %s | FileCheck --check-prefixes=V3-GFX1012-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx1012 -mattr=+xnack < %s | FileCheck --check-prefixes=V3-GFX1012-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx1030 < %s | FileCheck --check-prefixes=V3-GFX1030 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx1031 < %s | FileCheck --check-prefixes=V3-GFX1031 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx1032 < %s | FileCheck --check-prefixes=V3-GFX1032 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx1033 < %s | FileCheck --check-prefixes=V3-GFX1033 %s
+
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx600 < %s | FileCheck --check-prefixes=GFX600 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tahiti < %s | FileCheck --check-prefixes=GFX600 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx601 < %s | FileCheck --check-prefixes=GFX601 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=pitcairn < %s | FileCheck --check-prefixes=GFX601 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=verde < %s | FileCheck --check-prefixes=GFX601 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx602 < %s | FileCheck --check-prefixes=GFX602 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hainan < %s | FileCheck --check-prefixes=GFX602 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=oland < %s | FileCheck --check-prefixes=GFX602 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 < %s | FileCheck --check-prefixes=GFX700 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri < %s | FileCheck --check-prefixes=GFX700 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx701 < %s | FileCheck --check-prefixes=GFX701 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck --check-prefixes=GFX701 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx702 < %s | FileCheck --check-prefixes=GFX702 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx703 < %s | FileCheck --check-prefixes=GFX703 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kabini < %s | FileCheck --check-prefixes=GFX703 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=mullins < %s | FileCheck --check-prefixes=GFX703 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx704 < %s | FileCheck --check-prefixes=GFX704 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=bonaire < %s | FileCheck --check-prefixes=GFX704 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx705 < %s | FileCheck --check-prefixes=GFX705 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=gfx801 < %s | FileCheck --check-prefixes=GFX801 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -mcpu=carrizo < %s | FileCheck --check-prefixes=GFX801 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx801 < %s | FileCheck --check-prefixes=GFX801 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx801 -mattr=-xnack < %s | FileCheck --check-prefixes=GFX801-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx801 -mattr=+xnack < %s | FileCheck --check-prefixes=GFX801-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=carrizo < %s | FileCheck --check-prefixes=GFX801 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=carrizo -mattr=-xnack < %s | FileCheck --check-prefixes=GFX801-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=carrizo -mattr=+xnack < %s | FileCheck --check-prefixes=GFX801-XNACK %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 < %s | FileCheck --check-prefixes=GFX802 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=iceland < %s | FileCheck --check-prefixes=GFX802 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga < %s | FileCheck --check-prefixes=GFX802 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck --check-prefixes=GFX803 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck --check-prefixes=GFX803 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=polaris10 < %s | FileCheck --check-prefixes=GFX803 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=polaris11 < %s | FileCheck --check-prefixes=GFX803 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx805 < %s | FileCheck --check-prefixes=GFX805 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tongapro < %s | FileCheck --check-prefixes=GFX805 %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 < %s | FileCheck --check-prefixes=GFX810 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 -mattr=-xnack < %s | FileCheck --check-prefixes=GFX810-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx810 -mattr=+xnack < %s | FileCheck --check-prefixes=GFX810-XNACK %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=stoney < %s | FileCheck --check-prefixes=GFX810 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=stoney -mattr=-xnack < %s | FileCheck --check-prefixes=GFX810-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=stoney -mattr=+xnack < %s | FileCheck --check-prefixes=GFX810-XNACK %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefixes=GFX900 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-xnack < %s | FileCheck --check-prefixes=GFX900-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+xnack < %s | FileCheck --check-prefixes=GFX900-XNACK %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx902 < %s | FileCheck --check-prefixes=GFX902 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx902 -mattr=-xnack < %s | FileCheck --check-prefixes=GFX902-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx902 -mattr=+xnack < %s | FileCheck --check-prefixes=GFX902-XNACK %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx904 < %s | FileCheck --check-prefixes=GFX904 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=-xnack < %s | FileCheck --check-prefixes=GFX904-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=+xnack < %s | FileCheck --check-prefixes=GFX904-XNACK %s
 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 < %s | FileCheck --check-prefixes=GFX906 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -mattr=-sramecc < %s | FileCheck --check-prefixes=GFX906-NOSRAMECC %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -mattr=+sramecc < %s | FileCheck --check-prefixes=GFX906-SRAMECC %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -mattr=-xnack < %s | FileCheck --check-prefixes=GFX906-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -mattr=+xnack < %s | FileCheck --check-prefixes=GFX906-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -mattr=-sramecc,-xnack < %s | FileCheck --check-prefixes=GFX906-NOSRAMECC-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -mattr=+sramecc,-xnack < %s | FileCheck --check-prefixes=GFX906-SRAMECC-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -mattr=-sramecc,+xnack < %s | FileCheck --check-prefixes=GFX906-NOSRAMECC-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -mattr=+sramecc,+xnack < %s | FileCheck --check-prefixes=GFX906-SRAMECC-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck --check-prefixes=GFX908 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-sramecc < %s | FileCheck --check-prefixes=GFX908-NOSRAMECC %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=+sramecc < %s | FileCheck --check-prefixes=GFX908-SRAMECC %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack < %s | FileCheck --check-prefixes=GFX908-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=+xnack < %s | FileCheck --check-prefixes=GFX908-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-sramecc,-xnack < %s | FileCheck --check-prefixes=GFX908-NOSRAMECC-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=+sramecc,-xnack < %s | FileCheck --check-prefixes=GFX908-SRAMECC-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-sramecc,+xnack < %s | FileCheck --check-prefixes=GFX908-NOSRAMECC-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=+sramecc,+xnack < %s | FileCheck --check-prefixes=GFX908-SRAMECC-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx909 < %s | FileCheck --check-prefixes=GFX909 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx909 -mattr=-xnack < %s | FileCheck --check-prefixes=GFX909-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx909 -mattr=+xnack < %s | FileCheck --check-prefixes=GFX909-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90c < %s | FileCheck --check-prefixes=GFX90C %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90c -mattr=-xnack < %s | FileCheck --check-prefixes=GFX90C-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90c -mattr=+xnack < %s | FileCheck --check-prefixes=GFX90C-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck --check-prefixes=GFX1010 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=-xnack < %s | FileCheck --check-prefixes=GFX1010-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+xnack < %s | FileCheck --check-prefixes=GFX1010-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1011 < %s | FileCheck --check-prefixes=GFX1011 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1011 -mattr=-xnack < %s | FileCheck --check-prefixes=GFX1011-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1011 -mattr=+xnack < %s | FileCheck --check-prefixes=GFX1011-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1012 < %s | FileCheck --check-prefixes=GFX1012 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1012 -mattr=-xnack < %s | FileCheck --check-prefixes=GFX1012-NOXNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1012 -mattr=+xnack < %s | FileCheck --check-prefixes=GFX1012-XNACK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck --check-prefixes=GFX1030 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 < %s | FileCheck --check-prefixes=GFX1031 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1032 < %s | FileCheck --check-prefixes=GFX1032 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1033 < %s | FileCheck --check-prefixes=GFX1033 %s
 
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=+xnack < %s | FileCheck --check-prefixes=XNACK-GFX900 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx902 -mattr=-xnack < %s | FileCheck --check-prefixes=NO-XNACK-GFX902 %s
-
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=+sramecc < %s | FileCheck --check-prefixes=SRAM-ECC-GFX904 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -mattr=+sramecc < %s | FileCheck --check-prefixes=SRAM-ECC-GFX906 %s
-
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=+sramecc,+xnack < %s | FileCheck --check-prefixes=SRAM-ECC-XNACK-GFX904 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -mattr=+sramecc,+xnack < %s | FileCheck --check-prefixes=SRAM-ECC-XNACK-GFX906 %s
-
-; FIXME: With the default attributes these directives are not accurate for
-; xnack and sramecc. Subsequent Target-ID patches will address this.
+; V3-GFX600: .amdgcn_target "amdgcn-amd-amdhsa--gfx600"
+; V3-GFX601: .amdgcn_target "amdgcn-amd-amdhsa--gfx601"
+; V3-GFX602: .amdgcn_target "amdgcn-amd-amdhsa--gfx602"
+; V3-GFX700: .amdgcn_target "amdgcn-amd-amdhsa--gfx700"
+; V3-GFX701: .amdgcn_target "amdgcn-amd-amdhsa--gfx701"
+; V3-GFX702: .amdgcn_target "amdgcn-amd-amdhsa--gfx702"
+; V3-GFX703: .amdgcn_target "amdgcn-amd-amdhsa--gfx703"
+; V3-GFX704: .amdgcn_target "amdgcn-amd-amdhsa--gfx704"
+; V3-GFX705: .amdgcn_target "amdgcn-amd-amdhsa--gfx705"
+; V3-GFX801-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx801"
+; V3-GFX801-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx801+xnack"
+; V3-GFX802: .amdgcn_target "amdgcn-amd-amdhsa--gfx802"
+; V3-GFX803: .amdgcn_target "amdgcn-amd-amdhsa--gfx803"
+; V3-GFX805: .amdgcn_target "amdgcn-amd-amdhsa--gfx805"
+; V3-GFX810-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx810"
+; V3-GFX810-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx810+xnack"
+; V3-GFX900-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx900"
+; V3-GFX900-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx900+xnack"
+; V3-GFX902-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx902"
+; V3-GFX902-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx902+xnack"
+; V3-GFX904-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx904"
+; V3-GFX904-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx904+xnack"
+; V3-GFX906-NOSRAMECC-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx906"
+; V3-GFX906-SRAMECC-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx906+sram-ecc"
+; V3-GFX906-NOSRAMECC-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx906+xnack"
+; V3-GFX906-SRAMECC-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx906+xnack+sram-ecc"
+; V3-GFX908-NOSRAMECC-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx908"
+; V3-GFX908-SRAMECC-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx908+sram-ecc"
+; V3-GFX908-NOSRAMECC-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx908+xnack"
+; V3-GFX908-SRAMECC-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx908+xnack+sram-ecc"
+; V3-GFX909-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx909"
+; V3-GFX909-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx909+xnack"
+; V3-GFX90C-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx90c"
+; V3-GFX90C-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx90c+xnack"
+; V3-GFX1010-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx1010"
+; V3-GFX1010-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx1010+xnack"
+; V3-GFX1011-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx1011"
+; V3-GFX1011-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx1011+xnack"
+; V3-GFX1012-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx1012"
+; V3-GFX1012-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx1012+xnack"
+; V3-GFX1030: .amdgcn_target "amdgcn-amd-amdhsa--gfx1030"
+; V3-GFX1031: .amdgcn_target "amdgcn-amd-amdhsa--gfx1031"
+; V3-GFX1032: .amdgcn_target "amdgcn-amd-amdhsa--gfx1032"
+; V3-GFX1033: .amdgcn_target "amdgcn-amd-amdhsa--gfx1033"
 
 ; GFX600: .amdgcn_target "amdgcn-amd-amdhsa--gfx600"
 ; GFX601: .amdgcn_target "amdgcn-amd-amdhsa--gfx601"
 ; GFX602: .amdgcn_target "amdgcn-amd-amdhsa--gfx602"
 ; GFX700: .amdgcn_target "amdgcn-amd-amdhsa--gfx700"
 ; GFX701: .amdgcn_target "amdgcn-amd-amdhsa--gfx701"
 ; GFX702: .amdgcn_target "amdgcn-amd-amdhsa--gfx702"
 ; GFX703: .amdgcn_target "amdgcn-amd-amdhsa--gfx703"
 ; GFX704: .amdgcn_target "amdgcn-amd-amdhsa--gfx704"
 ; GFX705: .amdgcn_target "amdgcn-amd-amdhsa--gfx705"
 ; GFX801: .amdgcn_target "amdgcn-amd-amdhsa--gfx801"
+; GFX801-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx801:xnack-"
+; GFX801-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx801:xnack+"
 ; GFX802: .amdgcn_target "amdgcn-amd-amdhsa--gfx802"
 ; GFX803: .amdgcn_target "amdgcn-amd-amdhsa--gfx803"
 ; GFX805: .amdgcn_target "amdgcn-amd-amdhsa--gfx805"
 ; GFX810: .amdgcn_target "amdgcn-amd-amdhsa--gfx810"
+; GFX810-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx810:xnack-"
+; GFX810-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx810:xnack+"
 ; GFX900: .amdgcn_target "amdgcn-amd-amdhsa--gfx900"
+; GFX900-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack-"
+; GFX900-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx900:xnack+"
 ; GFX902: .amdgcn_target "amdgcn-amd-amdhsa--gfx902"
+; GFX902-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx902:xnack-"
+; GFX902-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx902:xnack+"
 ; GFX904: .amdgcn_target "amdgcn-amd-amdhsa--gfx904"
+; GFX904-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx904:xnack-"
+; GFX904-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx904:xnack+"
 ; GFX906: .amdgcn_target "amdgcn-amd-amdhsa--gfx906"
-
-; XNACK-GFX900: .amdgcn_target "amdgcn-amd-amdhsa--gfx900+xnack"
-; NO-XNACK-GFX902: .amdgcn_target "amdgcn-amd-amdhsa--gfx902"
-
-; SRAM-ECC-GFX904: .amdgcn_target "amdgcn-amd-amdhsa--gfx904+sramecc"
-; SRAM-ECC-GFX906: "amdgcn-amd-amdhsa--gfx906+sramecc"
-
-; SRAM-ECC-XNACK-GFX904: .amdgcn_target "amdgcn-amd-amdhsa--gfx904+xnack+sramecc"
-; SRAM-ECC-XNACK-GFX906: .amdgcn_target "amdgcn-amd-amdhsa--gfx906+xnack+sramecc"
+; GFX906-NOSRAMECC: .amdgcn_target "amdgcn-amd-amdhsa--gfx906:sramecc-"
+; GFX906-SRAMECC: .amdgcn_target "amdgcn-amd-amdhsa--gfx906:sramecc+"
+; GFX906-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx906:xnack-"
+; GFX906-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx906:xnack+"
+; GFX906-NOSRAMECC-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx906:sramecc-:xnack-"
+; GFX906-SRAMECC-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx906:sramecc+:xnack-"
+; GFX906-NOSRAMECC-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx906:sramecc-:xnack+"
+; GFX906-SRAMECC-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx906:sramecc+:xnack+"
+; GFX908: .amdgcn_target "amdgcn-amd-amdhsa--gfx908"
+; GFX908-NOSRAMECC: .amdgcn_target "amdgcn-amd-amdhsa--gfx908:sramecc-"
+; GFX908-SRAMECC: .amdgcn_target "amdgcn-amd-amdhsa--gfx908:sramecc+"
+; GFX908-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx908:xnack-"
+; GFX908-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx908:xnack+"
+; GFX908-NOSRAMECC-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx908:sramecc-:xnack-"
+; GFX908-SRAMECC-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx908:sramecc+:xnack-"
+; GFX908-NOSRAMECC-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx908:sramecc-:xnack+"
+; GFX908-SRAMECC-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx908:sramecc+:xnack+"
+; GFX909: .amdgcn_target "amdgcn-amd-amdhsa--gfx909"
+; GFX909-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx909:xnack-"
+; GFX909-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx909:xnack+"
+; GFX90C: .amdgcn_target "amdgcn-amd-amdhsa--gfx90c"
+; GFX90C-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx90c:xnack-"
+; GFX90C-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx90c:xnack+"
+; GFX1010: .amdgcn_target "amdgcn-amd-amdhsa--gfx1010"
+; GFX1010-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx1010:xnack-"
+; GFX1010-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx1010:xnack+"
+; GFX1011: .amdgcn_target "amdgcn-amd-amdhsa--gfx1011"
+; GFX1011-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx1011:xnack-"
+; GFX1011-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx1011:xnack+"
+; GFX1012: .amdgcn_target "amdgcn-amd-amdhsa--gfx1012"
+; GFX1012-NOXNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx1012:xnack-"
+; GFX1012-XNACK: .amdgcn_target "amdgcn-amd-amdhsa--gfx1012:xnack+"
+; GFX1030: .amdgcn_target "amdgcn-amd-amdhsa--gfx1030"
+; GFX1031: .amdgcn_target "amdgcn-amd-amdhsa--gfx1031"
+; GFX1032: .amdgcn_target "amdgcn-amd-amdhsa--gfx1032"
+; GFX1033: .amdgcn_target "amdgcn-amd-amdhsa--gfx1033"
 
 define amdgpu_kernel void @directive_amdgcn_target() {
   ret void
 }

llvm/test/CodeGen/AMDGPU/elf-header-flags-sramecc.ll

-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx906 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NO-SRAM-ECC-GFX906 %s
+; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx906 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=SRAM-ECC-GFX906 %s
 ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx906 -mattr=-sramecc < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NO-SRAM-ECC-GFX906 %s
 ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx906 -mattr=+sramecc < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=SRAM-ECC-GFX906 %s
 ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx906 -mattr=+sramecc,+xnack < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=SRAM-ECC-XNACK-GFX906 %s
 
+; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx908 < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=SRAM-ECC-GFX908 %s
 ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx908 -mattr=+sramecc < %s | llvm-readobj -file-headers - | FileCheck --check-prefix=SRAM-ECC-GFX908 %s
 
 ; NO-SRAM-ECC-GFX906:      Flags [
+; NO-SRAM-ECC-GFX906-NEXT:   EF_AMDGPU_FEATURE_XNACK_V3   (0x100)
 ; NO-SRAM-ECC-GFX906-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX906 (0x2F)
 ; NO-SRAM-ECC-GFX906-NEXT: ]
 
 ; SRAM-ECC-GFX906:      Flags [
+; SRAM-ECC-GFX906-NEXT:   EF_AMDGPU_FEATURE_SRAMECC_V3 (0x200)
+; SRAM-ECC-GFX906-NEXT:   EF_AMDGPU_FEATURE_XNACK_V3   (0x100)
 ; SRAM-ECC-GFX906-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX906 (0x2F)
-; SRAM-ECC-GFX906-NEXT:   EF_AMDGPU_SRAM_ECC           (0x200)
 ; SRAM-ECC-GFX906-NEXT: ]
 
 ; SRAM-ECC-XNACK-GFX906:      Flags [
+; SRAM-ECC-XNACK-GFX906-NEXT:   EF_AMDGPU_FEATURE_SRAMECC_V3 (0x200)
+; SRAM-ECC-XNACK-GFX906-NEXT:   EF_AMDGPU_FEATURE_XNACK_V3   (0x100)
 ; SRAM-ECC-XNACK-GFX906-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX906 (0x2F)
-; SRAM-ECC-XNACK-GFX906-NEXT:   EF_AMDGPU_SRAM_ECC           (0x200)
-; SRAM-ECC-XNACK-GFX906-NEXT:   EF_AMDGPU_XNACK              (0x100)
 ; SRAM-ECC-XNACK-GFX906-NEXT: ]
 
-; SRAM-ECC-GFX908: Flags [ (0x230)
+; SRAM-ECC-GFX908: Flags [
+; SRAM-ECC-GFX908:    EF_AMDGPU_FEATURE_SRAMECC_V3 (0x200)
 ; SRAM-ECC-GFX908:    EF_AMDGPU_MACH_AMDGCN_GFX908 (0x30)
-; SRAM-ECC-GFX908:    EF_AMDGPU_SRAM_ECC (0x200)
 ; SRAM-ECC-GFX908:  ]
 
 define amdgpu_kernel void @elf_header() {
   ret void
 }

llvm/test/CodeGen/AMDGPU/elf-header-flags-xnack.ll

-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx801 -mattr=-xnack < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NO-XNACK-GFX801 %s
-; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx802 -mattr=+xnack < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=XNACK-GFX802 %s
+; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=XNACK-GFX801 %s
+; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx801 -mattr=+xnack < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=XNACK-GFX801 %s
+; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx802 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NO-XNACK-GFX802 %s
+; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx802 -mattr=-xnack < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NO-XNACK-GFX802 %s
 
-; NO-XNACK-GFX801:      Flags [
-; NO-XNACK-GFX801-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX801 (0x28)
-; NO-XNACK-GFX801-NEXT: ]
+; XNACK-GFX801:      Flags [
+; XNACK-GFX801-NEXT:   EF_AMDGPU_FEATURE_XNACK_V3   (0x100)
+; XNACK-GFX801-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX801 (0x28)
+; XNACK-GFX801-NEXT: ]
 
-; XNACK-GFX802:      Flags [
-; XNACK-GFX802-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX802 (0x29)
-; XNACK-GFX802-NEXT:   EF_AMDGPU_XNACK              (0x100)
-; XNACK-GFX802-NEXT: ]
+; NO-XNACK-GFX802:      Flags [
+; NO-XNACK-GFX802-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX802 (0x29)
+; NO-XNACK-GFX802-NEXT: ]
 
 define amdgpu_kernel void @elf_header() {
   ret void
 }

llvm/test/CodeGen/AMDGPU/elf-header-osabi.ll

 ; RUN: llc -filetype=obj -march=amdgcn -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NONE %s
 ; RUN: llc -filetype=obj -mtriple=amdgcn-amd- -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NONE %s
 ; RUN: llc -filetype=obj -mtriple=amdgcn-amd-unknown -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=NONE %s
 ; RUN: llc -filetype=obj -mtriple=amdgcn--amdhsa -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=HSA %s
 ; RUN: llc -filetype=obj -mtriple=amdgcn-amd-amdhsa -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=HSA %s
 ; RUN: llc -filetype=obj -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=HSA %s
 ; RUN: llc -filetype=obj -mtriple=amdgcn--amdpal -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=PAL %s
 ; RUN: llc -filetype=obj -mtriple=amdgcn-amd-amdpal -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=PAL %s
 ; RUN: llc -filetype=obj -mtriple=amdgcn-unknown-amdpal -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=PAL %s
 ; RUN: llc -filetype=obj -mtriple=amdgcn--mesa3d -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=MESA3D %s
 ; RUN: llc -filetype=obj -mtriple=amdgcn-amd-mesa3d -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=MESA3D %s
 ; RUN: llc -filetype=obj -mtriple=amdgcn-unknown-mesa3d -mcpu=gfx801 < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=MESA3D %s
 
 ; NONE:   OS/ABI: SystemV       (0x0)
 ; HSA:    OS/ABI: AMDGPU_HSA    (0x40)
-; HSA:    ABIVersion: 1
+; HSA:    ABIVersion: 2
 ; PAL:    OS/ABI: AMDGPU_PAL    (0x41)
 ; PAL:    ABIVersion: 0
 ; MESA3D: OS/ABI: AMDGPU_MESA3D (0x42)
-; MESA3D:    ABIVersion: 0
+; MESA3D: ABIVersion: 0
 
 define amdgpu_kernel void @elf_header() {
   ret void
 }

llvm/test/CodeGen/AMDGPU/elf-notes.ll

 
 ; OSABI-UNK-NOT: .hsa_code_object_version
 ; OSABI-UNK-NOT: .hsa_code_object_isa
 ; OSABI-UNK: .amd_amdgpu_isa "amdgcn-amd-unknown--gfx802"
 ; OSABI-UNK-NOT: .amd_amdgpu_hsa_metadata
 ; OSABI-UNK-NOT: .amd_amdgpu_pal_metadata
 
 ; OSABI-UNK-ELF-NOT: Unknown note type
-; OSABI-UNK-ELF: NT_AMD_AMDGPU_ISA (ISA Version)
-; OSABI-UNK-ELF: ISA Version:
+; OSABI-UNK-ELF: NT_AMD_HSA_ISA_NAME (AMD HSA ISA Name)
+; OSABI-UNK-ELF: AMD HSA ISA Name:
 ; OSABI-UNK-ELF: amdgcn-amd-unknown--gfx802
 ; OSABI-UNK-ELF-NOT: Unknown note type
-; OSABI-UNK-ELF-NOT: NT_AMD_AMDGPU_HSA_METADATA (HSA Metadata)
+; OSABI-UNK-ELF-NOT: NT_AMD_HSA_METADATA (AMD HSA Metadata)
 ; OSABI-UNK-ELF-NOT: Unknown note type
-; OSABI-UNK-ELF-NOT: NT_AMD_AMDGPU_PAL_METADATA (PAL Metadata)
+; OSABI-UNK-ELF-NOT: NT_AMD_PAL_METADATA (AMD PAL Metadata)
 ; OSABI-UNK-ELF-NOT: Unknown note type
 
 ; OSABI-HSA: .hsa_code_object_version
 ; OSABI-HSA: .hsa_code_object_isa
 ; OSABI-HSA: .amd_amdgpu_isa "amdgcn-amd-amdhsa--gfx802"
 ; OSABI-HSA: .amd_amdgpu_hsa_metadata
 ; OSABI-HSA-NOT: .amd_amdgpu_pal_metadata
 
-; OSABI-HSA-ELF: Unknown note type: (0x00000001)
-; OSABI-HSA-ELF: Unknown note type: (0x00000003)
-; OSABI-HSA-ELF: NT_AMD_AMDGPU_ISA (ISA Version)
-; OSABI-HSA-ELF: ISA Version:
+; OSABI-HSA-ELF: NT_AMD_HSA_CODE_OBJECT_VERSION (AMD HSA Code Object Version)
+; OSABI-HSA-ELF: NT_AMD_HSA_ISA_VERSION (AMD HSA ISA Version)
+; OSABI-HSA-ELF: NT_AMD_HSA_ISA_NAME (AMD HSA ISA Name)
+; OSABI-HSA-ELF: AMD HSA ISA Name:
 ; OSABI-HSA-ELF: amdgcn-amd-amdhsa--gfx802
-; OSABI-HSA-ELF: NT_AMD_AMDGPU_HSA_METADATA (HSA Metadata)
+; OSABI-HSA-ELF: NT_AMD_HSA_METADATA (AMD HSA Metadata)
 ; OSABI-HSA-ELF: HSA Metadata:
 ; OSABI-HSA-ELF: ---
 ; OSABI-HSA-ELF: Version: [ 1, 0 ]
 ; OSABI-HSA-ELF: Kernels:
 ; OSABI-HSA-ELF:   - Name:       elf_notes
 ; OSABI-HSA-ELF:     SymbolName: 'elf_notes@kd'
 ; OSABI-HSA-ELF:     CodeProps:
 ; OSABI-HSA-ELF:       KernargSegmentSize: 0
 ; OSABI-HSA-ELF:       GroupSegmentFixedSize: 0
 ; OSABI-HSA-ELF:       PrivateSegmentFixedSize: 0
 ; OSABI-HSA-ELF:       KernargSegmentAlign: 4
 ; OSABI-HSA-ELF:       WavefrontSize:   64
 ; OSABI-HSA-ELF:       NumSGPRs:        96
 ; OSABI-HSA-ELF: ...
-; OSABI-HSA-ELF-NOT: NT_AMD_AMDGPU_PAL_METADATA (PAL Metadata)
+; OSABI-HSA-ELF-NOT: NT_AMD_PAL_METADATA (AMD PAL Metadata)
 
 ; OSABI-PAL-NOT: .hsa_code_object_version
 ; OSABI-PAL: .hsa_code_object_isa
 ; OSABI-PAL: .amd_amdgpu_isa "amdgcn-amd-amdpal--gfx802"
 ; OSABI-PAL-NOT: .amd_amdgpu_hsa_metadata
 
-; OSABI-PAL-ELF: Unknown note type: (0x00000003)
-; OSABI-PAL-ELF: NT_AMD_AMDGPU_ISA (ISA Version)
-; OSABI-PAL-ELF: ISA Version:
+; OSABI-PAL-ELF: NT_AMD_HSA_ISA_VERSION (AMD HSA ISA Version)
+; OSABI-PAL-ELF: NT_AMD_HSA_ISA_NAME (AMD HSA ISA Name)
+; OSABI-PAL-ELF: AMD HSA ISA Name:
 ; OSABI-PAL-ELF: amdgcn-amd-amdpal--gfx802
-; OSABI-PAL-ELF-NOT: NT_AMD_AMDGPU_HSA_METADATA (HSA Metadata)
+; OSABI-PAL-ELF-NOT: NT_AMD_HSA_METADATA (AMD HSA Metadata)
 ; OSABI-PAL-ELF: NT_AMDGPU_METADATA (AMDGPU Metadata)
 ; OSABI-PAL-ELF: AMDGPU Metadata:
 ; OSABI-PAL-ELF: amdpal.pipelines:
 ; OSABI-PAL-ELF:   - .hardware_stages:
 ; OSABI-PAL-ELF:       .cs:
 ; OSABI-PAL-ELF:         .entry_point:    elf_notes
 ; OSABI-PAL-ELF:         .scratch_memory_size: 0
 ; OSABI-PAL-ELF:         .sgpr_count:     96

llvm/test/CodeGen/AMDGPU/fabs.ll

 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
+; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global,-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
 
 
 ; DAGCombiner will transform:
 ; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))
 ; unless isFabsFree returns true
 
 ; FUNC-LABEL: {{^}}s_fabs_fn_free:

llvm/test/CodeGen/AMDGPU/flat-scratch-reg.ll

 ; RUN: llc -march=amdgcn -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN %s
 ; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK -check-prefix=GCN %s
 
-; RUN: llc -march=amdgcn -mcpu=carrizo -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK  -check-prefix=GCN %s
-; RUN: llc -march=amdgcn -mcpu=stoney -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK  -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=carrizo -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefixes=VI-NOXNACK,GCN %s
+; RUN: llc -march=amdgcn -mcpu=stoney -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefixes=VI-NOXNACK,GCN %s
 
 ; RUN: llc -march=amdgcn -mcpu=carrizo -mattr=+xnack -verify-machineinstrs < %s | FileCheck -check-prefix=VI-XNACK  -check-prefix=GCN %s
 ; RUN: llc -march=amdgcn -mcpu=stoney -mattr=+xnack -verify-machineinstrs < %s | FileCheck -check-prefix=VI-XNACK  -check-prefix=GCN %s
 
-; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-CI -check-prefix=GCN %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-VI-NOXNACK -check-prefix=GCN %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 -mattr=+xnack -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-VI-XNACK -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefixes=CI,HSA-CI-V2,GCN %s
+; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 -mattr=+xnack -verify-machineinstrs < %s | FileCheck -check-prefixes=VI-XNACK,HSA-VI-XNACK-V2,GCN %s
+
+; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
+; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefixes=VI-NOXNACK,HSA-VI-NOXNACK,GCN %s
+; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=+xnack -verify-machineinstrs < %s | FileCheck -check-prefixes=VI-XNACK,HSA-VI-XNACK,GCN %s
 
 ; GCN-LABEL: {{^}}no_vcc_no_flat:
-; HSA-CI: is_xnack_enabled = 0
-; HSA-VI-NOXNACK: is_xnack_enabled = 0
-; HSA-VI-XNACK: is_xnack_enabled = 1
+
+; HSA-CI-V2: is_xnack_enabled = 0
+; HSA-VI-XNACK-V2: is_xnack_enabled = 1
+
+; NOT-HSA-CI: .amdhsa_reserve_xnack_mask
+; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
+; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
 
 ; CI: ; NumSgprs: 8
 ; VI-NOXNACK: ; NumSgprs: 8
 ; VI-XNACK: ; NumSgprs: 12
 define amdgpu_kernel void @no_vcc_no_flat() {
 entry:
   call void asm sideeffect "", "~{s7}"()
   ret void
 }
 
 ; GCN-LABEL: {{^}}vcc_no_flat:
-; HSA-CI: is_xnack_enabled = 0
-; HSA-VI-NOXNACK: is_xnack_enabled = 0
-; HSA-VI-XNACK: is_xnack_enabled = 1
+
+; HSA-CI-V2: is_xnack_enabled = 0
+; HSA-VI-XNACK-V2: is_xnack_enabled = 1
+
+; NOT-HSA-CI: .amdhsa_reserve_xnack_mask
+; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
+; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
 
 ; CI: ; NumSgprs: 10
 ; VI-NOXNACK: ; NumSgprs: 10
 ; VI-XNACK: ; NumSgprs: 12
 define amdgpu_kernel void @vcc_no_flat() {
 entry:
   call void asm sideeffect "", "~{s7},~{vcc}"()
   ret void
 }
 
 ; GCN-LABEL: {{^}}no_vcc_flat:
-; HSA-CI: is_xnack_enabled = 0
-; HSA-VI-NOXNACK: is_xnack_enabled = 0
-; HSA-VI-XNACK: is_xnack_enabled = 1
+
+; HSA-CI-V2: is_xnack_enabled = 0
+; HSA-VI-XNACK-V2: is_xnack_enabled = 1
+
+; NOT-HSA-CI: .amdhsa_reserve_xnack_mask
+; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
+; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
 
 ; CI: ; NumSgprs: 12
 ; VI-NOXNACK: ; NumSgprs: 14
 ; VI-XNACK: ; NumSgprs: 14
-; HSA-CI: ; NumSgprs: 12
-; HSA-VI-NOXNACK: ; NumSgprs: 14
-; HSA-VI-XNACK: ; NumSgprs: 14
 define amdgpu_kernel void @no_vcc_flat() {
 entry:
   call void asm sideeffect "", "~{s7},~{flat_scratch}"()
   ret void
 }
 
 ; GCN-LABEL: {{^}}vcc_flat:
-; HSA-NOXNACK: is_xnack_enabled = 0
-; HSA-XNACK: is_xnack_enabled = 1
+
+; HSA-CI-V2: is_xnack_enabled = 0
+; HSA-VI-XNACK-V2: is_xnack_enabled = 1
+
+; NOT-HSA-CI: .amdhsa_reserve_xnack_mask
+; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
+; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
 
 ; CI: ; NumSgprs: 12
 ; VI-NOXNACK: ; NumSgprs: 14
 ; VI-XNACK: ; NumSgprs: 14
-; HSA-CI: ; NumSgprs: 12
-; HSA-VI-NOXNACK: ; NumSgprs: 14
-; HSA-VI-XNACK: ; NumSgprs: 14
 define amdgpu_kernel void @vcc_flat() {
 entry:
   call void asm sideeffect "", "~{s7},~{vcc},~{flat_scratch}"()
   ret void
 }
 
 ; Make sure used SGPR count for flat_scr is correct when there is no
 ; scratch usage and implicit flat uses.
 
 ; GCN-LABEL: {{^}}use_flat_scr:
+
+; HSA-CI-V2: is_xnack_enabled = 0
+; HSA-VI-XNACK-V2: is_xnack_enabled = 1
+
+; NOT-HSA-CI: .amdhsa_reserve_xnack_mask
+; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
+; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
+
 ; CI: NumSgprs: 4
 ; VI-NOXNACK: NumSgprs: 6
 ; VI-XNACK: NumSgprs: 6
 define amdgpu_kernel void @use_flat_scr() #0 {
 entry:
   call void asm sideeffect "; clobber ", "~{flat_scratch}"()
   ret void
 }
 
 ; GCN-LABEL: {{^}}use_flat_scr_lo:
+
+; HSA-CI-V2: is_xnack_enabled = 0
+; HSA-VI-XNACK-V2: is_xnack_enabled = 1
+
+; NOT-HSA-CI: .amdhsa_reserve_xnack_mask
+; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
+; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
+
 ; CI: NumSgprs: 4
 ; VI-NOXNACK: NumSgprs: 6
 ; VI-XNACK: NumSgprs: 6
 define amdgpu_kernel void @use_flat_scr_lo() #0 {
 entry:
   call void asm sideeffect "; clobber ", "~{flat_scratch_lo}"()
   ret void
 }
 
 ; GCN-LABEL: {{^}}use_flat_scr_hi:
+
+; HSA-CI-V2: is_xnack_enabled = 0
+; HSA-VI-XNACK-V2: is_xnack_enabled = 1
+
+; NOT-HSA-CI: .amdhsa_reserve_xnack_mask
+; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
+; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
+
 ; CI: NumSgprs: 4
 ; VI-NOXNACK: NumSgprs: 6
 ; VI-XNACK: NumSgprs: 6
 define amdgpu_kernel void @use_flat_scr_hi() #0 {
 entry:
   call void asm sideeffect "; clobber ", "~{flat_scratch_hi}"()
   ret void
 }
 
 attributes #0 = { nounwind }

llvm/test/CodeGen/AMDGPU/hsa-metadata-enqueue-kernel-v3.ll

-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=3 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
 
 ; CHECK:              ---
 ; CHECK:      amdhsa.kernels:
 ; CHECK:        - .args:
 ; CHECK-NEXT:       - .name:           a
 ; CHECK-NEXT:         .offset:         0
 ; CHECK-NEXT:         .size:           1
 ; CHECK-NEXT:         .type_name:      char

llvm/test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full-v3.ll

-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 --amdhsa-code-object-version=3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=3 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 --amdhsa-code-object-version=3 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=3 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
 
 %struct.A = type { i8, float }
 %opencl.image1d_t = type opaque
 %opencl.image2d_t = type opaque
 %opencl.image3d_t = type opaque
 %opencl.queue_t = type opaque
 %opencl.pipe_t = type opaque
 %struct.B = type { i32 addrspace(1)*}

llvm/test/CodeGen/AMDGPU/hsa-metadata-hidden-args-v3.ll

-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 --amdhsa-code-object-version=3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
 
 ; CHECK:              ---
 ; CHECK:      amdhsa.kernels:
 
 ; CHECK:        - .args:
 ; CHECK-NEXT:       - .address_space:  global
 ; CHECK-NEXT:         .name:           r
 ; CHECK-NEXT:         .offset:         0

llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-absent-v3.ll

-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=3 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
 
 ; CHECK:              ---
 ; CHECK:      amdhsa.kernels:
 ; CHECK:        - .args:
 ; CHECK-NEXT:       - .name:           a
 ; CHECK-NEXT:         .offset:         0
 ; CHECK-NEXT:         .size:           1
 ; CHECK-NEXT:         .type_name:      char

llvm/test/CodeGen/AMDGPU/hsa-metadata-hostcall-present-v3.ll

-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=3 -amdgpu-dump-hsa-metadata -amdgpu-verify-hsa-metadata -filetype=obj -o - < %s 2>&1 | FileCheck --check-prefix=PARSER %s
 
 ; CHECK:              ---
 ; CHECK:      amdhsa.kernels:
 ; CHECK:        - .args:
 ; CHECK-NEXT:       - .name:           a
 ; CHECK-NEXT:         .offset:         0
 ; CHECK-NEXT:         .size:           1
 ; CHECK-NEXT:         .type_name:      char

llvm/test/CodeGen/AMDGPU/hsa-metadata-images-v3.ll

-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx802 --amdhsa-code-object-version=3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck --check-prefix=CHECK %s
 
 %opencl.image1d_t = type opaque
 %opencl.image1d_array_t = type opaque
 %opencl.image1d_buffer_t = type opaque
 %opencl.image2d_t = type opaque
 %opencl.image2d_array_t = type opaque
 %opencl.image2d_array_depth_t = type opaque
 %opencl.image2d_array_msaa_t = type opaque

llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-1-v3.ll

-; RUN: llc -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
 
 ; Make sure llc does not crash for invalid opencl version metadata.
 
 ; CHECK: ---
 ; CHECK: amdhsa.version:
 ; CHECK-NEXT: - 1
 ; CHECK-NEXT: - 0
 ; CHECK: ...
 
 !opencl.ocl.version = !{}

llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-2-v3.ll

-; RUN: llc -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
 
 ; Make sure llc does not crash for invalid opencl version metadata.
 
 ; CHECK: ---
 ; CHECK: amdhsa.version:
 ; CHECK-NEXT: - 1
 ; CHECK-NEXT: - 0
 ; CHECK: ...
 
 !opencl.ocl.version = !{!0}
 !0 = !{}

llvm/test/CodeGen/AMDGPU/hsa-metadata-invalid-ocl-version-3-v3.ll

-; RUN: llc -mtriple=amdgcn-amd-amdhsa -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa --amdhsa-code-object-version=3 -filetype=obj -o - < %s | llvm-readelf --notes - | FileCheck %s
 
 ; Make sure llc does not crash for invalid opencl version metadata.
 
 ; CHECK: ---
 ; CHECK: amdhsa.version:
 ; CHECK-NEXT: - 1
 ; CHECK-NEXT: - 0
 ; CHECK: ...
 
 !opencl.ocl.version = !{!0}
 !0 = !{i32 1}

llvm/test/CodeGen/AMDGPU/hsa-metadata-wavefrontsize.ll

-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 --amdhsa-code-object-version=2 -mattr=+wavefrontsize32,-wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10-32 %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 --amdhsa-code-object-version=2 -mattr=-wavefrontsize32,+wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10-64 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10-32 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 < %s | FileCheck -check-prefixes=GCN,GFX10-64 %s
 
-; GCN:      ---
-; GCN:      Kernels:
-; GCN:        - Name: wavefrontsize
-; GCN:          CodeProps:
-; GFX10-32:       WavefrontSize: 32
-; GFX10-64:       WavefrontSize: 64
-; GCN:      ...
+; GCN:      amdhsa.kernels:
+; GCN:      .name: wavefrontsize
+; GFX10-32: .wavefront_size: 32
+; GFX10-64: .wavefront_size: 64
 define amdgpu_kernel void @wavefrontsize() {
 entry:
   ret void
 }

llvm/test/CodeGen/AMDGPU/hsa-note-no-func.ll

-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx600 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-SI600 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx601 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-SI601 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx700 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI700 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx701 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI701 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx702 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI702 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx703 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI703 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx704 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI704 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=bonaire --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI704 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=mullins --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI703 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=hawaii --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI701 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kabini --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI703 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-CI700 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefix=HSA --check-prefix=HSA-VI801 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=tonga --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefix=HSA --check-prefix=HSA-VI802 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=polaris10 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=polaris11 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx801 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI801 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx802 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI802 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx803 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI803 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx810 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-VI810 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX900 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx902 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX902 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx904 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX904 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx906 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX906 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx908 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX908 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx909 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX909 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1010 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1011 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1011 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1012 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1012 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1030 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1030 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1031 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1031 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1032 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1032 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1033 --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA --check-prefix=HSA-GFX1033 %s
+; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx600 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=NONHSA-SI600 %s
+; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx601 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=NONHSA-SI601 %s
+; RUN: llc < %s -mtriple=amdgcn-- -mcpu=gfx602 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=NONHSA-SI602 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx700 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-CI700 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-CI700 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx701 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-CI701 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=hawaii --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-CI701 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx702 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-CI702 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx703 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-CI703 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kabini --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-CI703 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=mullins --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-CI703 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx704 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-CI704 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=bonaire --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-CI704 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx705 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-CI705 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx801 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-VI801 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefixes=HSA,HSA-VI801 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx802 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-VI802 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=iceland --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefixes=HSA,HSA-VI802 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=tonga --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefixes=HSA,HSA-VI802 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx803 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-VI803 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=fiji --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefixes=HSA,HSA-VI803 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=polaris10 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-VI803 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=polaris11 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-VI803 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx805 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-VI805 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=tongapro --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-VI805 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx810 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-VI810 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=stoney --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-VI810 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -mattr=-xnack | FileCheck --check-prefixes=HSA,HSA-GFX900 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-GFX901 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx902 --amdhsa-code-object-version=2 -mattr=-xnack | FileCheck --check-prefixes=HSA,HSA-GFX902 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx902 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-GFX903 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx904 --amdhsa-code-object-version=2 -mattr=-xnack | FileCheck --check-prefixes=HSA,HSA-GFX904 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx904 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-GFX905 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx906 --amdhsa-code-object-version=2 -mattr=-xnack | FileCheck --check-prefixes=HSA,HSA-GFX906 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx906 --amdhsa-code-object-version=2 | FileCheck --check-prefixes=HSA,HSA-GFX907 %s
 
 ; HSA: .hsa_code_object_version 2,1
-; HSA-SI600: .hsa_code_object_isa 6,0,0,"AMD","AMDGPU"
-; HSA-SI601: .hsa_code_object_isa 6,0,1,"AMD","AMDGPU"
+; NONHSA-SI600: .amd_amdgpu_isa "amdgcn-unknown-unknown--gfx600"
+; NONHSA-SI601: .amd_amdgpu_isa "amdgcn-unknown-unknown--gfx601"
+; NONHSA-SI602: .amd_amdgpu_isa "amdgcn-unknown-unknown--gfx602"
 ; HSA-CI700: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
 ; HSA-CI701: .hsa_code_object_isa 7,0,1,"AMD","AMDGPU"
 ; HSA-CI702: .hsa_code_object_isa 7,0,2,"AMD","AMDGPU"
 ; HSA-CI703: .hsa_code_object_isa 7,0,3,"AMD","AMDGPU"
 ; HSA-CI704: .hsa_code_object_isa 7,0,4,"AMD","AMDGPU"
+; HSA-CI705: .hsa_code_object_isa 7,0,5,"AMD","AMDGPU"
 ; HSA-VI801: .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
 ; HSA-VI802: .hsa_code_object_isa 8,0,2,"AMD","AMDGPU"
 ; HSA-VI803: .hsa_code_object_isa 8,0,3,"AMD","AMDGPU"
+; HSA-VI805: .hsa_code_object_isa 8,0,5,"AMD","AMDGPU"
 ; HSA-VI810: .hsa_code_object_isa 8,1,0,"AMD","AMDGPU"
 ; HSA-GFX900: .hsa_code_object_isa 9,0,0,"AMD","AMDGPU"
+; HSA-GFX901: .hsa_code_object_isa 9,0,1,"AMD","AMDGPU"
 ; HSA-GFX902: .hsa_code_object_isa 9,0,2,"AMD","AMDGPU"
+; HSA-GFX903: .hsa_code_object_isa 9,0,3,"AMD","AMDGPU"
 ; HSA-GFX904: .hsa_code_object_isa 9,0,4,"AMD","AMDGPU"
+; HSA-GFX905: .hsa_code_object_isa 9,0,5,"AMD","AMDGPU"
 ; HSA-GFX906: .hsa_code_object_isa 9,0,6,"AMD","AMDGPU"
-; HSA-GFX908: .hsa_code_object_isa 9,0,8,"AMD","AMDGPU"
-; HSA-GFX909: .hsa_code_object_isa 9,0,9,"AMD","AMDGPU"
-; HSA-GFX1010: .hsa_code_object_isa 10,1,0,"AMD","AMDGPU"
-; HSA-GFX1011: .hsa_code_object_isa 10,1,1,"AMD","AMDGPU"
-; HSA-GFX1012: .hsa_code_object_isa 10,1,2,"AMD","AMDGPU"
-; HSA-GFX1030: .hsa_code_object_isa 10,3,0,"AMD","AMDGPU"
-; HSA-GFX1031: .hsa_code_object_isa 10,3,1,"AMD","AMDGPU"
-; HSA-GFX1032: .hsa_code_object_isa 10,3,2,"AMD","AMDGPU"
-; HSA-GFX1033: .hsa_code_object_isa 10,3,3,"AMD","AMDGPU"
+; HSA-GFX907: .hsa_code_object_isa 9,0,7,"AMD","AMDGPU"

llvm/test/CodeGen/AMDGPU/hsa.ll

 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefix=HSA-CI %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 | FileCheck --check-prefix=HSA %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 -mattr=-flat-for-global | FileCheck --check-prefix=HSA-VI %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj --amdhsa-code-object-version=2 | llvm-readobj -symbols -s -sd - | FileCheck --check-prefix=ELF %s
 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | llvm-mc -filetype=obj -triple amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 | llvm-readobj -symbols -s -sd - | FileCheck %s --check-prefix=ELF
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 --amdhsa-code-object-version=2 -mattr=+wavefrontsize32,-wavefrontsize64 | FileCheck --check-prefix=HSA --check-prefix=GFX10 --check-prefix=GFX10-W32 %s
-; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 --amdhsa-code-object-version=2 -mattr=-wavefrontsize32,+wavefrontsize64 | FileCheck --check-prefix=HSA --check-prefix=GFX10 --check-prefix=GFX10-W64 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W32 %s
+; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 | FileCheck --check-prefix=GFX10 --check-prefix=GFX10-W64 %s
 
 ; The SHT_NOTE section contains the output from the .hsa_code_object_*
 ; directives.
 
 ; ELF: Section {
 ; ELF: Name: .text
 ; ELF: Type: SHT_PROGBITS (0x1)
 ; ELF: Flags [ (0x6)

 
 ; HSA-LABEL: .amdgpu_hsa_kernel simple
 ; HSA: {{^}}simple:
 ; HSA: .amd_kernel_code_t
 ; HSA: enable_sgpr_private_segment_buffer = 1
 ; HSA: enable_sgpr_kernarg_segment_ptr = 1
 
 ; PRE-GFX10: enable_wavefront_size32 = 0
-; GFX10-W32: enable_wavefront_size32 = 1
-; GFX10-W64: enable_wavefront_size32 = 0
+; GFX10-W32: .amdhsa_wavefront_size32 1
+; GFX10-W64: .amdhsa_wavefront_size32 0
 
 ; PRE-GFX10: wavefront_size = 6
-; GFX10-W32: wavefront_size = 5
-; GFX10-W64: wavefront_size = 6
 
 ; HSA: call_convention = -1
 ; HSA: .end_amd_kernel_code_t
 ; HSA: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x0
 
 ; Make sure we are setting the ATC bit:
 ; HSA-CI: s_mov_b32 s[[HI:[0-9]]], 0x100f000
 ; On VI+ we also need to set MTYPE = 2
 ; HSA-VI: s_mov_b32 s[[HI:[0-9]]], 0x1100f000
 ; Make sure we generate flat store for HSA
 ; PRE-GFX10: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
-; GFX10: global_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}
+; GFX10: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, off
 
 ; HSA: .Lfunc_end0:
 ; HSA: .size   simple, .Lfunc_end0-simple
 
 define amdgpu_kernel void @simple(i32 addrspace(1)* %out) {
 entry:
   store i32 0, i32 addrspace(1)* %out
   ret void

llvm/test/CodeGen/AMDGPU/kernarg-size.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefix=HSA %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 < %s | FileCheck --check-prefix=HSA %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=3 < %s | FileCheck --check-prefix=HSA %s
+
+declare void @llvm.trap() #0
+declare void @llvm.debugtrap() #1
+
+; HSA:      .amdhsa_kernel trap
+; HSA-NEXT:     .amdhsa_group_segment_fixed_size 0
+; HSA-NEXT:     .amdhsa_private_segment_fixed_size 0
+; HSA-NEXT:     .amdhsa_kernarg_size 8
+; HSA-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
+; HSA:      .end_amdhsa_kernel
+
+define amdgpu_kernel void @trap(i32 addrspace(1)* nocapture readonly %arg0) {
+  store volatile i32 1, i32 addrspace(1)* %arg0
+  call void @llvm.trap()
+  unreachable
+  store volatile i32 2, i32 addrspace(1)* %arg0
+  ret void
+}

llvm/test/CodeGen/AMDGPU/large-alloca-compute.ll

 ; RUN: llc -march=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck --check-prefixes=GCN,CI,ALL %s
 ; RUN: llc -march=amdgcn -mcpu=carrizo --show-mc-encoding < %s | FileCheck --check-prefixes=GCN,VI,ALL %s
 ; RUN: llc -march=amdgcn -mcpu=gfx900 --show-mc-encoding < %s | FileCheck --check-prefixes=GCN,GFX9,ALL %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 < %s -mattr=-flat-for-global | FileCheck --check-prefixes=GCNHSA,ALL %s
-; RUN: llc -march=amdgcn -mcpu=carrizo -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCNHSA,ALL %s
-; RUN: llc -march=amdgcn -mcpu=gfx1010 -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCNHSA,GFX10HSA,ALL %s
+; RUN: llc -march=amdgcn -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=4 < %s -mattr=-flat-for-global | FileCheck --check-prefixes=GCNHSA,ALL %s
+; RUN: llc -march=amdgcn -mcpu=carrizo -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=4 -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCNHSA,ALL %s
+; RUN: llc -march=amdgcn -mcpu=gfx1010 -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=4 -mattr=-flat-for-global < %s | FileCheck --check-prefixes=GCNHSA,GFX10HSA,ALL %s
 
 ; FIXME: align on alloca seems to be ignored for private_segment_alignment
 
 ; ALL-LABEL: {{^}}large_alloca_compute_shader:
 
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
 ; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
 ; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD1
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, -1
 ; CI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe8f000
 ; VI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe80000
 ; GFX9-DAG: s_mov_b32 s{{[0-9]+}}, 0xe00000
 
 
-; GCNHSA: .amd_kernel_code_t
-
-; GCNHSA: enable_sgpr_private_segment_wave_byte_offset = 1
-; GCNHSA: user_sgpr_count = 8
-; GCNHSA: enable_sgpr_workgroup_id_x = 1
-; GCNHSA: enable_sgpr_workgroup_id_y = 0
-; GCNHSA: enable_sgpr_workgroup_id_z = 0
-; GCNHSA: enable_sgpr_workgroup_info = 0
-; GCNHSA: enable_vgpr_workitem_id = 0
-
-; GCNHSA: enable_sgpr_private_segment_buffer = 1
-; GCNHSA: enable_sgpr_dispatch_ptr = 0
-; GCNHSA: enable_sgpr_queue_ptr = 0
-; GCNHSA: enable_sgpr_kernarg_segment_ptr = 1
-; GCNHSA: enable_sgpr_dispatch_id = 0
-; GCNHSA: enable_sgpr_flat_scratch_init = 1
-; GCNHSA: enable_sgpr_private_segment_size = 0
-; GCNHSA: enable_sgpr_grid_workgroup_count_x = 0
-; GCNHSA: enable_sgpr_grid_workgroup_count_y = 0
-; GCNHSA: enable_sgpr_grid_workgroup_count_z = 0
-; GCNHSA: workitem_private_segment_byte_size = 32772
-; GCNHSA: private_segment_alignment = 4
-; GCNHSA: .end_amd_kernel_code_t
-
 ; GFX10HSA: s_add_u32 [[FLAT_SCR_LO:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}}
 ; GFX10HSA-DAG: s_addc_u32 [[FLAT_SCR_HI:s[0-9]+]], s{{[0-9]+}}, 0
 ; GFX10HSA-DAG: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), [[FLAT_SCR_LO]]
 ; GFX10HSA-DAG: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), [[FLAT_SCR_HI]]
 
 ; GCNHSA: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], 0 offen
 ; GCNHSA: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], 0 offen
 
+; GCNHSA: .amdhsa_kernel large_alloca_compute_shader
+; GCNHSA:         .amdhsa_group_segment_fixed_size 0
+; GCNHSA:         .amdhsa_private_segment_fixed_size 32772
+; GCNHSA:         .amdhsa_user_sgpr_private_segment_buffer 1
+; GCNHSA:         .amdhsa_user_sgpr_dispatch_ptr 0
+; GCNHSA:         .amdhsa_user_sgpr_queue_ptr 0
+; GCNHSA:         .amdhsa_user_sgpr_kernarg_segment_ptr 1
+; GCNHSA:         .amdhsa_user_sgpr_dispatch_id 0
+; GCNHSA:         .amdhsa_user_sgpr_flat_scratch_init 1
+; GCNHSA:         .amdhsa_user_sgpr_private_segment_size 0
+; GCNHSA:         .amdhsa_system_sgpr_private_segment_wavefront_offset 1
+; GCNHSA:         .amdhsa_system_sgpr_workgroup_id_x 1
+; GCNHSA:         .amdhsa_system_sgpr_workgroup_id_y 0
+; GCNHSA:         .amdhsa_system_sgpr_workgroup_id_z 0
+; GCNHSA:         .amdhsa_system_sgpr_workgroup_info 0
+; GCNHSA:         .amdhsa_system_vgpr_workitem_id 0
+; GCNHSA:         .amdhsa_next_free_vgpr 3
+; GCNHSA:         .amdhsa_next_free_sgpr 10
+; GCNHSA:         .amdhsa_float_round_mode_32 0
+; GCNHSA:         .amdhsa_float_round_mode_16_64 0
+; GCNHSA:         .amdhsa_float_denorm_mode_32 3
+; GCNHSA:         .amdhsa_float_denorm_mode_16_64 3
+; GCNHSA:         .amdhsa_dx10_clamp 1
+; GCNHSA:         .amdhsa_ieee_mode 1
+; GCNHSA:         .amdhsa_exception_fp_ieee_invalid_op 0
+; GCNHSA:         .amdhsa_exception_fp_denorm_src 0
+; GCNHSA:         .amdhsa_exception_fp_ieee_div_zero 0
+; GCNHSA:         .amdhsa_exception_fp_ieee_overflow 0
+; GCNHSA:         .amdhsa_exception_fp_ieee_underflow 0
+; GCNHSA:         .amdhsa_exception_fp_ieee_inexact 0
+; GCNHSA:         .amdhsa_exception_int_div_zero 0
+; GCNHSA: .end_amdhsa_kernel
+
 ; Scratch size = alloca size + emergency stack slot, align {{.*}}, addrspace(5)
 ; ALL: ; ScratchSize: 32772
 define amdgpu_kernel void @large_alloca_compute_shader(i32 %x, i32 %y) #0 {
   %large = alloca [8192 x i32], align 4, addrspace(5)
   %gep = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 8191
   store volatile i32 %x, i32 addrspace(5)* %gep
   %gep1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 %y
   %val = load volatile i32, i32 addrspace(5)* %gep1
   store volatile i32 %val, i32 addrspace(1)* undef
   ret void
 }
 
 attributes #0 = { nounwind  }

llvm/test/CodeGen/AMDGPU/lds-global-non-entry-func.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -o - %s 2> %t | FileCheck -check-prefixes=GCN,GFX8 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -o - %s 2> %t | FileCheck -check-prefixes=GFX8 %s
 ; RUN: FileCheck -check-prefix=ERR %s < %t
 
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s 2> %t | FileCheck -check-prefixes=GCN,GFX9 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -o - %s 2> %t | FileCheck -check-prefixes=GFX9 %s
 ; RUN: FileCheck -check-prefix=ERR %s < %t
 
 @lds = internal addrspace(3) global float undef, align 4
 
 ; ERR: warning: <unknown>:0:0: in function func_use_lds_global void (): local memory global used by non-kernel function
 define void @func_use_lds_global() {
 ; GFX8-LABEL: func_use_lds_global:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX8-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX8-NEXT:    s_mov_b32 m0, -1
 ; GFX8-NEXT:    ds_write_b32 v0, v0
 ; GFX8-NEXT:    s_mov_b64 s[0:1], s[4:5]
 ; GFX8-NEXT:    s_trap 2
 ; GFX8-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: func_use_lds_global:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    ds_write_b32 v0, v0
-; GFX9-NEXT:    s_mov_b64 s[0:1], s[4:5]
 ; GFX9-NEXT:    s_trap 2
 ; GFX9-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
   store float 0.0, float addrspace(3)* @lds, align 4
   ret void
 }
 
 ; ERR: warning: <unknown>:0:0: in function func_use_lds_global_constexpr_cast void (): local memory global used by non-kernel function
 define void @func_use_lds_global_constexpr_cast() {
-; GCN-LABEL: func_use_lds_global_constexpr_cast:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    s_mov_b64 s[0:1], s[4:5]
-; GCN-NEXT:    s_trap 2
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; GFX8-LABEL: func_use_lds_global_constexpr_cast:
+; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT:    s_mov_b64 s[0:1], s[4:5]
+; GFX8-NEXT:    s_trap 2
+; GFX8-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX9-LABEL: func_use_lds_global_constexpr_cast:
+; GFX9:       ; %bb.0:
+; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX9-NEXT:    s_trap 2
+; GFX9-NEXT:    s_setpc_b64 s[30:31]
   store i32 ptrtoint (float addrspace(3)* @lds to i32), i32 addrspace(1)* undef, align 4
   ret void
 }

llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=VI %s
 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=CI %s
-; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=VI %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=CI %s
 
 define amdgpu_kernel void @s_lshr_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %lhs, <2 x i16> %rhs) #0 {
 ; GFX9-LABEL: s_lshr_v2i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX9-NEXT:    s_load_dword s4, s[0:1], 0x2c
 ; GFX9-NEXT:    s_load_dword s5, s[0:1], 0x30
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0

llvm/test/CodeGen/AMDGPU/s_addk_i32.ll

 ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -mattr=-flat-for-global,-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
 
 ; TODO: Some of those tests fail with OS == amdhsa due to unreasonable register
 ;       allocation differences.
 
 ; SI-LABEL: {{^}}s_addk_i32_k0:
 ; SI: s_load_dword [[VAL:s[0-9]+]]
 ; SI: s_addk_i32 [[VAL]], 0x41
 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[VAL]]

llvm/test/CodeGen/AMDGPU/s_mulk_i32.ll

 ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
-; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
+; RUN: llc -mtriple=amdgcn--amdpal -mcpu=tonga -mattr=-flat-for-global,-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
 
 ; SI-LABEL: {{^}}s_mulk_i32_k0:
 ; SI: s_load_dword [[VAL:s[0-9]+]]
 ; SI: s_mulk_i32 [[VAL]], 0x41
 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[VAL]]
 ; SI: buffer_store_dword [[VRESULT]]
 ; SI: s_endpgm
 define amdgpu_kernel void @s_mulk_i32_k0(i32 addrspace(1)* %out, i32 %b) {

llvm/test/CodeGen/AMDGPU/sram-ecc-default.ll

 ; RUN: llc -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,NO-ECC %s
-; RUN: llc -march=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,NO-ECC %s
+; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+sramecc < %s | FileCheck -check-prefixes=GCN,NO-ECC %s
+; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-sramecc < %s | FileCheck -check-prefixes=GCN,NO-ECC %s
+; RUN: llc -march=amdgcn -mcpu=gfx902 -mattr=+sramecc < %s | FileCheck -check-prefixes=GCN,NO-ECC %s
 ; RUN: llc -march=amdgcn -mcpu=gfx904 -mattr=+sramecc < %s | FileCheck -check-prefixes=GCN,NO-ECC %s
 ; RUN: llc -march=amdgcn -mcpu=gfx906 -mattr=+sramecc < %s | FileCheck -check-prefixes=GCN,ECC %s
 ; RUN: llc -march=amdgcn -mcpu=gfx906 -mattr=-sramecc < %s | FileCheck -check-prefixes=GCN,NO-ECC %s
 
 ; Make sure the correct set of targets are marked with
-; FeatureDoesNotSupportSRAMECC, and +sram-ecc is ignored if it's never
+; FeatureDoesNotSupportSRAMECC, and +sramecc is ignored if it's never
 ; supported.
 
 ; GCN-LABEL: {{^}}load_global_hi_v2i16_reglo_vreg:
 ; NO-ECC: global_load_short_d16_hi
 ; ECC: global_load_ushort
 define void @load_global_hi_v2i16_reglo_vreg(i16 addrspace(1)* %in, i16 %reg) {
 entry:
   %gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 -2047
   %load = load i16, i16 addrspace(1)* %gep
   %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
   %build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
   store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
   ret void
 }

llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll

-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=VI %s
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900  < %s | FileCheck -check-prefix=GFX9 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji --amdhsa-code-object-version=3 < %s | FileCheck -check-prefix=VI %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=3 < %s | FileCheck -check-prefix=GFX9 %s
 
 ; Make sure the stack is never realigned for entry functions.
 
 define amdgpu_kernel void @max_alignment_128() #0 {
 ; VI-LABEL: max_alignment_128:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_add_u32 s4, s4, s7
 ; VI-NEXT:    s_lshr_b32 flat_scratch_hi, s4, 8
 ; VI-NEXT:    s_add_u32 s0, s0, s7
 ; VI-NEXT:    s_addc_u32 s1, s1, 0
 ; VI-NEXT:    v_mov_b32_e32 v0, 9
 ; VI-NEXT:    s_mov_b32 flat_scratch_lo, s5
 ; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:128
 ; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    s_endpgm
 ; VI-NEXT:    .section .rodata,#alloc
 ; VI-NEXT:    .p2align 6
 ; VI-NEXT:    .amdhsa_kernel max_alignment_128
 ; VI-NEXT:     .amdhsa_group_segment_fixed_size 0
 ; VI-NEXT:     .amdhsa_private_segment_fixed_size 256
+; VI-NEXT:     .amdhsa_kernarg_size 0
 ; VI-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
 ; VI-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
 ; VI-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
 ; VI-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
 ; VI-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
 ; VI-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
 ; VI-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
 ; VI-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1

 ; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:128
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_endpgm
 ; GFX9-NEXT:    .section .rodata,#alloc
 ; GFX9-NEXT:    .p2align 6
 ; GFX9-NEXT:    .amdhsa_kernel max_alignment_128
 ; GFX9-NEXT:     .amdhsa_group_segment_fixed_size 0
 ; GFX9-NEXT:     .amdhsa_private_segment_fixed_size 256
+; GFX9-NEXT:     .amdhsa_kernarg_size 0
 ; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
 ; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
 ; GFX9-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
 ; GFX9-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
 ; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
 ; GFX9-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
 ; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
 ; GFX9-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
 ; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
 ; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
 ; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
 ; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
 ; GFX9-NEXT:     .amdhsa_system_vgpr_workitem_id 0
 ; GFX9-NEXT:     .amdhsa_next_free_vgpr 1
 ; GFX9-NEXT:     .amdhsa_next_free_sgpr 8
 ; GFX9-NEXT:     .amdhsa_reserve_vcc 0
+; GFX9-NEXT:     .amdhsa_reserve_xnack_mask 1
 ; GFX9-NEXT:     .amdhsa_float_round_mode_32 0
 ; GFX9-NEXT:     .amdhsa_float_round_mode_16_64 0
 ; GFX9-NEXT:     .amdhsa_float_denorm_mode_32 3
 ; GFX9-NEXT:     .amdhsa_float_denorm_mode_16_64 3
 ; GFX9-NEXT:     .amdhsa_dx10_clamp 1
 ; GFX9-NEXT:     .amdhsa_ieee_mode 1
 ; GFX9-NEXT:     .amdhsa_fp16_overflow 0
 ; GFX9-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0

 ; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
 ; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    s_endpgm
 ; VI-NEXT:    .section .rodata,#alloc
 ; VI-NEXT:    .p2align 6
 ; VI-NEXT:    .amdhsa_kernel stackrealign_attr
 ; VI-NEXT:     .amdhsa_group_segment_fixed_size 0
 ; VI-NEXT:     .amdhsa_private_segment_fixed_size 8
+; VI-NEXT:     .amdhsa_kernarg_size 0
 ; VI-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
 ; VI-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
 ; VI-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
 ; VI-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
 ; VI-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
 ; VI-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
 ; VI-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
 ; VI-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1

 ; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_endpgm
 ; GFX9-NEXT:    .section .rodata,#alloc
 ; GFX9-NEXT:    .p2align 6
 ; GFX9-NEXT:    .amdhsa_kernel stackrealign_attr
 ; GFX9-NEXT:     .amdhsa_group_segment_fixed_size 0
 ; GFX9-NEXT:     .amdhsa_private_segment_fixed_size 8
+; GFX9-NEXT:     .amdhsa_kernarg_size 0
 ; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
 ; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
 ; GFX9-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
 ; GFX9-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
 ; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
 ; GFX9-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
 ; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
 ; GFX9-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
 ; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
 ; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
 ; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
 ; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
 ; GFX9-NEXT:     .amdhsa_system_vgpr_workitem_id 0
 ; GFX9-NEXT:     .amdhsa_next_free_vgpr 1
 ; GFX9-NEXT:     .amdhsa_next_free_sgpr 8
 ; GFX9-NEXT:     .amdhsa_reserve_vcc 0
+; GFX9-NEXT:     .amdhsa_reserve_xnack_mask 1
 ; GFX9-NEXT:     .amdhsa_float_round_mode_32 0
 ; GFX9-NEXT:     .amdhsa_float_round_mode_16_64 0
 ; GFX9-NEXT:     .amdhsa_float_denorm_mode_32 3
 ; GFX9-NEXT:     .amdhsa_float_denorm_mode_16_64 3
 ; GFX9-NEXT:     .amdhsa_dx10_clamp 1
 ; GFX9-NEXT:     .amdhsa_ieee_mode 1
 ; GFX9-NEXT:     .amdhsa_fp16_overflow 0
 ; GFX9-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0

 ; VI-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
 ; VI-NEXT:    s_waitcnt vmcnt(0)
 ; VI-NEXT:    s_endpgm
 ; VI-NEXT:    .section .rodata,#alloc
 ; VI-NEXT:    .p2align 6
 ; VI-NEXT:    .amdhsa_kernel alignstack_attr
 ; VI-NEXT:     .amdhsa_group_segment_fixed_size 0
 ; VI-NEXT:     .amdhsa_private_segment_fixed_size 128
+; VI-NEXT:     .amdhsa_kernarg_size 0
 ; VI-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
 ; VI-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
 ; VI-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
 ; VI-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
 ; VI-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
 ; VI-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
 ; VI-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
 ; VI-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1

 ; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_endpgm
 ; GFX9-NEXT:    .section .rodata,#alloc
 ; GFX9-NEXT:    .p2align 6
 ; GFX9-NEXT:    .amdhsa_kernel alignstack_attr
 ; GFX9-NEXT:     .amdhsa_group_segment_fixed_size 0
 ; GFX9-NEXT:     .amdhsa_private_segment_fixed_size 128
+; GFX9-NEXT:     .amdhsa_kernarg_size 0
 ; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_buffer 1
 ; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_ptr 0
 ; GFX9-NEXT:     .amdhsa_user_sgpr_queue_ptr 0
 ; GFX9-NEXT:     .amdhsa_user_sgpr_kernarg_segment_ptr 0
 ; GFX9-NEXT:     .amdhsa_user_sgpr_dispatch_id 0
 ; GFX9-NEXT:     .amdhsa_user_sgpr_flat_scratch_init 1
 ; GFX9-NEXT:     .amdhsa_user_sgpr_private_segment_size 0
 ; GFX9-NEXT:     .amdhsa_system_sgpr_private_segment_wavefront_offset 1
 ; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_x 1
 ; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_y 0
 ; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_id_z 0
 ; GFX9-NEXT:     .amdhsa_system_sgpr_workgroup_info 0
 ; GFX9-NEXT:     .amdhsa_system_vgpr_workitem_id 0
 ; GFX9-NEXT:     .amdhsa_next_free_vgpr 1
 ; GFX9-NEXT:     .amdhsa_next_free_sgpr 8
 ; GFX9-NEXT:     .amdhsa_reserve_vcc 0
+; GFX9-NEXT:     .amdhsa_reserve_xnack_mask 1
 ; GFX9-NEXT:     .amdhsa_float_round_mode_32 0
 ; GFX9-NEXT:     .amdhsa_float_round_mode_16_64 0
 ; GFX9-NEXT:     .amdhsa_float_denorm_mode_32 3
 ; GFX9-NEXT:     .amdhsa_float_denorm_mode_16_64 3
 ; GFX9-NEXT:     .amdhsa_dx10_clamp 1
 ; GFX9-NEXT:     .amdhsa_ieee_mode 1
 ; GFX9-NEXT:     .amdhsa_fp16_overflow 0
 ; GFX9-NEXT:     .amdhsa_exception_fp_ieee_invalid_op 0

llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-any.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 --filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900"
+; ASM:  amdhsa.target: amdgcn-amd-amdhsa--gfx900
+; ASM:  amdhsa.version:
+; ASM:    - 1
+; ASM:    - 1
+
+; ELF:      OS/ABI: AMDGPU_HSA (0x40)
+; ELF:      ABIVersion: 2
+; ELF:      Flags [ (0x12C)
+; ELF-NEXT:   EF_AMDGPU_FEATURE_XNACK_ANY_V4 (0x100)
+; ELF-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX900   (0x2C)
+; ELF-NEXT: ]
+
+define void @func0() {
+entry:
+  ret void
+}
+
+define void @func1() {
+entry:
+  ret void
+}
+
+define void @func2() {
+entry:
+  ret void
+}

llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-not-supported.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=4 < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=4 --filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx700"
+; ASM:  amdhsa.target: amdgcn-amd-amdhsa--gfx700
+; ASM:  amdhsa.version:
+; ASM:    - 1
+; ASM:    - 1
+
+; ELF:      OS/ABI: AMDGPU_HSA (0x40)
+; ELF:      ABIVersion: 2
+; ELF:      Flags [ (0x22)
+; ELF-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX700 (0x22)
+; ELF-NEXT: ]
+
+define void @func0() {
+entry:
+  ret void
+}
+
+define void @func1() {
+entry:
+  ret void
+}
+
+define void @func2() {
+entry:
+  ret void
+}

llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-off.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 --filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target  "amdgcn-amd-amdhsa--gfx900:xnack-"
+; ASM:  amdhsa.target: 'amdgcn-amd-amdhsa--gfx900:xnack-'
+; ASM:  amdhsa.version:
+; ASM:    - 1
+; ASM:    - 1
+
+; ELF:      OS/ABI: AMDGPU_HSA (0x40)
+; ELF:      ABIVersion: 2
+; ELF:      Flags [ (0x22C)
+; ELF-NEXT:   EF_AMDGPU_FEATURE_XNACK_OFF_V4 (0x200)
+; ELF-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX900   (0x2C)
+; ELF-NEXT: ]
+
+define void @func0() #0 {
+entry:
+  ret void
+}
+
+define void @func1() #0 {
+entry:
+  ret void
+}
+
+define void @func2() #0 {
+entry:
+  ret void
+}
+
+attributes #0 = { "target-features"="-xnack" }

llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-on.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 --filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target  "amdgcn-amd-amdhsa--gfx900:xnack+"
+; ASM:  amdhsa.target: 'amdgcn-amd-amdhsa--gfx900:xnack+'
+; ASM:  amdhsa.version:
+; ASM:    - 1
+; ASM:    - 1
+
+; ELF:      OS/ABI: AMDGPU_HSA (0x40)
+; ELF:      ABIVersion: 2
+; ELF:      Flags [ (0x32C)
+; ELF-NEXT:   EF_AMDGPU_FEATURE_XNACK_ON_V4 (0x300)
+; ELF-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX900  (0x2C)
+; ELF-NEXT: ]
+
+define void @func0() #0 {
+entry:
+  ret void
+}
+
+define void @func1() #0 {
+entry:
+  ret void
+}
+
+define void @func2() #0 {
+entry:
+  ret void
+}
+
+attributes #0 = { "target-features"="+xnack" }

llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-1.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 --filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target  "amdgcn-amd-amdhsa--gfx900:xnack-"
+; ASM:  amdhsa.target: 'amdgcn-amd-amdhsa--gfx900:xnack-'
+; ASM:  amdhsa.version:
+; ASM:    - 1
+; ASM:    - 1
+
+; ELF:      OS/ABI: AMDGPU_HSA (0x40)
+; ELF:      ABIVersion: 2
+; ELF:      Flags [ (0x22C)
+; ELF-NEXT:   EF_AMDGPU_FEATURE_XNACK_OFF_V4 (0x200)
+; ELF-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX900   (0x2C)
+; ELF-NEXT: ]
+
+define void @func0() {
+entry:
+  ret void
+}
+
+define void @func1() #0 {
+entry:
+  ret void
+}
+
+define void @func2() {
+entry:
+  ret void
+}
+
+attributes #0 = { "target-features"="-xnack" }

llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-2.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 --filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target  "amdgcn-amd-amdhsa--gfx900:xnack-"
+; ASM:  amdhsa.target: 'amdgcn-amd-amdhsa--gfx900:xnack-'
+; ASM:  amdhsa.version:
+; ASM:    - 1
+; ASM:    - 1
+
+; ELF:      OS/ABI: AMDGPU_HSA (0x40)
+; ELF:      ABIVersion: 2
+; ELF:      Flags [ (0x22C)
+; ELF-NEXT:   EF_AMDGPU_FEATURE_XNACK_OFF_V4 (0x200)
+; ELF-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX900   (0x2C)
+; ELF-NEXT: ]
+
+define void @func0() #0 {
+entry:
+  ret void
+}
+
+define void @func1() {
+entry:
+  ret void
+}
+
+define void @func2() {
+entry:
+  ret void
+}
+
+attributes #0 = { "target-features"="-xnack" }

llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-1.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 --filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target  "amdgcn-amd-amdhsa--gfx900:xnack+"
+; ASM:  amdhsa.target: 'amdgcn-amd-amdhsa--gfx900:xnack+'
+; ASM:  amdhsa.version:
+; ASM:    - 1
+; ASM:    - 1
+
+; ELF:      OS/ABI: AMDGPU_HSA (0x40)
+; ELF:      ABIVersion: 2
+; ELF:      Flags [ (0x32C)
+; ELF-NEXT:   EF_AMDGPU_FEATURE_XNACK_ON_V4 (0x300)
+; ELF-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX900  (0x2C)
+; ELF-NEXT: ]
+
+define void @func0() {
+entry:
+  ret void
+}
+
+define void @func1() #0 {
+entry:
+  ret void
+}
+
+define void @func2() {
+entry:
+  ret void
+}
+
+attributes #0 = { "target-features"="+xnack" }

llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-2.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 --filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target  "amdgcn-amd-amdhsa--gfx900:xnack+"
+; ASM:  amdhsa.target: 'amdgcn-amd-amdhsa--gfx900:xnack+'
+; ASM:  amdhsa.version:
+; ASM:    - 1
+; ASM:    - 1
+
+; ELF:      OS/ABI: AMDGPU_HSA (0x40)
+; ELF:      ABIVersion: 2
+; ELF:      Flags [ (0x32C)
+; ELF-NEXT:   EF_AMDGPU_FEATURE_XNACK_ON_V4 (0x300)
+; ELF-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX900  (0x2C)
+; ELF-NEXT: ]
+
+define void @func0() #0 {
+entry:
+  ret void
+}
+
+define void @func1() {
+entry:
+  ret void
+}
+
+define void @func2() {
+entry:
+  ret void
+}
+
+attributes #0 = { "target-features"="+xnack" }

llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-invalid-any-off-on.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 < %s 2>&1 | FileCheck --check-prefixes=ERR %s
+
+; ERR: error: xnack setting of 'func2' function does not match module xnack setting
+
+define void @func0() {
+entry:
+  ret void
+}
+
+define void @func1() #0 {
+entry:
+  ret void
+}
+
+define void @func2() #1 {
+entry:
+  ret void
+}
+
+attributes #0 = { "target-features"="-xnack" }
+attributes #1 = { "target-features"="+xnack" }

llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-any.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 --filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx900"
+; ASM:  amdhsa.target: amdgcn-amd-amdhsa--gfx900
+; ASM:  amdhsa.version:
+; ASM:    - 1
+; ASM:    - 1
+
+; ELF:      OS/ABI: AMDGPU_HSA (0x40)
+; ELF:      ABIVersion: 2
+; ELF:      Flags [ (0x12C)
+; ELF-NEXT:   EF_AMDGPU_FEATURE_XNACK_ANY_V4 (0x100)
+; ELF-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX900   (0x2C)
+; ELF-NEXT: ]
+
+define void @func0() {
+entry:
+  ret void
+}

llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-not-supported.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=4 < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 --amdhsa-code-object-version=4 --filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx700"
+; ASM:  amdhsa.target: amdgcn-amd-amdhsa--gfx700
+; ASM:  amdhsa.version:
+; ASM:    - 1
+; ASM:    - 1
+
+; ELF:      OS/ABI: AMDGPU_HSA (0x40)
+; ELF:      ABIVersion: 2
+; ELF:      Flags [ (0x22)
+; ELF-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX700 (0x22)
+; ELF-NEXT: ]
+
+define void @func0() {
+entry:
+  ret void
+}

llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-off.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 --filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target  "amdgcn-amd-amdhsa--gfx900:xnack-"
+; ASM:  amdhsa.target: 'amdgcn-amd-amdhsa--gfx900:xnack-'
+; ASM:  amdhsa.version:
+; ASM:    - 1
+; ASM:    - 1
+
+; ELF:      OS/ABI: AMDGPU_HSA (0x40)
+; ELF:      ABIVersion: 2
+; ELF:      Flags [ (0x22C)
+; ELF-NEXT:   EF_AMDGPU_FEATURE_XNACK_OFF_V4 (0x200)
+; ELF-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX900   (0x2C)
+; ELF-NEXT: ]
+
+define void @func0() #0 {
+entry:
+  ret void
+}
+
+attributes #0 = { "target-features"="-xnack" }

llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-on.ll

+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 < %s | FileCheck --check-prefixes=ASM %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 --filetype=obj < %s | llvm-readobj --file-headers - | FileCheck --check-prefixes=ELF %s
+
+; ASM: .amdgcn_target  "amdgcn-amd-amdhsa--gfx900:xnack+"
+; ASM:  amdhsa.target: 'amdgcn-amd-amdhsa--gfx900:xnack+'
+; ASM:  amdhsa.version:
+; ASM:    - 1
+; ASM:    - 1
+
+; ELF:      OS/ABI: AMDGPU_HSA (0x40)
+; ELF:      ABIVersion: 2
+; ELF:      Flags [ (0x32C)
+; ELF-NEXT:   EF_AMDGPU_FEATURE_XNACK_ON_V4 (0x300)
+; ELF-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX900  (0x2C)
+; ELF-NEXT: ]
+
+define void @func0() #0 {
+entry:
+  ret void
+}
+
+attributes #0 = { "target-features"="+xnack" }

llvm/test/CodeGen/AMDGPU/trap-abis.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=amdgcn -mcpu=gfx900 --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck --check-prefix=NOHSA-TRAP-GFX900-V2 %s
+; RUN: llc -march=amdgcn -mcpu=gfx900 --amdhsa-code-object-version=3 -verify-machineinstrs < %s | FileCheck --check-prefix=NOHSA-TRAP-GFX900-V3 %s
+; RUN: llc -march=amdgcn -mcpu=gfx900 --amdhsa-code-object-version=4 -verify-machineinstrs < %s | FileCheck --check-prefix=NOHSA-TRAP-GFX900-V4 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck --check-prefix=HSA-TRAP-GFX803-V2 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 --amdhsa-code-object-version=3 -verify-machineinstrs < %s | FileCheck --check-prefix=HSA-TRAP-GFX803-V3 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 --amdhsa-code-object-version=4 -verify-machineinstrs < %s | FileCheck --check-prefix=HSA-TRAP-GFX803-V4 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck --check-prefix=HSA-TRAP-GFX900-V2 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=3 -verify-machineinstrs < %s | FileCheck --check-prefix=HSA-TRAP-GFX900-V3 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 --amdhsa-code-object-version=4 -verify-machineinstrs < %s | FileCheck --check-prefix=HSA-TRAP-GFX900-V4 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-trap-handler --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck --check-prefix=HSA-NOTRAP-GFX900-V2 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-trap-handler --amdhsa-code-object-version=3 -verify-machineinstrs < %s | FileCheck --check-prefix=HSA-NOTRAP-GFX900-V3 %s
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-trap-handler --amdhsa-code-object-version=4 -verify-machineinstrs < %s | FileCheck --check-prefix=HSA-NOTRAP-GFX900-V4 %s
+
+declare void @llvm.trap() #0
+declare void @llvm.debugtrap() #1
+
+define amdgpu_kernel void @trap(i32 addrspace(1)* nocapture readonly %arg0) {
+; NOHSA-TRAP-GFX900-V2-LABEL: trap:
+; NOHSA-TRAP-GFX900-V2:       ; %bb.0:
+; NOHSA-TRAP-GFX900-V2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; NOHSA-TRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v0, 0
+; NOHSA-TRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v1, 1
+; NOHSA-TRAP-GFX900-V2-NEXT:    s_waitcnt lgkmcnt(0)
+; NOHSA-TRAP-GFX900-V2-NEXT:    global_store_dword v0, v1, s[0:1]
+; NOHSA-TRAP-GFX900-V2-NEXT:    s_waitcnt vmcnt(0)
+; NOHSA-TRAP-GFX900-V2-NEXT:    s_endpgm
+;
+; NOHSA-TRAP-GFX900-V3-LABEL: trap:
+; NOHSA-TRAP-GFX900-V3:       ; %bb.0:
+; NOHSA-TRAP-GFX900-V3-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; NOHSA-TRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v0, 0
+; NOHSA-TRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v1, 1
+; NOHSA-TRAP-GFX900-V3-NEXT:    s_waitcnt lgkmcnt(0)
+; NOHSA-TRAP-GFX900-V3-NEXT:    global_store_dword v0, v1, s[0:1]
+; NOHSA-TRAP-GFX900-V3-NEXT:    s_waitcnt vmcnt(0)
+; NOHSA-TRAP-GFX900-V3-NEXT:    s_endpgm
+;
+; NOHSA-TRAP-GFX900-V4-LABEL: trap:
+; NOHSA-TRAP-GFX900-V4:       ; %bb.0:
+; NOHSA-TRAP-GFX900-V4-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; NOHSA-TRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v0, 0
+; NOHSA-TRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v1, 1
+; NOHSA-TRAP-GFX900-V4-NEXT:    s_waitcnt lgkmcnt(0)
+; NOHSA-TRAP-GFX900-V4-NEXT:    global_store_dword v0, v1, s[0:1]
+; NOHSA-TRAP-GFX900-V4-NEXT:    s_waitcnt vmcnt(0)
+; NOHSA-TRAP-GFX900-V4-NEXT:    s_endpgm
+;
+; HSA-TRAP-GFX803-V2-LABEL: trap:
+; HSA-TRAP-GFX803-V2:         .amd_kernel_code_t
+; HSA-TRAP-GFX803-V2-NEXT:     amd_code_version_major = 1
+; HSA-TRAP-GFX803-V2-NEXT:     amd_code_version_minor = 2
+; HSA-TRAP-GFX803-V2-NEXT:     amd_machine_kind = 1
+; HSA-TRAP-GFX803-V2-NEXT:     amd_machine_version_major = 8
+; HSA-TRAP-GFX803-V2-NEXT:     amd_machine_version_minor = 0
+; HSA-TRAP-GFX803-V2-NEXT:     amd_machine_version_stepping = 3
+; HSA-TRAP-GFX803-V2-NEXT:     kernel_code_entry_byte_offset = 256
+; HSA-TRAP-GFX803-V2-NEXT:     kernel_code_prefetch_byte_size = 0
+; HSA-TRAP-GFX803-V2-NEXT:     granulated_workitem_vgpr_count = 0
+; HSA-TRAP-GFX803-V2-NEXT:     granulated_wavefront_sgpr_count = 0
+; HSA-TRAP-GFX803-V2-NEXT:     priority = 0
+; HSA-TRAP-GFX803-V2-NEXT:     float_mode = 240
+; HSA-TRAP-GFX803-V2-NEXT:     priv = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_dx10_clamp = 1
+; HSA-TRAP-GFX803-V2-NEXT:     debug_mode = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_ieee_mode = 1
+; HSA-TRAP-GFX803-V2-NEXT:     enable_wgp_mode = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_mem_ordered = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_fwd_progress = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_private_segment_wave_byte_offset = 0
+; HSA-TRAP-GFX803-V2-NEXT:     user_sgpr_count = 8
+; HSA-TRAP-GFX803-V2-NEXT:     enable_trap_handler = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_workgroup_id_x = 1
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_workgroup_id_y = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_workgroup_id_z = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_workgroup_info = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_vgpr_workitem_id = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_exception_msb = 0
+; HSA-TRAP-GFX803-V2-NEXT:     granulated_lds_size = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_exception = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_private_segment_buffer = 1
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_dispatch_ptr = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_queue_ptr = 1
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_kernarg_segment_ptr = 1
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_dispatch_id = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_flat_scratch_init = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_private_segment_size = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_grid_workgroup_count_x = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_grid_workgroup_count_y = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_grid_workgroup_count_z = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_wavefront_size32 = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_ordered_append_gds = 0
+; HSA-TRAP-GFX803-V2-NEXT:     private_element_size = 1
+; HSA-TRAP-GFX803-V2-NEXT:     is_ptr64 = 1
+; HSA-TRAP-GFX803-V2-NEXT:     is_dynamic_callstack = 0
+; HSA-TRAP-GFX803-V2-NEXT:     is_debug_enabled = 0
+; HSA-TRAP-GFX803-V2-NEXT:     is_xnack_enabled = 0
+; HSA-TRAP-GFX803-V2-NEXT:     workitem_private_segment_byte_size = 0
+; HSA-TRAP-GFX803-V2-NEXT:     workgroup_group_segment_byte_size = 0
+; HSA-TRAP-GFX803-V2-NEXT:     gds_segment_byte_size = 0
+; HSA-TRAP-GFX803-V2-NEXT:     kernarg_segment_byte_size = 8
+; HSA-TRAP-GFX803-V2-NEXT:     workgroup_fbarrier_count = 0
+; HSA-TRAP-GFX803-V2-NEXT:     wavefront_sgpr_count = 8
+; HSA-TRAP-GFX803-V2-NEXT:     workitem_vgpr_count = 3
+; HSA-TRAP-GFX803-V2-NEXT:     reserved_vgpr_first = 0
+; HSA-TRAP-GFX803-V2-NEXT:     reserved_vgpr_count = 0
+; HSA-TRAP-GFX803-V2-NEXT:     reserved_sgpr_first = 0
+; HSA-TRAP-GFX803-V2-NEXT:     reserved_sgpr_count = 0
+; HSA-TRAP-GFX803-V2-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
+; HSA-TRAP-GFX803-V2-NEXT:     debug_private_segment_buffer_sgpr = 0
+; HSA-TRAP-GFX803-V2-NEXT:     kernarg_segment_alignment = 4
+; HSA-TRAP-GFX803-V2-NEXT:     group_segment_alignment = 4
+; HSA-TRAP-GFX803-V2-NEXT:     private_segment_alignment = 4
+; HSA-TRAP-GFX803-V2-NEXT:     wavefront_size = 6
+; HSA-TRAP-GFX803-V2-NEXT:     call_convention = -1
+; HSA-TRAP-GFX803-V2-NEXT:     runtime_loader_kernel_symbol = 0
+; HSA-TRAP-GFX803-V2-NEXT:    .end_amd_kernel_code_t
+; HSA-TRAP-GFX803-V2-NEXT:  ; %bb.0:
+; HSA-TRAP-GFX803-V2-NEXT:    s_load_dwordx2 s[2:3], s[6:7], 0x0
+; HSA-TRAP-GFX803-V2-NEXT:    v_mov_b32_e32 v2, 1
+; HSA-TRAP-GFX803-V2-NEXT:    s_mov_b64 s[0:1], s[4:5]
+; HSA-TRAP-GFX803-V2-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX803-V2-NEXT:    v_mov_b32_e32 v0, s2
+; HSA-TRAP-GFX803-V2-NEXT:    v_mov_b32_e32 v1, s3
+; HSA-TRAP-GFX803-V2-NEXT:    flat_store_dword v[0:1], v2
+; HSA-TRAP-GFX803-V2-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX803-V2-NEXT:    s_trap 2
+;
+; HSA-TRAP-GFX803-V3-LABEL: trap:
+; HSA-TRAP-GFX803-V3:       ; %bb.0:
+; HSA-TRAP-GFX803-V3-NEXT:    s_load_dwordx2 s[2:3], s[6:7], 0x0
+; HSA-TRAP-GFX803-V3-NEXT:    v_mov_b32_e32 v2, 1
+; HSA-TRAP-GFX803-V3-NEXT:    s_mov_b64 s[0:1], s[4:5]
+; HSA-TRAP-GFX803-V3-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX803-V3-NEXT:    v_mov_b32_e32 v0, s2
+; HSA-TRAP-GFX803-V3-NEXT:    v_mov_b32_e32 v1, s3
+; HSA-TRAP-GFX803-V3-NEXT:    flat_store_dword v[0:1], v2
+; HSA-TRAP-GFX803-V3-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX803-V3-NEXT:    s_trap 2
+;
+; HSA-TRAP-GFX803-V4-LABEL: trap:
+; HSA-TRAP-GFX803-V4:       ; %bb.0:
+; HSA-TRAP-GFX803-V4-NEXT:    s_load_dwordx2 s[2:3], s[6:7], 0x0
+; HSA-TRAP-GFX803-V4-NEXT:    v_mov_b32_e32 v2, 1
+; HSA-TRAP-GFX803-V4-NEXT:    s_mov_b64 s[0:1], s[4:5]
+; HSA-TRAP-GFX803-V4-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX803-V4-NEXT:    v_mov_b32_e32 v0, s2
+; HSA-TRAP-GFX803-V4-NEXT:    v_mov_b32_e32 v1, s3
+; HSA-TRAP-GFX803-V4-NEXT:    flat_store_dword v[0:1], v2
+; HSA-TRAP-GFX803-V4-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX803-V4-NEXT:    s_trap 2
+;
+; HSA-TRAP-GFX900-V2-LABEL: trap:
+; HSA-TRAP-GFX900-V2:         .amd_kernel_code_t
+; HSA-TRAP-GFX900-V2-NEXT:     amd_code_version_major = 1
+; HSA-TRAP-GFX900-V2-NEXT:     amd_code_version_minor = 2
+; HSA-TRAP-GFX900-V2-NEXT:     amd_machine_kind = 1
+; HSA-TRAP-GFX900-V2-NEXT:     amd_machine_version_major = 9
+; HSA-TRAP-GFX900-V2-NEXT:     amd_machine_version_minor = 0
+; HSA-TRAP-GFX900-V2-NEXT:     amd_machine_version_stepping = 0
+; HSA-TRAP-GFX900-V2-NEXT:     kernel_code_entry_byte_offset = 256
+; HSA-TRAP-GFX900-V2-NEXT:     kernel_code_prefetch_byte_size = 0
+; HSA-TRAP-GFX900-V2-NEXT:     granulated_workitem_vgpr_count = 0
+; HSA-TRAP-GFX900-V2-NEXT:     granulated_wavefront_sgpr_count = 0
+; HSA-TRAP-GFX900-V2-NEXT:     priority = 0
+; HSA-TRAP-GFX900-V2-NEXT:     float_mode = 240
+; HSA-TRAP-GFX900-V2-NEXT:     priv = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_dx10_clamp = 1
+; HSA-TRAP-GFX900-V2-NEXT:     debug_mode = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_ieee_mode = 1
+; HSA-TRAP-GFX900-V2-NEXT:     enable_wgp_mode = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_mem_ordered = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_fwd_progress = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_private_segment_wave_byte_offset = 0
+; HSA-TRAP-GFX900-V2-NEXT:     user_sgpr_count = 8
+; HSA-TRAP-GFX900-V2-NEXT:     enable_trap_handler = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_id_x = 1
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_id_y = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_id_z = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_info = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_vgpr_workitem_id = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_exception_msb = 0
+; HSA-TRAP-GFX900-V2-NEXT:     granulated_lds_size = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_exception = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_private_segment_buffer = 1
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_dispatch_ptr = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_queue_ptr = 1
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_kernarg_segment_ptr = 1
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_dispatch_id = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_flat_scratch_init = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_private_segment_size = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_grid_workgroup_count_x = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_grid_workgroup_count_y = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_grid_workgroup_count_z = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_wavefront_size32 = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_ordered_append_gds = 0
+; HSA-TRAP-GFX900-V2-NEXT:     private_element_size = 1
+; HSA-TRAP-GFX900-V2-NEXT:     is_ptr64 = 1
+; HSA-TRAP-GFX900-V2-NEXT:     is_dynamic_callstack = 0
+; HSA-TRAP-GFX900-V2-NEXT:     is_debug_enabled = 0
+; HSA-TRAP-GFX900-V2-NEXT:     is_xnack_enabled = 1
+; HSA-TRAP-GFX900-V2-NEXT:     workitem_private_segment_byte_size = 0
+; HSA-TRAP-GFX900-V2-NEXT:     workgroup_group_segment_byte_size = 0
+; HSA-TRAP-GFX900-V2-NEXT:     gds_segment_byte_size = 0
+; HSA-TRAP-GFX900-V2-NEXT:     kernarg_segment_byte_size = 8
+; HSA-TRAP-GFX900-V2-NEXT:     workgroup_fbarrier_count = 0
+; HSA-TRAP-GFX900-V2-NEXT:     wavefront_sgpr_count = 8
+; HSA-TRAP-GFX900-V2-NEXT:     workitem_vgpr_count = 2
+; HSA-TRAP-GFX900-V2-NEXT:     reserved_vgpr_first = 0
+; HSA-TRAP-GFX900-V2-NEXT:     reserved_vgpr_count = 0
+; HSA-TRAP-GFX900-V2-NEXT:     reserved_sgpr_first = 0
+; HSA-TRAP-GFX900-V2-NEXT:     reserved_sgpr_count = 0
+; HSA-TRAP-GFX900-V2-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
+; HSA-TRAP-GFX900-V2-NEXT:     debug_private_segment_buffer_sgpr = 0
+; HSA-TRAP-GFX900-V2-NEXT:     kernarg_segment_alignment = 4
+; HSA-TRAP-GFX900-V2-NEXT:     group_segment_alignment = 4
+; HSA-TRAP-GFX900-V2-NEXT:     private_segment_alignment = 4
+; HSA-TRAP-GFX900-V2-NEXT:     wavefront_size = 6
+; HSA-TRAP-GFX900-V2-NEXT:     call_convention = -1
+; HSA-TRAP-GFX900-V2-NEXT:     runtime_loader_kernel_symbol = 0
+; HSA-TRAP-GFX900-V2-NEXT:    .end_amd_kernel_code_t
+; HSA-TRAP-GFX900-V2-NEXT:  ; %bb.0:
+; HSA-TRAP-GFX900-V2-NEXT:    s_load_dwordx2 s[2:3], s[6:7], 0x0
+; HSA-TRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v0, 0
+; HSA-TRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v1, 1
+; HSA-TRAP-GFX900-V2-NEXT:    s_mov_b64 s[0:1], s[4:5]
+; HSA-TRAP-GFX900-V2-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX900-V2-NEXT:    global_store_dword v0, v1, s[2:3]
+; HSA-TRAP-GFX900-V2-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX900-V2-NEXT:    s_trap 2
+;
+; HSA-TRAP-GFX900-V3-LABEL: trap:
+; HSA-TRAP-GFX900-V3:       ; %bb.0:
+; HSA-TRAP-GFX900-V3-NEXT:    s_load_dwordx2 s[2:3], s[6:7], 0x0
+; HSA-TRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v0, 0
+; HSA-TRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v1, 1
+; HSA-TRAP-GFX900-V3-NEXT:    s_mov_b64 s[0:1], s[4:5]
+; HSA-TRAP-GFX900-V3-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX900-V3-NEXT:    global_store_dword v0, v1, s[2:3]
+; HSA-TRAP-GFX900-V3-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX900-V3-NEXT:    s_trap 2
+;
+; HSA-TRAP-GFX900-V4-LABEL: trap:
+; HSA-TRAP-GFX900-V4:       ; %bb.0:
+; HSA-TRAP-GFX900-V4-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-TRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v0, 0
+; HSA-TRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v1, 1
+; HSA-TRAP-GFX900-V4-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX900-V4-NEXT:    global_store_dword v0, v1, s[0:1]
+; HSA-TRAP-GFX900-V4-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX900-V4-NEXT:    s_trap 2
+;
+; HSA-NOTRAP-GFX900-V2-LABEL: trap:
+; HSA-NOTRAP-GFX900-V2:         .amd_kernel_code_t
+; HSA-NOTRAP-GFX900-V2-NEXT:     amd_code_version_major = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     amd_code_version_minor = 2
+; HSA-NOTRAP-GFX900-V2-NEXT:     amd_machine_kind = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     amd_machine_version_major = 9
+; HSA-NOTRAP-GFX900-V2-NEXT:     amd_machine_version_minor = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     amd_machine_version_stepping = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     kernel_code_entry_byte_offset = 256
+; HSA-NOTRAP-GFX900-V2-NEXT:     kernel_code_prefetch_byte_size = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     granulated_workitem_vgpr_count = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     granulated_wavefront_sgpr_count = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     priority = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     float_mode = 240
+; HSA-NOTRAP-GFX900-V2-NEXT:     priv = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_dx10_clamp = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     debug_mode = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_ieee_mode = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_wgp_mode = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_mem_ordered = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_fwd_progress = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_private_segment_wave_byte_offset = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     user_sgpr_count = 8
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_trap_handler = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_id_x = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_id_y = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_id_z = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_info = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_vgpr_workitem_id = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_exception_msb = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     granulated_lds_size = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_exception = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_private_segment_buffer = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_dispatch_ptr = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_queue_ptr = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_kernarg_segment_ptr = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_dispatch_id = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_flat_scratch_init = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_private_segment_size = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_grid_workgroup_count_x = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_grid_workgroup_count_y = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_grid_workgroup_count_z = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_wavefront_size32 = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_ordered_append_gds = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     private_element_size = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     is_ptr64 = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     is_dynamic_callstack = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     is_debug_enabled = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     is_xnack_enabled = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     workitem_private_segment_byte_size = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     workgroup_group_segment_byte_size = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     gds_segment_byte_size = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     kernarg_segment_byte_size = 8
+; HSA-NOTRAP-GFX900-V2-NEXT:     workgroup_fbarrier_count = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     wavefront_sgpr_count = 8
+; HSA-NOTRAP-GFX900-V2-NEXT:     workitem_vgpr_count = 2
+; HSA-NOTRAP-GFX900-V2-NEXT:     reserved_vgpr_first = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     reserved_vgpr_count = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     reserved_sgpr_first = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     reserved_sgpr_count = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     debug_private_segment_buffer_sgpr = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     kernarg_segment_alignment = 4
+; HSA-NOTRAP-GFX900-V2-NEXT:     group_segment_alignment = 4
+; HSA-NOTRAP-GFX900-V2-NEXT:     private_segment_alignment = 4
+; HSA-NOTRAP-GFX900-V2-NEXT:     wavefront_size = 6
+; HSA-NOTRAP-GFX900-V2-NEXT:     call_convention = -1
+; HSA-NOTRAP-GFX900-V2-NEXT:     runtime_loader_kernel_symbol = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:    .end_amd_kernel_code_t
+; HSA-NOTRAP-GFX900-V2-NEXT:  ; %bb.0:
+; HSA-NOTRAP-GFX900-V2-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-NOTRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v0, 0
+; HSA-NOTRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v1, 1
+; HSA-NOTRAP-GFX900-V2-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-NOTRAP-GFX900-V2-NEXT:    global_store_dword v0, v1, s[0:1]
+; HSA-NOTRAP-GFX900-V2-NEXT:    s_waitcnt vmcnt(0)
+; HSA-NOTRAP-GFX900-V2-NEXT:    s_endpgm
+;
+; HSA-NOTRAP-GFX900-V3-LABEL: trap:
+; HSA-NOTRAP-GFX900-V3:       ; %bb.0:
+; HSA-NOTRAP-GFX900-V3-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-NOTRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v0, 0
+; HSA-NOTRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v1, 1
+; HSA-NOTRAP-GFX900-V3-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-NOTRAP-GFX900-V3-NEXT:    global_store_dword v0, v1, s[0:1]
+; HSA-NOTRAP-GFX900-V3-NEXT:    s_waitcnt vmcnt(0)
+; HSA-NOTRAP-GFX900-V3-NEXT:    s_endpgm
+;
+; HSA-NOTRAP-GFX900-V4-LABEL: trap:
+; HSA-NOTRAP-GFX900-V4:       ; %bb.0:
+; HSA-NOTRAP-GFX900-V4-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-NOTRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v0, 0
+; HSA-NOTRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v1, 1
+; HSA-NOTRAP-GFX900-V4-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-NOTRAP-GFX900-V4-NEXT:    global_store_dword v0, v1, s[0:1]
+; HSA-NOTRAP-GFX900-V4-NEXT:    s_waitcnt vmcnt(0)
+; HSA-NOTRAP-GFX900-V4-NEXT:    s_endpgm
+  store volatile i32 1, i32 addrspace(1)* %arg0
+  call void @llvm.trap()
+  unreachable
+  store volatile i32 2, i32 addrspace(1)* %arg0
+  ret void
+}
+
+define amdgpu_kernel void @non_entry_trap(i32 addrspace(1)* nocapture readonly %arg0) local_unnamed_addr {
+; NOHSA-TRAP-GFX900-V2-LABEL: non_entry_trap:
+; NOHSA-TRAP-GFX900-V2:       ; %bb.0: ; %entry
+; NOHSA-TRAP-GFX900-V2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; NOHSA-TRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v0, 0
+; NOHSA-TRAP-GFX900-V2-NEXT:    s_waitcnt lgkmcnt(0)
+; NOHSA-TRAP-GFX900-V2-NEXT:    global_load_dword v1, v0, s[0:1] glc
+; NOHSA-TRAP-GFX900-V2-NEXT:    s_waitcnt vmcnt(0)
+; NOHSA-TRAP-GFX900-V2-NEXT:    v_cmp_eq_u32_e32 vcc, -1, v1
+; NOHSA-TRAP-GFX900-V2-NEXT:    s_and_b64 vcc, exec, vcc
+; NOHSA-TRAP-GFX900-V2-NEXT:    s_cbranch_vccz BB1_2
+; NOHSA-TRAP-GFX900-V2-NEXT:  ; %bb.1: ; %ret
+; NOHSA-TRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v1, 3
+; NOHSA-TRAP-GFX900-V2-NEXT:    global_store_dword v0, v1, s[0:1]
+; NOHSA-TRAP-GFX900-V2-NEXT:    s_waitcnt vmcnt(0)
+; NOHSA-TRAP-GFX900-V2-NEXT:    s_endpgm
+; NOHSA-TRAP-GFX900-V2-NEXT:  BB1_2: ; %trap
+; NOHSA-TRAP-GFX900-V2-NEXT:    s_endpgm
+;
+; NOHSA-TRAP-GFX900-V3-LABEL: non_entry_trap:
+; NOHSA-TRAP-GFX900-V3:       ; %bb.0: ; %entry
+; NOHSA-TRAP-GFX900-V3-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; NOHSA-TRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v0, 0
+; NOHSA-TRAP-GFX900-V3-NEXT:    s_waitcnt lgkmcnt(0)
+; NOHSA-TRAP-GFX900-V3-NEXT:    global_load_dword v1, v0, s[0:1] glc
+; NOHSA-TRAP-GFX900-V3-NEXT:    s_waitcnt vmcnt(0)
+; NOHSA-TRAP-GFX900-V3-NEXT:    v_cmp_eq_u32_e32 vcc, -1, v1
+; NOHSA-TRAP-GFX900-V3-NEXT:    s_and_b64 vcc, exec, vcc
+; NOHSA-TRAP-GFX900-V3-NEXT:    s_cbranch_vccz BB1_2
+; NOHSA-TRAP-GFX900-V3-NEXT:  ; %bb.1: ; %ret
+; NOHSA-TRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v1, 3
+; NOHSA-TRAP-GFX900-V3-NEXT:    global_store_dword v0, v1, s[0:1]
+; NOHSA-TRAP-GFX900-V3-NEXT:    s_waitcnt vmcnt(0)
+; NOHSA-TRAP-GFX900-V3-NEXT:    s_endpgm
+; NOHSA-TRAP-GFX900-V3-NEXT:  BB1_2: ; %trap
+; NOHSA-TRAP-GFX900-V3-NEXT:    s_endpgm
+;
+; NOHSA-TRAP-GFX900-V4-LABEL: non_entry_trap:
+; NOHSA-TRAP-GFX900-V4:       ; %bb.0: ; %entry
+; NOHSA-TRAP-GFX900-V4-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; NOHSA-TRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v0, 0
+; NOHSA-TRAP-GFX900-V4-NEXT:    s_waitcnt lgkmcnt(0)
+; NOHSA-TRAP-GFX900-V4-NEXT:    global_load_dword v1, v0, s[0:1] glc
+; NOHSA-TRAP-GFX900-V4-NEXT:    s_waitcnt vmcnt(0)
+; NOHSA-TRAP-GFX900-V4-NEXT:    v_cmp_eq_u32_e32 vcc, -1, v1
+; NOHSA-TRAP-GFX900-V4-NEXT:    s_and_b64 vcc, exec, vcc
+; NOHSA-TRAP-GFX900-V4-NEXT:    s_cbranch_vccz BB1_2
+; NOHSA-TRAP-GFX900-V4-NEXT:  ; %bb.1: ; %ret
+; NOHSA-TRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v1, 3
+; NOHSA-TRAP-GFX900-V4-NEXT:    global_store_dword v0, v1, s[0:1]
+; NOHSA-TRAP-GFX900-V4-NEXT:    s_waitcnt vmcnt(0)
+; NOHSA-TRAP-GFX900-V4-NEXT:    s_endpgm
+; NOHSA-TRAP-GFX900-V4-NEXT:  BB1_2: ; %trap
+; NOHSA-TRAP-GFX900-V4-NEXT:    s_endpgm
+;
+; HSA-TRAP-GFX803-V2-LABEL: non_entry_trap:
+; HSA-TRAP-GFX803-V2:         .amd_kernel_code_t
+; HSA-TRAP-GFX803-V2-NEXT:     amd_code_version_major = 1
+; HSA-TRAP-GFX803-V2-NEXT:     amd_code_version_minor = 2
+; HSA-TRAP-GFX803-V2-NEXT:     amd_machine_kind = 1
+; HSA-TRAP-GFX803-V2-NEXT:     amd_machine_version_major = 8
+; HSA-TRAP-GFX803-V2-NEXT:     amd_machine_version_minor = 0
+; HSA-TRAP-GFX803-V2-NEXT:     amd_machine_version_stepping = 3
+; HSA-TRAP-GFX803-V2-NEXT:     kernel_code_entry_byte_offset = 256
+; HSA-TRAP-GFX803-V2-NEXT:     kernel_code_prefetch_byte_size = 0
+; HSA-TRAP-GFX803-V2-NEXT:     granulated_workitem_vgpr_count = 0
+; HSA-TRAP-GFX803-V2-NEXT:     granulated_wavefront_sgpr_count = 1
+; HSA-TRAP-GFX803-V2-NEXT:     priority = 0
+; HSA-TRAP-GFX803-V2-NEXT:     float_mode = 240
+; HSA-TRAP-GFX803-V2-NEXT:     priv = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_dx10_clamp = 1
+; HSA-TRAP-GFX803-V2-NEXT:     debug_mode = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_ieee_mode = 1
+; HSA-TRAP-GFX803-V2-NEXT:     enable_wgp_mode = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_mem_ordered = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_fwd_progress = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_private_segment_wave_byte_offset = 0
+; HSA-TRAP-GFX803-V2-NEXT:     user_sgpr_count = 8
+; HSA-TRAP-GFX803-V2-NEXT:     enable_trap_handler = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_workgroup_id_x = 1
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_workgroup_id_y = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_workgroup_id_z = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_workgroup_info = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_vgpr_workitem_id = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_exception_msb = 0
+; HSA-TRAP-GFX803-V2-NEXT:     granulated_lds_size = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_exception = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_private_segment_buffer = 1
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_dispatch_ptr = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_queue_ptr = 1
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_kernarg_segment_ptr = 1
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_dispatch_id = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_flat_scratch_init = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_private_segment_size = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_grid_workgroup_count_x = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_grid_workgroup_count_y = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_grid_workgroup_count_z = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_wavefront_size32 = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_ordered_append_gds = 0
+; HSA-TRAP-GFX803-V2-NEXT:     private_element_size = 1
+; HSA-TRAP-GFX803-V2-NEXT:     is_ptr64 = 1
+; HSA-TRAP-GFX803-V2-NEXT:     is_dynamic_callstack = 0
+; HSA-TRAP-GFX803-V2-NEXT:     is_debug_enabled = 0
+; HSA-TRAP-GFX803-V2-NEXT:     is_xnack_enabled = 0
+; HSA-TRAP-GFX803-V2-NEXT:     workitem_private_segment_byte_size = 0
+; HSA-TRAP-GFX803-V2-NEXT:     workgroup_group_segment_byte_size = 0
+; HSA-TRAP-GFX803-V2-NEXT:     gds_segment_byte_size = 0
+; HSA-TRAP-GFX803-V2-NEXT:     kernarg_segment_byte_size = 8
+; HSA-TRAP-GFX803-V2-NEXT:     workgroup_fbarrier_count = 0
+; HSA-TRAP-GFX803-V2-NEXT:     wavefront_sgpr_count = 10
+; HSA-TRAP-GFX803-V2-NEXT:     workitem_vgpr_count = 3
+; HSA-TRAP-GFX803-V2-NEXT:     reserved_vgpr_first = 0
+; HSA-TRAP-GFX803-V2-NEXT:     reserved_vgpr_count = 0
+; HSA-TRAP-GFX803-V2-NEXT:     reserved_sgpr_first = 0
+; HSA-TRAP-GFX803-V2-NEXT:     reserved_sgpr_count = 0
+; HSA-TRAP-GFX803-V2-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
+; HSA-TRAP-GFX803-V2-NEXT:     debug_private_segment_buffer_sgpr = 0
+; HSA-TRAP-GFX803-V2-NEXT:     kernarg_segment_alignment = 4
+; HSA-TRAP-GFX803-V2-NEXT:     group_segment_alignment = 4
+; HSA-TRAP-GFX803-V2-NEXT:     private_segment_alignment = 4
+; HSA-TRAP-GFX803-V2-NEXT:     wavefront_size = 6
+; HSA-TRAP-GFX803-V2-NEXT:     call_convention = -1
+; HSA-TRAP-GFX803-V2-NEXT:     runtime_loader_kernel_symbol = 0
+; HSA-TRAP-GFX803-V2-NEXT:    .end_amd_kernel_code_t
+; HSA-TRAP-GFX803-V2-NEXT:  ; %bb.0: ; %entry
+; HSA-TRAP-GFX803-V2-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-TRAP-GFX803-V2-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX803-V2-NEXT:    v_mov_b32_e32 v0, s0
+; HSA-TRAP-GFX803-V2-NEXT:    v_mov_b32_e32 v1, s1
+; HSA-TRAP-GFX803-V2-NEXT:    flat_load_dword v0, v[0:1] glc
+; HSA-TRAP-GFX803-V2-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX803-V2-NEXT:    v_cmp_eq_u32_e32 vcc, -1, v0
+; HSA-TRAP-GFX803-V2-NEXT:    s_and_b64 vcc, exec, vcc
+; HSA-TRAP-GFX803-V2-NEXT:    s_cbranch_vccz BB1_2
+; HSA-TRAP-GFX803-V2-NEXT:  ; %bb.1: ; %ret
+; HSA-TRAP-GFX803-V2-NEXT:    v_mov_b32_e32 v0, s0
+; HSA-TRAP-GFX803-V2-NEXT:    v_mov_b32_e32 v2, 3
+; HSA-TRAP-GFX803-V2-NEXT:    v_mov_b32_e32 v1, s1
+; HSA-TRAP-GFX803-V2-NEXT:    flat_store_dword v[0:1], v2
+; HSA-TRAP-GFX803-V2-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX803-V2-NEXT:    s_endpgm
+; HSA-TRAP-GFX803-V2-NEXT:  BB1_2: ; %trap
+; HSA-TRAP-GFX803-V2-NEXT:    s_mov_b64 s[0:1], s[4:5]
+; HSA-TRAP-GFX803-V2-NEXT:    s_trap 2
+;
+; HSA-TRAP-GFX803-V3-LABEL: non_entry_trap:
+; HSA-TRAP-GFX803-V3:       ; %bb.0: ; %entry
+; HSA-TRAP-GFX803-V3-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-TRAP-GFX803-V3-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX803-V3-NEXT:    v_mov_b32_e32 v0, s0
+; HSA-TRAP-GFX803-V3-NEXT:    v_mov_b32_e32 v1, s1
+; HSA-TRAP-GFX803-V3-NEXT:    flat_load_dword v0, v[0:1] glc
+; HSA-TRAP-GFX803-V3-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX803-V3-NEXT:    v_cmp_eq_u32_e32 vcc, -1, v0
+; HSA-TRAP-GFX803-V3-NEXT:    s_and_b64 vcc, exec, vcc
+; HSA-TRAP-GFX803-V3-NEXT:    s_cbranch_vccz BB1_2
+; HSA-TRAP-GFX803-V3-NEXT:  ; %bb.1: ; %ret
+; HSA-TRAP-GFX803-V3-NEXT:    v_mov_b32_e32 v0, s0
+; HSA-TRAP-GFX803-V3-NEXT:    v_mov_b32_e32 v2, 3
+; HSA-TRAP-GFX803-V3-NEXT:    v_mov_b32_e32 v1, s1
+; HSA-TRAP-GFX803-V3-NEXT:    flat_store_dword v[0:1], v2
+; HSA-TRAP-GFX803-V3-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX803-V3-NEXT:    s_endpgm
+; HSA-TRAP-GFX803-V3-NEXT:  BB1_2: ; %trap
+; HSA-TRAP-GFX803-V3-NEXT:    s_mov_b64 s[0:1], s[4:5]
+; HSA-TRAP-GFX803-V3-NEXT:    s_trap 2
+;
+; HSA-TRAP-GFX803-V4-LABEL: non_entry_trap:
+; HSA-TRAP-GFX803-V4:       ; %bb.0: ; %entry
+; HSA-TRAP-GFX803-V4-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-TRAP-GFX803-V4-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX803-V4-NEXT:    v_mov_b32_e32 v0, s0
+; HSA-TRAP-GFX803-V4-NEXT:    v_mov_b32_e32 v1, s1
+; HSA-TRAP-GFX803-V4-NEXT:    flat_load_dword v0, v[0:1] glc
+; HSA-TRAP-GFX803-V4-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX803-V4-NEXT:    v_cmp_eq_u32_e32 vcc, -1, v0
+; HSA-TRAP-GFX803-V4-NEXT:    s_and_b64 vcc, exec, vcc
+; HSA-TRAP-GFX803-V4-NEXT:    s_cbranch_vccz BB1_2
+; HSA-TRAP-GFX803-V4-NEXT:  ; %bb.1: ; %ret
+; HSA-TRAP-GFX803-V4-NEXT:    v_mov_b32_e32 v0, s0
+; HSA-TRAP-GFX803-V4-NEXT:    v_mov_b32_e32 v2, 3
+; HSA-TRAP-GFX803-V4-NEXT:    v_mov_b32_e32 v1, s1
+; HSA-TRAP-GFX803-V4-NEXT:    flat_store_dword v[0:1], v2
+; HSA-TRAP-GFX803-V4-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX803-V4-NEXT:    s_endpgm
+; HSA-TRAP-GFX803-V4-NEXT:  BB1_2: ; %trap
+; HSA-TRAP-GFX803-V4-NEXT:    s_mov_b64 s[0:1], s[4:5]
+; HSA-TRAP-GFX803-V4-NEXT:    s_trap 2
+;
+; HSA-TRAP-GFX900-V2-LABEL: non_entry_trap:
+; HSA-TRAP-GFX900-V2:         .amd_kernel_code_t
+; HSA-TRAP-GFX900-V2-NEXT:     amd_code_version_major = 1
+; HSA-TRAP-GFX900-V2-NEXT:     amd_code_version_minor = 2
+; HSA-TRAP-GFX900-V2-NEXT:     amd_machine_kind = 1
+; HSA-TRAP-GFX900-V2-NEXT:     amd_machine_version_major = 9
+; HSA-TRAP-GFX900-V2-NEXT:     amd_machine_version_minor = 0
+; HSA-TRAP-GFX900-V2-NEXT:     amd_machine_version_stepping = 0
+; HSA-TRAP-GFX900-V2-NEXT:     kernel_code_entry_byte_offset = 256
+; HSA-TRAP-GFX900-V2-NEXT:     kernel_code_prefetch_byte_size = 0
+; HSA-TRAP-GFX900-V2-NEXT:     granulated_workitem_vgpr_count = 0
+; HSA-TRAP-GFX900-V2-NEXT:     granulated_wavefront_sgpr_count = 1
+; HSA-TRAP-GFX900-V2-NEXT:     priority = 0
+; HSA-TRAP-GFX900-V2-NEXT:     float_mode = 240
+; HSA-TRAP-GFX900-V2-NEXT:     priv = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_dx10_clamp = 1
+; HSA-TRAP-GFX900-V2-NEXT:     debug_mode = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_ieee_mode = 1
+; HSA-TRAP-GFX900-V2-NEXT:     enable_wgp_mode = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_mem_ordered = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_fwd_progress = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_private_segment_wave_byte_offset = 0
+; HSA-TRAP-GFX900-V2-NEXT:     user_sgpr_count = 8
+; HSA-TRAP-GFX900-V2-NEXT:     enable_trap_handler = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_id_x = 1
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_id_y = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_id_z = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_info = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_vgpr_workitem_id = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_exception_msb = 0
+; HSA-TRAP-GFX900-V2-NEXT:     granulated_lds_size = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_exception = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_private_segment_buffer = 1
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_dispatch_ptr = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_queue_ptr = 1
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_kernarg_segment_ptr = 1
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_dispatch_id = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_flat_scratch_init = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_private_segment_size = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_grid_workgroup_count_x = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_grid_workgroup_count_y = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_grid_workgroup_count_z = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_wavefront_size32 = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_ordered_append_gds = 0
+; HSA-TRAP-GFX900-V2-NEXT:     private_element_size = 1
+; HSA-TRAP-GFX900-V2-NEXT:     is_ptr64 = 1
+; HSA-TRAP-GFX900-V2-NEXT:     is_dynamic_callstack = 0
+; HSA-TRAP-GFX900-V2-NEXT:     is_debug_enabled = 0
+; HSA-TRAP-GFX900-V2-NEXT:     is_xnack_enabled = 1
+; HSA-TRAP-GFX900-V2-NEXT:     workitem_private_segment_byte_size = 0
+; HSA-TRAP-GFX900-V2-NEXT:     workgroup_group_segment_byte_size = 0
+; HSA-TRAP-GFX900-V2-NEXT:     gds_segment_byte_size = 0
+; HSA-TRAP-GFX900-V2-NEXT:     kernarg_segment_byte_size = 8
+; HSA-TRAP-GFX900-V2-NEXT:     workgroup_fbarrier_count = 0
+; HSA-TRAP-GFX900-V2-NEXT:     wavefront_sgpr_count = 10
+; HSA-TRAP-GFX900-V2-NEXT:     workitem_vgpr_count = 2
+; HSA-TRAP-GFX900-V2-NEXT:     reserved_vgpr_first = 0
+; HSA-TRAP-GFX900-V2-NEXT:     reserved_vgpr_count = 0
+; HSA-TRAP-GFX900-V2-NEXT:     reserved_sgpr_first = 0
+; HSA-TRAP-GFX900-V2-NEXT:     reserved_sgpr_count = 0
+; HSA-TRAP-GFX900-V2-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
+; HSA-TRAP-GFX900-V2-NEXT:     debug_private_segment_buffer_sgpr = 0
+; HSA-TRAP-GFX900-V2-NEXT:     kernarg_segment_alignment = 4
+; HSA-TRAP-GFX900-V2-NEXT:     group_segment_alignment = 4
+; HSA-TRAP-GFX900-V2-NEXT:     private_segment_alignment = 4
+; HSA-TRAP-GFX900-V2-NEXT:     wavefront_size = 6
+; HSA-TRAP-GFX900-V2-NEXT:     call_convention = -1
+; HSA-TRAP-GFX900-V2-NEXT:     runtime_loader_kernel_symbol = 0
+; HSA-TRAP-GFX900-V2-NEXT:    .end_amd_kernel_code_t
+; HSA-TRAP-GFX900-V2-NEXT:  ; %bb.0: ; %entry
+; HSA-TRAP-GFX900-V2-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-TRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v0, 0
+; HSA-TRAP-GFX900-V2-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX900-V2-NEXT:    global_load_dword v1, v0, s[0:1] glc
+; HSA-TRAP-GFX900-V2-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX900-V2-NEXT:    v_cmp_eq_u32_e32 vcc, -1, v1
+; HSA-TRAP-GFX900-V2-NEXT:    s_and_b64 vcc, exec, vcc
+; HSA-TRAP-GFX900-V2-NEXT:    s_cbranch_vccz BB1_2
+; HSA-TRAP-GFX900-V2-NEXT:  ; %bb.1: ; %ret
+; HSA-TRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v1, 3
+; HSA-TRAP-GFX900-V2-NEXT:    global_store_dword v0, v1, s[0:1]
+; HSA-TRAP-GFX900-V2-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX900-V2-NEXT:    s_endpgm
+; HSA-TRAP-GFX900-V2-NEXT:  BB1_2: ; %trap
+; HSA-TRAP-GFX900-V2-NEXT:    s_mov_b64 s[0:1], s[4:5]
+; HSA-TRAP-GFX900-V2-NEXT:    s_trap 2
+;
+; HSA-TRAP-GFX900-V3-LABEL: non_entry_trap:
+; HSA-TRAP-GFX900-V3:       ; %bb.0: ; %entry
+; HSA-TRAP-GFX900-V3-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-TRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v0, 0
+; HSA-TRAP-GFX900-V3-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX900-V3-NEXT:    global_load_dword v1, v0, s[0:1] glc
+; HSA-TRAP-GFX900-V3-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX900-V3-NEXT:    v_cmp_eq_u32_e32 vcc, -1, v1
+; HSA-TRAP-GFX900-V3-NEXT:    s_and_b64 vcc, exec, vcc
+; HSA-TRAP-GFX900-V3-NEXT:    s_cbranch_vccz BB1_2
+; HSA-TRAP-GFX900-V3-NEXT:  ; %bb.1: ; %ret
+; HSA-TRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v1, 3
+; HSA-TRAP-GFX900-V3-NEXT:    global_store_dword v0, v1, s[0:1]
+; HSA-TRAP-GFX900-V3-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX900-V3-NEXT:    s_endpgm
+; HSA-TRAP-GFX900-V3-NEXT:  BB1_2: ; %trap
+; HSA-TRAP-GFX900-V3-NEXT:    s_mov_b64 s[0:1], s[4:5]
+; HSA-TRAP-GFX900-V3-NEXT:    s_trap 2
+;
+; HSA-TRAP-GFX900-V4-LABEL: non_entry_trap:
+; HSA-TRAP-GFX900-V4:       ; %bb.0: ; %entry
+; HSA-TRAP-GFX900-V4-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-TRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v0, 0
+; HSA-TRAP-GFX900-V4-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX900-V4-NEXT:    global_load_dword v1, v0, s[0:1] glc
+; HSA-TRAP-GFX900-V4-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX900-V4-NEXT:    v_cmp_eq_u32_e32 vcc, -1, v1
+; HSA-TRAP-GFX900-V4-NEXT:    s_and_b64 vcc, exec, vcc
+; HSA-TRAP-GFX900-V4-NEXT:    s_cbranch_vccz BB1_2
+; HSA-TRAP-GFX900-V4-NEXT:  ; %bb.1: ; %ret
+; HSA-TRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v1, 3
+; HSA-TRAP-GFX900-V4-NEXT:    global_store_dword v0, v1, s[0:1]
+; HSA-TRAP-GFX900-V4-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX900-V4-NEXT:    s_endpgm
+; HSA-TRAP-GFX900-V4-NEXT:  BB1_2: ; %trap
+; HSA-TRAP-GFX900-V4-NEXT:    s_trap 2
+;
+; HSA-NOTRAP-GFX900-V2-LABEL: non_entry_trap:
+; HSA-NOTRAP-GFX900-V2:         .amd_kernel_code_t
+; HSA-NOTRAP-GFX900-V2-NEXT:     amd_code_version_major = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     amd_code_version_minor = 2
+; HSA-NOTRAP-GFX900-V2-NEXT:     amd_machine_kind = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     amd_machine_version_major = 9
+; HSA-NOTRAP-GFX900-V2-NEXT:     amd_machine_version_minor = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     amd_machine_version_stepping = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     kernel_code_entry_byte_offset = 256
+; HSA-NOTRAP-GFX900-V2-NEXT:     kernel_code_prefetch_byte_size = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     granulated_workitem_vgpr_count = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     granulated_wavefront_sgpr_count = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     priority = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     float_mode = 240
+; HSA-NOTRAP-GFX900-V2-NEXT:     priv = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_dx10_clamp = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     debug_mode = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_ieee_mode = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_wgp_mode = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_mem_ordered = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_fwd_progress = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_private_segment_wave_byte_offset = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     user_sgpr_count = 8
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_trap_handler = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_id_x = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_id_y = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_id_z = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_info = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_vgpr_workitem_id = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_exception_msb = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     granulated_lds_size = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_exception = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_private_segment_buffer = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_dispatch_ptr = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_queue_ptr = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_kernarg_segment_ptr = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_dispatch_id = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_flat_scratch_init = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_private_segment_size = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_grid_workgroup_count_x = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_grid_workgroup_count_y = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_grid_workgroup_count_z = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_wavefront_size32 = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_ordered_append_gds = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     private_element_size = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     is_ptr64 = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     is_dynamic_callstack = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     is_debug_enabled = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     is_xnack_enabled = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     workitem_private_segment_byte_size = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     workgroup_group_segment_byte_size = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     gds_segment_byte_size = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     kernarg_segment_byte_size = 8
+; HSA-NOTRAP-GFX900-V2-NEXT:     workgroup_fbarrier_count = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     wavefront_sgpr_count = 10
+; HSA-NOTRAP-GFX900-V2-NEXT:     workitem_vgpr_count = 2
+; HSA-NOTRAP-GFX900-V2-NEXT:     reserved_vgpr_first = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     reserved_vgpr_count = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     reserved_sgpr_first = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     reserved_sgpr_count = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     debug_private_segment_buffer_sgpr = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     kernarg_segment_alignment = 4
+; HSA-NOTRAP-GFX900-V2-NEXT:     group_segment_alignment = 4
+; HSA-NOTRAP-GFX900-V2-NEXT:     private_segment_alignment = 4
+; HSA-NOTRAP-GFX900-V2-NEXT:     wavefront_size = 6
+; HSA-NOTRAP-GFX900-V2-NEXT:     call_convention = -1
+; HSA-NOTRAP-GFX900-V2-NEXT:     runtime_loader_kernel_symbol = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:    .end_amd_kernel_code_t
+; HSA-NOTRAP-GFX900-V2-NEXT:  ; %bb.0: ; %entry
+; HSA-NOTRAP-GFX900-V2-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-NOTRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v0, 0
+; HSA-NOTRAP-GFX900-V2-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-NOTRAP-GFX900-V2-NEXT:    global_load_dword v1, v0, s[0:1] glc
+; HSA-NOTRAP-GFX900-V2-NEXT:    s_waitcnt vmcnt(0)
+; HSA-NOTRAP-GFX900-V2-NEXT:    v_cmp_eq_u32_e32 vcc, -1, v1
+; HSA-NOTRAP-GFX900-V2-NEXT:    s_and_b64 vcc, exec, vcc
+; HSA-NOTRAP-GFX900-V2-NEXT:    s_cbranch_vccz BB1_2
+; HSA-NOTRAP-GFX900-V2-NEXT:  ; %bb.1: ; %ret
+; HSA-NOTRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v1, 3
+; HSA-NOTRAP-GFX900-V2-NEXT:    global_store_dword v0, v1, s[0:1]
+; HSA-NOTRAP-GFX900-V2-NEXT:    s_waitcnt vmcnt(0)
+; HSA-NOTRAP-GFX900-V2-NEXT:    s_endpgm
+; HSA-NOTRAP-GFX900-V2-NEXT:  BB1_2: ; %trap
+; HSA-NOTRAP-GFX900-V2-NEXT:    s_endpgm
+;
+; HSA-NOTRAP-GFX900-V3-LABEL: non_entry_trap:
+; HSA-NOTRAP-GFX900-V3:       ; %bb.0: ; %entry
+; HSA-NOTRAP-GFX900-V3-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-NOTRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v0, 0
+; HSA-NOTRAP-GFX900-V3-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-NOTRAP-GFX900-V3-NEXT:    global_load_dword v1, v0, s[0:1] glc
+; HSA-NOTRAP-GFX900-V3-NEXT:    s_waitcnt vmcnt(0)
+; HSA-NOTRAP-GFX900-V3-NEXT:    v_cmp_eq_u32_e32 vcc, -1, v1
+; HSA-NOTRAP-GFX900-V3-NEXT:    s_and_b64 vcc, exec, vcc
+; HSA-NOTRAP-GFX900-V3-NEXT:    s_cbranch_vccz BB1_2
+; HSA-NOTRAP-GFX900-V3-NEXT:  ; %bb.1: ; %ret
+; HSA-NOTRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v1, 3
+; HSA-NOTRAP-GFX900-V3-NEXT:    global_store_dword v0, v1, s[0:1]
+; HSA-NOTRAP-GFX900-V3-NEXT:    s_waitcnt vmcnt(0)
+; HSA-NOTRAP-GFX900-V3-NEXT:    s_endpgm
+; HSA-NOTRAP-GFX900-V3-NEXT:  BB1_2: ; %trap
+; HSA-NOTRAP-GFX900-V3-NEXT:    s_endpgm
+;
+; HSA-NOTRAP-GFX900-V4-LABEL: non_entry_trap:
+; HSA-NOTRAP-GFX900-V4:       ; %bb.0: ; %entry
+; HSA-NOTRAP-GFX900-V4-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-NOTRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v0, 0
+; HSA-NOTRAP-GFX900-V4-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-NOTRAP-GFX900-V4-NEXT:    global_load_dword v1, v0, s[0:1] glc
+; HSA-NOTRAP-GFX900-V4-NEXT:    s_waitcnt vmcnt(0)
+; HSA-NOTRAP-GFX900-V4-NEXT:    v_cmp_eq_u32_e32 vcc, -1, v1
+; HSA-NOTRAP-GFX900-V4-NEXT:    s_and_b64 vcc, exec, vcc
+; HSA-NOTRAP-GFX900-V4-NEXT:    s_cbranch_vccz BB1_2
+; HSA-NOTRAP-GFX900-V4-NEXT:  ; %bb.1: ; %ret
+; HSA-NOTRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v1, 3
+; HSA-NOTRAP-GFX900-V4-NEXT:    global_store_dword v0, v1, s[0:1]
+; HSA-NOTRAP-GFX900-V4-NEXT:    s_waitcnt vmcnt(0)
+; HSA-NOTRAP-GFX900-V4-NEXT:    s_endpgm
+; HSA-NOTRAP-GFX900-V4-NEXT:  BB1_2: ; %trap
+; HSA-NOTRAP-GFX900-V4-NEXT:    s_endpgm
+entry:
+  %tmp29 = load volatile i32, i32 addrspace(1)* %arg0
+  %cmp = icmp eq i32 %tmp29, -1
+  br i1 %cmp, label %ret, label %trap
+
+trap:
+  call void @llvm.trap()
+  unreachable
+
+ret:
+  store volatile i32 3, i32 addrspace(1)* %arg0
+  ret void
+}
+
+define amdgpu_kernel void @debugtrap(i32 addrspace(1)* nocapture readonly %arg0) {
+; NOHSA-TRAP-GFX900-V2-LABEL: debugtrap:
+; NOHSA-TRAP-GFX900-V2:       ; %bb.0:
+; NOHSA-TRAP-GFX900-V2-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; NOHSA-TRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v0, 0
+; NOHSA-TRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v1, 1
+; NOHSA-TRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v2, 2
+; NOHSA-TRAP-GFX900-V2-NEXT:    s_waitcnt lgkmcnt(0)
+; NOHSA-TRAP-GFX900-V2-NEXT:    global_store_dword v0, v1, s[0:1]
+; NOHSA-TRAP-GFX900-V2-NEXT:    s_waitcnt vmcnt(0)
+; NOHSA-TRAP-GFX900-V2-NEXT:    global_store_dword v0, v2, s[0:1]
+; NOHSA-TRAP-GFX900-V2-NEXT:    s_waitcnt vmcnt(0)
+; NOHSA-TRAP-GFX900-V2-NEXT:    s_endpgm
+;
+; NOHSA-TRAP-GFX900-V3-LABEL: debugtrap:
+; NOHSA-TRAP-GFX900-V3:       ; %bb.0:
+; NOHSA-TRAP-GFX900-V3-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; NOHSA-TRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v0, 0
+; NOHSA-TRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v1, 1
+; NOHSA-TRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v2, 2
+; NOHSA-TRAP-GFX900-V3-NEXT:    s_waitcnt lgkmcnt(0)
+; NOHSA-TRAP-GFX900-V3-NEXT:    global_store_dword v0, v1, s[0:1]
+; NOHSA-TRAP-GFX900-V3-NEXT:    s_waitcnt vmcnt(0)
+; NOHSA-TRAP-GFX900-V3-NEXT:    global_store_dword v0, v2, s[0:1]
+; NOHSA-TRAP-GFX900-V3-NEXT:    s_waitcnt vmcnt(0)
+; NOHSA-TRAP-GFX900-V3-NEXT:    s_endpgm
+;
+; NOHSA-TRAP-GFX900-V4-LABEL: debugtrap:
+; NOHSA-TRAP-GFX900-V4:       ; %bb.0:
+; NOHSA-TRAP-GFX900-V4-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
+; NOHSA-TRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v0, 0
+; NOHSA-TRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v1, 1
+; NOHSA-TRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v2, 2
+; NOHSA-TRAP-GFX900-V4-NEXT:    s_waitcnt lgkmcnt(0)
+; NOHSA-TRAP-GFX900-V4-NEXT:    global_store_dword v0, v1, s[0:1]
+; NOHSA-TRAP-GFX900-V4-NEXT:    s_waitcnt vmcnt(0)
+; NOHSA-TRAP-GFX900-V4-NEXT:    global_store_dword v0, v2, s[0:1]
+; NOHSA-TRAP-GFX900-V4-NEXT:    s_waitcnt vmcnt(0)
+; NOHSA-TRAP-GFX900-V4-NEXT:    s_endpgm
+;
+; HSA-TRAP-GFX803-V2-LABEL: debugtrap:
+; HSA-TRAP-GFX803-V2:         .amd_kernel_code_t
+; HSA-TRAP-GFX803-V2-NEXT:     amd_code_version_major = 1
+; HSA-TRAP-GFX803-V2-NEXT:     amd_code_version_minor = 2
+; HSA-TRAP-GFX803-V2-NEXT:     amd_machine_kind = 1
+; HSA-TRAP-GFX803-V2-NEXT:     amd_machine_version_major = 8
+; HSA-TRAP-GFX803-V2-NEXT:     amd_machine_version_minor = 0
+; HSA-TRAP-GFX803-V2-NEXT:     amd_machine_version_stepping = 3
+; HSA-TRAP-GFX803-V2-NEXT:     kernel_code_entry_byte_offset = 256
+; HSA-TRAP-GFX803-V2-NEXT:     kernel_code_prefetch_byte_size = 0
+; HSA-TRAP-GFX803-V2-NEXT:     granulated_workitem_vgpr_count = 0
+; HSA-TRAP-GFX803-V2-NEXT:     granulated_wavefront_sgpr_count = 0
+; HSA-TRAP-GFX803-V2-NEXT:     priority = 0
+; HSA-TRAP-GFX803-V2-NEXT:     float_mode = 240
+; HSA-TRAP-GFX803-V2-NEXT:     priv = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_dx10_clamp = 1
+; HSA-TRAP-GFX803-V2-NEXT:     debug_mode = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_ieee_mode = 1
+; HSA-TRAP-GFX803-V2-NEXT:     enable_wgp_mode = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_mem_ordered = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_fwd_progress = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_private_segment_wave_byte_offset = 0
+; HSA-TRAP-GFX803-V2-NEXT:     user_sgpr_count = 8
+; HSA-TRAP-GFX803-V2-NEXT:     enable_trap_handler = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_workgroup_id_x = 1
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_workgroup_id_y = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_workgroup_id_z = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_workgroup_info = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_vgpr_workitem_id = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_exception_msb = 0
+; HSA-TRAP-GFX803-V2-NEXT:     granulated_lds_size = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_exception = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_private_segment_buffer = 1
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_dispatch_ptr = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_queue_ptr = 1
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_kernarg_segment_ptr = 1
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_dispatch_id = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_flat_scratch_init = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_private_segment_size = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_grid_workgroup_count_x = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_grid_workgroup_count_y = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_sgpr_grid_workgroup_count_z = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_wavefront_size32 = 0
+; HSA-TRAP-GFX803-V2-NEXT:     enable_ordered_append_gds = 0
+; HSA-TRAP-GFX803-V2-NEXT:     private_element_size = 1
+; HSA-TRAP-GFX803-V2-NEXT:     is_ptr64 = 1
+; HSA-TRAP-GFX803-V2-NEXT:     is_dynamic_callstack = 0
+; HSA-TRAP-GFX803-V2-NEXT:     is_debug_enabled = 0
+; HSA-TRAP-GFX803-V2-NEXT:     is_xnack_enabled = 0
+; HSA-TRAP-GFX803-V2-NEXT:     workitem_private_segment_byte_size = 0
+; HSA-TRAP-GFX803-V2-NEXT:     workgroup_group_segment_byte_size = 0
+; HSA-TRAP-GFX803-V2-NEXT:     gds_segment_byte_size = 0
+; HSA-TRAP-GFX803-V2-NEXT:     kernarg_segment_byte_size = 8
+; HSA-TRAP-GFX803-V2-NEXT:     workgroup_fbarrier_count = 0
+; HSA-TRAP-GFX803-V2-NEXT:     wavefront_sgpr_count = 8
+; HSA-TRAP-GFX803-V2-NEXT:     workitem_vgpr_count = 4
+; HSA-TRAP-GFX803-V2-NEXT:     reserved_vgpr_first = 0
+; HSA-TRAP-GFX803-V2-NEXT:     reserved_vgpr_count = 0
+; HSA-TRAP-GFX803-V2-NEXT:     reserved_sgpr_first = 0
+; HSA-TRAP-GFX803-V2-NEXT:     reserved_sgpr_count = 0
+; HSA-TRAP-GFX803-V2-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
+; HSA-TRAP-GFX803-V2-NEXT:     debug_private_segment_buffer_sgpr = 0
+; HSA-TRAP-GFX803-V2-NEXT:     kernarg_segment_alignment = 4
+; HSA-TRAP-GFX803-V2-NEXT:     group_segment_alignment = 4
+; HSA-TRAP-GFX803-V2-NEXT:     private_segment_alignment = 4
+; HSA-TRAP-GFX803-V2-NEXT:     wavefront_size = 6
+; HSA-TRAP-GFX803-V2-NEXT:     call_convention = -1
+; HSA-TRAP-GFX803-V2-NEXT:     runtime_loader_kernel_symbol = 0
+; HSA-TRAP-GFX803-V2-NEXT:    .end_amd_kernel_code_t
+; HSA-TRAP-GFX803-V2-NEXT:  ; %bb.0:
+; HSA-TRAP-GFX803-V2-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-TRAP-GFX803-V2-NEXT:    v_mov_b32_e32 v2, 1
+; HSA-TRAP-GFX803-V2-NEXT:    v_mov_b32_e32 v3, 2
+; HSA-TRAP-GFX803-V2-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX803-V2-NEXT:    v_mov_b32_e32 v0, s0
+; HSA-TRAP-GFX803-V2-NEXT:    v_mov_b32_e32 v1, s1
+; HSA-TRAP-GFX803-V2-NEXT:    flat_store_dword v[0:1], v2
+; HSA-TRAP-GFX803-V2-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX803-V2-NEXT:    s_trap 3
+; HSA-TRAP-GFX803-V2-NEXT:    flat_store_dword v[0:1], v3
+; HSA-TRAP-GFX803-V2-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX803-V2-NEXT:    s_endpgm
+;
+; HSA-TRAP-GFX803-V3-LABEL: debugtrap:
+; HSA-TRAP-GFX803-V3:       ; %bb.0:
+; HSA-TRAP-GFX803-V3-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-TRAP-GFX803-V3-NEXT:    v_mov_b32_e32 v2, 1
+; HSA-TRAP-GFX803-V3-NEXT:    v_mov_b32_e32 v3, 2
+; HSA-TRAP-GFX803-V3-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX803-V3-NEXT:    v_mov_b32_e32 v0, s0
+; HSA-TRAP-GFX803-V3-NEXT:    v_mov_b32_e32 v1, s1
+; HSA-TRAP-GFX803-V3-NEXT:    flat_store_dword v[0:1], v2
+; HSA-TRAP-GFX803-V3-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX803-V3-NEXT:    s_trap 3
+; HSA-TRAP-GFX803-V3-NEXT:    flat_store_dword v[0:1], v3
+; HSA-TRAP-GFX803-V3-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX803-V3-NEXT:    s_endpgm
+;
+; HSA-TRAP-GFX803-V4-LABEL: debugtrap:
+; HSA-TRAP-GFX803-V4:       ; %bb.0:
+; HSA-TRAP-GFX803-V4-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-TRAP-GFX803-V4-NEXT:    v_mov_b32_e32 v2, 1
+; HSA-TRAP-GFX803-V4-NEXT:    v_mov_b32_e32 v3, 2
+; HSA-TRAP-GFX803-V4-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX803-V4-NEXT:    v_mov_b32_e32 v0, s0
+; HSA-TRAP-GFX803-V4-NEXT:    v_mov_b32_e32 v1, s1
+; HSA-TRAP-GFX803-V4-NEXT:    flat_store_dword v[0:1], v2
+; HSA-TRAP-GFX803-V4-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX803-V4-NEXT:    s_trap 3
+; HSA-TRAP-GFX803-V4-NEXT:    flat_store_dword v[0:1], v3
+; HSA-TRAP-GFX803-V4-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX803-V4-NEXT:    s_endpgm
+;
+; HSA-TRAP-GFX900-V2-LABEL: debugtrap:
+; HSA-TRAP-GFX900-V2:         .amd_kernel_code_t
+; HSA-TRAP-GFX900-V2-NEXT:     amd_code_version_major = 1
+; HSA-TRAP-GFX900-V2-NEXT:     amd_code_version_minor = 2
+; HSA-TRAP-GFX900-V2-NEXT:     amd_machine_kind = 1
+; HSA-TRAP-GFX900-V2-NEXT:     amd_machine_version_major = 9
+; HSA-TRAP-GFX900-V2-NEXT:     amd_machine_version_minor = 0
+; HSA-TRAP-GFX900-V2-NEXT:     amd_machine_version_stepping = 0
+; HSA-TRAP-GFX900-V2-NEXT:     kernel_code_entry_byte_offset = 256
+; HSA-TRAP-GFX900-V2-NEXT:     kernel_code_prefetch_byte_size = 0
+; HSA-TRAP-GFX900-V2-NEXT:     granulated_workitem_vgpr_count = 0
+; HSA-TRAP-GFX900-V2-NEXT:     granulated_wavefront_sgpr_count = 0
+; HSA-TRAP-GFX900-V2-NEXT:     priority = 0
+; HSA-TRAP-GFX900-V2-NEXT:     float_mode = 240
+; HSA-TRAP-GFX900-V2-NEXT:     priv = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_dx10_clamp = 1
+; HSA-TRAP-GFX900-V2-NEXT:     debug_mode = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_ieee_mode = 1
+; HSA-TRAP-GFX900-V2-NEXT:     enable_wgp_mode = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_mem_ordered = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_fwd_progress = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_private_segment_wave_byte_offset = 0
+; HSA-TRAP-GFX900-V2-NEXT:     user_sgpr_count = 8
+; HSA-TRAP-GFX900-V2-NEXT:     enable_trap_handler = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_id_x = 1
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_id_y = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_id_z = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_info = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_vgpr_workitem_id = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_exception_msb = 0
+; HSA-TRAP-GFX900-V2-NEXT:     granulated_lds_size = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_exception = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_private_segment_buffer = 1
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_dispatch_ptr = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_queue_ptr = 1
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_kernarg_segment_ptr = 1
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_dispatch_id = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_flat_scratch_init = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_private_segment_size = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_grid_workgroup_count_x = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_grid_workgroup_count_y = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_sgpr_grid_workgroup_count_z = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_wavefront_size32 = 0
+; HSA-TRAP-GFX900-V2-NEXT:     enable_ordered_append_gds = 0
+; HSA-TRAP-GFX900-V2-NEXT:     private_element_size = 1
+; HSA-TRAP-GFX900-V2-NEXT:     is_ptr64 = 1
+; HSA-TRAP-GFX900-V2-NEXT:     is_dynamic_callstack = 0
+; HSA-TRAP-GFX900-V2-NEXT:     is_debug_enabled = 0
+; HSA-TRAP-GFX900-V2-NEXT:     is_xnack_enabled = 1
+; HSA-TRAP-GFX900-V2-NEXT:     workitem_private_segment_byte_size = 0
+; HSA-TRAP-GFX900-V2-NEXT:     workgroup_group_segment_byte_size = 0
+; HSA-TRAP-GFX900-V2-NEXT:     gds_segment_byte_size = 0
+; HSA-TRAP-GFX900-V2-NEXT:     kernarg_segment_byte_size = 8
+; HSA-TRAP-GFX900-V2-NEXT:     workgroup_fbarrier_count = 0
+; HSA-TRAP-GFX900-V2-NEXT:     wavefront_sgpr_count = 8
+; HSA-TRAP-GFX900-V2-NEXT:     workitem_vgpr_count = 3
+; HSA-TRAP-GFX900-V2-NEXT:     reserved_vgpr_first = 0
+; HSA-TRAP-GFX900-V2-NEXT:     reserved_vgpr_count = 0
+; HSA-TRAP-GFX900-V2-NEXT:     reserved_sgpr_first = 0
+; HSA-TRAP-GFX900-V2-NEXT:     reserved_sgpr_count = 0
+; HSA-TRAP-GFX900-V2-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
+; HSA-TRAP-GFX900-V2-NEXT:     debug_private_segment_buffer_sgpr = 0
+; HSA-TRAP-GFX900-V2-NEXT:     kernarg_segment_alignment = 4
+; HSA-TRAP-GFX900-V2-NEXT:     group_segment_alignment = 4
+; HSA-TRAP-GFX900-V2-NEXT:     private_segment_alignment = 4
+; HSA-TRAP-GFX900-V2-NEXT:     wavefront_size = 6
+; HSA-TRAP-GFX900-V2-NEXT:     call_convention = -1
+; HSA-TRAP-GFX900-V2-NEXT:     runtime_loader_kernel_symbol = 0
+; HSA-TRAP-GFX900-V2-NEXT:    .end_amd_kernel_code_t
+; HSA-TRAP-GFX900-V2-NEXT:  ; %bb.0:
+; HSA-TRAP-GFX900-V2-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-TRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v0, 0
+; HSA-TRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v1, 1
+; HSA-TRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v2, 2
+; HSA-TRAP-GFX900-V2-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX900-V2-NEXT:    global_store_dword v0, v1, s[0:1]
+; HSA-TRAP-GFX900-V2-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX900-V2-NEXT:    s_trap 3
+; HSA-TRAP-GFX900-V2-NEXT:    global_store_dword v0, v2, s[0:1]
+; HSA-TRAP-GFX900-V2-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX900-V2-NEXT:    s_endpgm
+;
+; HSA-TRAP-GFX900-V3-LABEL: debugtrap:
+; HSA-TRAP-GFX900-V3:       ; %bb.0:
+; HSA-TRAP-GFX900-V3-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-TRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v0, 0
+; HSA-TRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v1, 1
+; HSA-TRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v2, 2
+; HSA-TRAP-GFX900-V3-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX900-V3-NEXT:    global_store_dword v0, v1, s[0:1]
+; HSA-TRAP-GFX900-V3-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX900-V3-NEXT:    s_trap 3
+; HSA-TRAP-GFX900-V3-NEXT:    global_store_dword v0, v2, s[0:1]
+; HSA-TRAP-GFX900-V3-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX900-V3-NEXT:    s_endpgm
+;
+; HSA-TRAP-GFX900-V4-LABEL: debugtrap:
+; HSA-TRAP-GFX900-V4:       ; %bb.0:
+; HSA-TRAP-GFX900-V4-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-TRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v0, 0
+; HSA-TRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v1, 1
+; HSA-TRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v2, 2
+; HSA-TRAP-GFX900-V4-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-TRAP-GFX900-V4-NEXT:    global_store_dword v0, v1, s[0:1]
+; HSA-TRAP-GFX900-V4-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX900-V4-NEXT:    s_trap 3
+; HSA-TRAP-GFX900-V4-NEXT:    global_store_dword v0, v2, s[0:1]
+; HSA-TRAP-GFX900-V4-NEXT:    s_waitcnt vmcnt(0)
+; HSA-TRAP-GFX900-V4-NEXT:    s_endpgm
+;
+; HSA-NOTRAP-GFX900-V2-LABEL: debugtrap:
+; HSA-NOTRAP-GFX900-V2:         .amd_kernel_code_t
+; HSA-NOTRAP-GFX900-V2-NEXT:     amd_code_version_major = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     amd_code_version_minor = 2
+; HSA-NOTRAP-GFX900-V2-NEXT:     amd_machine_kind = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     amd_machine_version_major = 9
+; HSA-NOTRAP-GFX900-V2-NEXT:     amd_machine_version_minor = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     amd_machine_version_stepping = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     kernel_code_entry_byte_offset = 256
+; HSA-NOTRAP-GFX900-V2-NEXT:     kernel_code_prefetch_byte_size = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     granulated_workitem_vgpr_count = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     granulated_wavefront_sgpr_count = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     priority = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     float_mode = 240
+; HSA-NOTRAP-GFX900-V2-NEXT:     priv = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_dx10_clamp = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     debug_mode = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_ieee_mode = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_wgp_mode = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_mem_ordered = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_fwd_progress = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_private_segment_wave_byte_offset = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     user_sgpr_count = 8
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_trap_handler = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_id_x = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_id_y = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_id_z = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_workgroup_info = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_vgpr_workitem_id = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_exception_msb = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     granulated_lds_size = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_exception = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_private_segment_buffer = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_dispatch_ptr = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_queue_ptr = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_kernarg_segment_ptr = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_dispatch_id = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_flat_scratch_init = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_private_segment_size = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_grid_workgroup_count_x = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_grid_workgroup_count_y = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_sgpr_grid_workgroup_count_z = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_wavefront_size32 = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     enable_ordered_append_gds = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     private_element_size = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     is_ptr64 = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     is_dynamic_callstack = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     is_debug_enabled = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     is_xnack_enabled = 1
+; HSA-NOTRAP-GFX900-V2-NEXT:     workitem_private_segment_byte_size = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     workgroup_group_segment_byte_size = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     gds_segment_byte_size = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     kernarg_segment_byte_size = 8
+; HSA-NOTRAP-GFX900-V2-NEXT:     workgroup_fbarrier_count = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     wavefront_sgpr_count = 8
+; HSA-NOTRAP-GFX900-V2-NEXT:     workitem_vgpr_count = 3
+; HSA-NOTRAP-GFX900-V2-NEXT:     reserved_vgpr_first = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     reserved_vgpr_count = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     reserved_sgpr_first = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     reserved_sgpr_count = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     debug_wavefront_private_segment_offset_sgpr = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     debug_private_segment_buffer_sgpr = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:     kernarg_segment_alignment = 4
+; HSA-NOTRAP-GFX900-V2-NEXT:     group_segment_alignment = 4
+; HSA-NOTRAP-GFX900-V2-NEXT:     private_segment_alignment = 4
+; HSA-NOTRAP-GFX900-V2-NEXT:     wavefront_size = 6
+; HSA-NOTRAP-GFX900-V2-NEXT:     call_convention = -1
+; HSA-NOTRAP-GFX900-V2-NEXT:     runtime_loader_kernel_symbol = 0
+; HSA-NOTRAP-GFX900-V2-NEXT:    .end_amd_kernel_code_t
+; HSA-NOTRAP-GFX900-V2-NEXT:  ; %bb.0:
+; HSA-NOTRAP-GFX900-V2-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-NOTRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v0, 0
+; HSA-NOTRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v1, 1
+; HSA-NOTRAP-GFX900-V2-NEXT:    v_mov_b32_e32 v2, 2
+; HSA-NOTRAP-GFX900-V2-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-NOTRAP-GFX900-V2-NEXT:    global_store_dword v0, v1, s[0:1]
+; HSA-NOTRAP-GFX900-V2-NEXT:    s_waitcnt vmcnt(0)
+; HSA-NOTRAP-GFX900-V2-NEXT:    global_store_dword v0, v2, s[0:1]
+; HSA-NOTRAP-GFX900-V2-NEXT:    s_waitcnt vmcnt(0)
+; HSA-NOTRAP-GFX900-V2-NEXT:    s_endpgm
+;
+; HSA-NOTRAP-GFX900-V3-LABEL: debugtrap:
+; HSA-NOTRAP-GFX900-V3:       ; %bb.0:
+; HSA-NOTRAP-GFX900-V3-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-NOTRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v0, 0
+; HSA-NOTRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v1, 1
+; HSA-NOTRAP-GFX900-V3-NEXT:    v_mov_b32_e32 v2, 2
+; HSA-NOTRAP-GFX900-V3-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-NOTRAP-GFX900-V3-NEXT:    global_store_dword v0, v1, s[0:1]
+; HSA-NOTRAP-GFX900-V3-NEXT:    s_waitcnt vmcnt(0)
+; HSA-NOTRAP-GFX900-V3-NEXT:    global_store_dword v0, v2, s[0:1]
+; HSA-NOTRAP-GFX900-V3-NEXT:    s_waitcnt vmcnt(0)
+; HSA-NOTRAP-GFX900-V3-NEXT:    s_endpgm
+;
+; HSA-NOTRAP-GFX900-V4-LABEL: debugtrap:
+; HSA-NOTRAP-GFX900-V4:       ; %bb.0:
+; HSA-NOTRAP-GFX900-V4-NEXT:    s_load_dwordx2 s[0:1], s[6:7], 0x0
+; HSA-NOTRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v0, 0
+; HSA-NOTRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v1, 1
+; HSA-NOTRAP-GFX900-V4-NEXT:    v_mov_b32_e32 v2, 2
+; HSA-NOTRAP-GFX900-V4-NEXT:    s_waitcnt lgkmcnt(0)
+; HSA-NOTRAP-GFX900-V4-NEXT:    global_store_dword v0, v1, s[0:1]
+; HSA-NOTRAP-GFX900-V4-NEXT:    s_waitcnt vmcnt(0)
+; HSA-NOTRAP-GFX900-V4-NEXT:    global_store_dword v0, v2, s[0:1]
+; HSA-NOTRAP-GFX900-V4-NEXT:    s_waitcnt vmcnt(0)
+; HSA-NOTRAP-GFX900-V4-NEXT:    s_endpgm
+  store volatile i32 1, i32 addrspace(1)* %arg0
+  call void @llvm.debugtrap()
+  store volatile i32 2, i32 addrspace(1)* %arg0
+  ret void
+}
+
+attributes #0 = { nounwind noreturn }
+attributes #1 = { nounwind }

llvm/test/MC/AMDGPU/hsa-diag-v3.s

-// RUN: not llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx803 -mattr=+xnack -show-encoding %s 2>&1 >/dev/null | FileCheck %s --check-prefixes=GCN,GFX8,NONGFX10,AMDHSA
-// RUN: not llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+xnack -show-encoding %s 2>&1 >/dev/null | FileCheck %s --check-prefixes=GCN,GFX10,AMDHSA
-// RUN: not llvm-mc -triple amdgcn-amd- -mcpu=gfx803 -mattr=+xnack -show-encoding %s 2>&1 >/dev/null | FileCheck %s --check-prefixes=GCN,NONAMDHSA
+// RUN: not llvm-mc --amdhsa-code-object-version=3 -triple amdgcn-amd-amdhsa -mcpu=gfx810 -mattr=+xnack -show-encoding %s 2>&1 >/dev/null | FileCheck %s --check-prefixes=GCN,GFX8,NONGFX10,AMDHSA
+// RUN: not llvm-mc --amdhsa-code-object-version=3 -triple amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+xnack -show-encoding %s 2>&1 >/dev/null | FileCheck %s --check-prefixes=GCN,GFX10,AMDHSA
+// RUN: not llvm-mc --amdhsa-code-object-version=3 -triple amdgcn-amd- -mcpu=gfx810 -mattr=+xnack -show-encoding %s 2>&1 >/dev/null | FileCheck %s --check-prefixes=GCN,NONAMDHSA
 
 .text
 
 // GCN-LABEL: warning: test_target
 // GFX8-NOT: error:
-// GFX10: error: target must match options
-// NONAMDHSA: error: unknown directive
+// GFX10: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa--gfx810+xnack does not match the specified target id amdgcn-amd-amdhsa--gfx1010+xnack
+// NONAMDHSA: error: .amdgcn_target directive's target id amdgcn-amd-amdhsa--gfx810+xnack does not match the specified target id amdgcn-amd-unknown--gfx810
 .warning "test_target"
-.amdgcn_target "amdgcn-amd-amdhsa--gfx803+xnack"
+.amdgcn_target "amdgcn-amd-amdhsa--gfx810+xnack"
 
 // GCN-LABEL: warning: test_amdhsa_kernel_no_name
 // GCN: error: unknown directive
 .warning "test_amdhsa_kernel_no_name"
 .amdhsa_kernel
 .end_amdhsa_kernel
 
 // GCN-LABEL: warning: test_amdhsa_kernel_empty

llvm/test/MC/AMDGPU/hsa-gfx10-v3.s

-// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+xnack < %s | FileCheck --check-prefix=ASM %s
-// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+xnack -filetype=obj < %s > %t
+// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx1010 --amdhsa-code-object-version=3 -mattr=+xnack < %s | FileCheck --check-prefix=ASM %s
+// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx1010 --amdhsa-code-object-version=3 -mattr=+xnack -filetype=obj < %s > %t
 // RUN: llvm-readobj -elf-output-style=GNU -sections -symbols -relocations %t | FileCheck --check-prefix=READOBJ %s
 // RUN: llvm-objdump -s -j .rodata %t | FileCheck --check-prefix=OBJDUMP %s
 
 // READOBJ: Section Headers
 // READOBJ: .text   PROGBITS {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9]+}} AX {{[0-9]+}} {{[0-9]+}} 256
 // READOBJ: .rodata PROGBITS {{[0-9a-f]+}} {{[0-9a-f]+}}        0000c0 {{[0-9]+}}  A {{[0-9]+}} {{[0-9]+}} 64
 
 // READOBJ: Relocation section '.rela.rodata' at offset

 // OBJDUMP: Contents of section .rodata
 // Note, relocation for KERNEL_CODE_ENTRY_BYTE_OFFSET is not resolved here.
 // minimal
 // OBJDUMP-NEXT: 0000 00000000 00000000 00000000 00000000
 // OBJDUMP-NEXT: 0010 00000000 00000000 00000000 00000000
 // OBJDUMP-NEXT: 0020 00000000 00000000 00000000 00000000
 // OBJDUMP-NEXT: 0030 0000ac60 80000000 00000000 00000000
 // complete
-// OBJDUMP-NEXT: 0040 01000000 01000000 00000000 00000000
+// OBJDUMP-NEXT: 0040 01000000 01000000 08000000 00000000
 // OBJDUMP-NEXT: 0050 00000000 00000000 00000000 00000000
 // OBJDUMP-NEXT: 0060 00000000 00000000 00000000 00000000
 // OBJDUMP-NEXT: 0070 015001e4 1f0f007f 7f040000 00000000
 // special_sgpr
 // OBJDUMP-NEXT: 0080 00000000 00000000 00000000 00000000
 // OBJDUMP-NEXT: 0090 00000000 00000000 00000000 00000000
 // OBJDUMP-NEXT: 00a0 00000000 00000000 00000000 00000000
 // OBJDUMP-NEXT: 00b0 00000060 80000000 00000000 00000000

 // ASM-NEXT: .amdhsa_next_free_sgpr 0
 // ASM: .end_amdhsa_kernel
 
 // Test that we can specify all available directives with non-default values.
 .p2align 6
 .amdhsa_kernel complete
   .amdhsa_group_segment_fixed_size 1
   .amdhsa_private_segment_fixed_size 1
+  .amdhsa_kernarg_size 8
   .amdhsa_user_sgpr_private_segment_buffer 1
   .amdhsa_user_sgpr_dispatch_ptr 1
   .amdhsa_user_sgpr_queue_ptr 1
   .amdhsa_user_sgpr_kernarg_segment_ptr 1
   .amdhsa_user_sgpr_dispatch_id 1
   .amdhsa_user_sgpr_flat_scratch_init 1
   .amdhsa_user_sgpr_private_segment_size 1
   .amdhsa_wavefront_size32 1
   .amdhsa_system_sgpr_private_segment_wavefront_offset 1
   .amdhsa_system_sgpr_workgroup_id_x 0
   .amdhsa_system_sgpr_workgroup_id_y 1
   .amdhsa_system_sgpr_workgroup_id_z 1
   .amdhsa_system_sgpr_workgroup_info 1
   .amdhsa_system_vgpr_workitem_id 1
   .amdhsa_next_free_vgpr 9
   .amdhsa_next_free_sgpr 27
   .amdhsa_reserve_vcc 0
   .amdhsa_reserve_flat_scratch 0
-  .amdhsa_reserve_xnack_mask 0
+  .amdhsa_reserve_xnack_mask 1
   .amdhsa_float_round_mode_32 1
   .amdhsa_float_round_mode_16_64 1
   .amdhsa_float_denorm_mode_32 1
   .amdhsa_float_denorm_mode_16_64 0
   .amdhsa_dx10_clamp 0
   .amdhsa_ieee_mode 0
   .amdhsa_fp16_overflow 1
   .amdhsa_workgroup_processor_mode 1
   .amdhsa_memory_ordered 1
   .amdhsa_forward_progress 1
   .amdhsa_exception_fp_ieee_invalid_op 1
   .amdhsa_exception_fp_denorm_src 1
   .amdhsa_exception_fp_ieee_div_zero 1
   .amdhsa_exception_fp_ieee_overflow 1
   .amdhsa_exception_fp_ieee_underflow 1
   .amdhsa_exception_fp_ieee_inexact 1
   .amdhsa_exception_int_div_zero 1
 .end_amdhsa_kernel
 
 // ASM: .amdhsa_kernel complete
 // ASM-NEXT: .amdhsa_group_segment_fixed_size 1
 // ASM-NEXT: .amdhsa_private_segment_fixed_size 1
+// ASM-NEXT: .amdhsa_kernarg_size 8
 // ASM-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
 // ASM-NEXT: .amdhsa_user_sgpr_dispatch_ptr 1
 // ASM-NEXT: .amdhsa_user_sgpr_queue_ptr 1
 // ASM-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 1
 // ASM-NEXT: .amdhsa_user_sgpr_dispatch_id 1
 // ASM-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1
 // ASM-NEXT: .amdhsa_user_sgpr_private_segment_size 1
 // ASM-NEXT: .amdhsa_wavefront_size32 1
 // ASM-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_x 0
 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1
 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_z 1
 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_info 1
 // ASM-NEXT: .amdhsa_system_vgpr_workitem_id 1
 // ASM-NEXT: .amdhsa_next_free_vgpr 9
 // ASM-NEXT: .amdhsa_next_free_sgpr 27
 // ASM-NEXT: .amdhsa_reserve_vcc 0
 // ASM-NEXT: .amdhsa_reserve_flat_scratch 0
-// ASM-NEXT: .amdhsa_reserve_xnack_mask 0
+// ASM-NEXT: .amdhsa_reserve_xnack_mask 1
 // ASM-NEXT: .amdhsa_float_round_mode_32 1
 // ASM-NEXT: .amdhsa_float_round_mode_16_64 1
 // ASM-NEXT: .amdhsa_float_denorm_mode_32 1
 // ASM-NEXT: .amdhsa_float_denorm_mode_16_64 0
 // ASM-NEXT: .amdhsa_dx10_clamp 0
 // ASM-NEXT: .amdhsa_ieee_mode 0
 // ASM-NEXT: .amdhsa_fp16_overflow 1
 // ASM-NEXT: .amdhsa_workgroup_processor_mode 1

 .amdhsa_kernel special_sgpr
   // Same next_free_sgpr as "complete", but...
   .amdhsa_next_free_sgpr 27
   // ...on GFX10+ this should require an additional 6 SGPRs, pushing us from
   // 3 granules to 4
   .amdhsa_reserve_flat_scratch 1
 
   .amdhsa_reserve_vcc 0
-  .amdhsa_reserve_xnack_mask 0
+  .amdhsa_reserve_xnack_mask 1
 
   .amdhsa_float_denorm_mode_16_64 0
   .amdhsa_dx10_clamp 0
   .amdhsa_ieee_mode 0
   .amdhsa_next_free_vgpr 0
 .end_amdhsa_kernel
 
 // ASM: .amdhsa_kernel special_sgpr
 // ASM: .amdhsa_next_free_vgpr 0
 // ASM-NEXT: .amdhsa_next_free_sgpr 27
 // ASM-NEXT: .amdhsa_reserve_vcc 0
-// ASM-NEXT: .amdhsa_reserve_xnack_mask 0
+// ASM-NEXT: .amdhsa_reserve_xnack_mask 1
 // ASM: .amdhsa_float_denorm_mode_16_64 0
 // ASM-NEXT: .amdhsa_dx10_clamp 0
 // ASM-NEXT: .amdhsa_ieee_mode 0
 // ASM: .end_amdhsa_kernel
 
 .section .foo
 
 .byte .amdgcn.gfx_generation_number

llvm/test/MC/AMDGPU/hsa-v3.s

-// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=+xnack < %s | FileCheck --check-prefix=ASM %s
-// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx904 -mattr=+xnack -filetype=obj < %s > %t
+// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx904 --amdhsa-code-object-version=3 -mattr=+xnack < %s | FileCheck --check-prefix=ASM %s
+// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx904 --amdhsa-code-object-version=3 -mattr=+xnack -filetype=obj < %s > %t
 // RUN: llvm-readelf -sections -symbols -relocations %t | FileCheck --check-prefix=READOBJ %s
 // RUN: llvm-objdump -s -j .rodata %t | FileCheck --check-prefix=OBJDUMP %s
 
 // READOBJ: Section Headers
 // READOBJ: .text   PROGBITS {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9]+}} AX {{[0-9]+}} {{[0-9]+}} 256
 // READOBJ: .rodata PROGBITS {{[0-9a-f]+}} {{[0-9a-f]+}}        000100 {{[0-9]+}}  A {{[0-9]+}} {{[0-9]+}} 64
 
 // READOBJ: Relocation section '.rela.rodata' at offset

 // OBJDUMP: Contents of section .rodata
 // Note, relocation for KERNEL_CODE_ENTRY_BYTE_OFFSET is not resolved here.
 // minimal
 // OBJDUMP-NEXT: 0000 00000000 00000000 00000000 00000000
 // OBJDUMP-NEXT: 0010 00000000 00000000 00000000 00000000
 // OBJDUMP-NEXT: 0020 00000000 00000000 00000000 00000000
 // OBJDUMP-NEXT: 0030 0000ac00 80000000 00000000 00000000
 // complete
-// OBJDUMP-NEXT: 0040 01000000 01000000 00000000 00000000
+// OBJDUMP-NEXT: 0040 01000000 01000000 08000000 00000000
 // OBJDUMP-NEXT: 0050 00000000 00000000 00000000 00000000
 // OBJDUMP-NEXT: 0060 00000000 00000000 00000000 00000000
 // OBJDUMP-NEXT: 0070 c2500104 1f0f007f 7f000000 00000000
 // special_sgpr
 // OBJDUMP-NEXT: 0080 00000000 00000000 00000000 00000000
 // OBJDUMP-NEXT: 0090 00000000 00000000 00000000 00000000
 // OBJDUMP-NEXT: 00a0 00000000 00000000 00000000 00000000
 // OBJDUMP-NEXT: 00b0 00010000 80000000 00000000 00000000

 // ASM-NEXT: .amdhsa_next_free_sgpr 0
 // ASM: .end_amdhsa_kernel
 
 // Test that we can specify all available directives with non-default values.
 .p2align 6
 .amdhsa_kernel complete
   .amdhsa_group_segment_fixed_size 1
   .amdhsa_private_segment_fixed_size 1
+  .amdhsa_kernarg_size 8
   .amdhsa_user_sgpr_private_segment_buffer 1
   .amdhsa_user_sgpr_dispatch_ptr 1
   .amdhsa_user_sgpr_queue_ptr 1
   .amdhsa_user_sgpr_kernarg_segment_ptr 1
   .amdhsa_user_sgpr_dispatch_id 1
   .amdhsa_user_sgpr_flat_scratch_init 1
   .amdhsa_user_sgpr_private_segment_size 1
   .amdhsa_system_sgpr_private_segment_wavefront_offset 1
   .amdhsa_system_sgpr_workgroup_id_x 0
   .amdhsa_system_sgpr_workgroup_id_y 1
   .amdhsa_system_sgpr_workgroup_id_z 1
   .amdhsa_system_sgpr_workgroup_info 1
   .amdhsa_system_vgpr_workitem_id 1
   .amdhsa_next_free_vgpr 9
   .amdhsa_next_free_sgpr 27
   .amdhsa_reserve_vcc 0
   .amdhsa_reserve_flat_scratch 0
-  .amdhsa_reserve_xnack_mask 0
+  .amdhsa_reserve_xnack_mask 1
   .amdhsa_float_round_mode_32 1
   .amdhsa_float_round_mode_16_64 1
   .amdhsa_float_denorm_mode_32 1
   .amdhsa_float_denorm_mode_16_64 0
   .amdhsa_dx10_clamp 0
   .amdhsa_ieee_mode 0
   .amdhsa_fp16_overflow 1
   .amdhsa_exception_fp_ieee_invalid_op 1
   .amdhsa_exception_fp_denorm_src 1
   .amdhsa_exception_fp_ieee_div_zero 1
   .amdhsa_exception_fp_ieee_overflow 1
   .amdhsa_exception_fp_ieee_underflow 1
   .amdhsa_exception_fp_ieee_inexact 1
   .amdhsa_exception_int_div_zero 1
 .end_amdhsa_kernel
 
 // ASM: .amdhsa_kernel complete
 // ASM-NEXT: .amdhsa_group_segment_fixed_size 1
 // ASM-NEXT: .amdhsa_private_segment_fixed_size 1
+// ASM-NEXT: .amdhsa_kernarg_size 8
 // ASM-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
 // ASM-NEXT: .amdhsa_user_sgpr_dispatch_ptr 1
 // ASM-NEXT: .amdhsa_user_sgpr_queue_ptr 1
 // ASM-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 1
 // ASM-NEXT: .amdhsa_user_sgpr_dispatch_id 1
 // ASM-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1
 // ASM-NEXT: .amdhsa_user_sgpr_private_segment_size 1
 // ASM-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_x 0
 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1
 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_z 1
 // ASM-NEXT: .amdhsa_system_sgpr_workgroup_info 1
 // ASM-NEXT: .amdhsa_system_vgpr_workitem_id 1
 // ASM-NEXT: .amdhsa_next_free_vgpr 9
 // ASM-NEXT: .amdhsa_next_free_sgpr 27
 // ASM-NEXT: .amdhsa_reserve_vcc 0
 // ASM-NEXT: .amdhsa_reserve_flat_scratch 0
-// ASM-NEXT: .amdhsa_reserve_xnack_mask 0
+// ASM-NEXT: .amdhsa_reserve_xnack_mask 1
 // ASM-NEXT: .amdhsa_float_round_mode_32 1
 // ASM-NEXT: .amdhsa_float_round_mode_16_64 1
 // ASM-NEXT: .amdhsa_float_denorm_mode_32 1
 // ASM-NEXT: .amdhsa_float_denorm_mode_16_64 0
 // ASM-NEXT: .amdhsa_dx10_clamp 0
 // ASM-NEXT: .amdhsa_ieee_mode 0
 // ASM-NEXT: .amdhsa_fp16_overflow 1
 // ASM-NEXT: .amdhsa_exception_fp_ieee_invalid_op 1

 .amdhsa_kernel special_sgpr
   // Same next_free_sgpr as "complete", but...
   .amdhsa_next_free_sgpr 27
   // ...on GFX9 this should require an additional 6 SGPRs, pushing us from
   // 3 granules to 4
   .amdhsa_reserve_flat_scratch 1
 
   .amdhsa_reserve_vcc 0
-  .amdhsa_reserve_xnack_mask 0
+  .amdhsa_reserve_xnack_mask 1
 
   .amdhsa_float_denorm_mode_16_64 0
   .amdhsa_dx10_clamp 0
   .amdhsa_ieee_mode 0
   .amdhsa_next_free_vgpr 0
 .end_amdhsa_kernel
 
 // ASM: .amdhsa_kernel special_sgpr
 // ASM: .amdhsa_next_free_vgpr 0
 // ASM-NEXT: .amdhsa_next_free_sgpr 27
 // ASM-NEXT: .amdhsa_reserve_vcc 0
-// ASM-NEXT: .amdhsa_reserve_xnack_mask 0
+// ASM-NEXT: .amdhsa_reserve_xnack_mask 1
 // ASM: .amdhsa_float_denorm_mode_16_64 0
 // ASM-NEXT: .amdhsa_dx10_clamp 0
 // ASM-NEXT: .amdhsa_ieee_mode 0
 // ASM: .end_amdhsa_kernel
 
 // Test that explicitly disabling user_sgpr's does not affect the user_sgpr
 // count, i.e. this should produce the same descriptor as minimal.
 .p2align 6

llvm/test/MC/AMDGPU/hsa-v4.s

+// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx904 --amdhsa-code-object-version=4 -mattr=+xnack < %s | FileCheck --check-prefix=ASM %s
+// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx904 --amdhsa-code-object-version=4 -mattr=+xnack -filetype=obj < %s > %t
+// RUN: llvm-readelf -sections -symbols -relocations %t | FileCheck --check-prefix=READOBJ %s
+// RUN: llvm-objdump -s -j .rodata %t | FileCheck --check-prefix=OBJDUMP %s
+
+// READOBJ: Section Headers
+// READOBJ: .text   PROGBITS {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9a-f]+}} {{[0-9]+}} AX {{[0-9]+}} {{[0-9]+}} 256
+// READOBJ: .rodata PROGBITS {{[0-9a-f]+}} {{[0-9a-f]+}}        000100 {{[0-9]+}}  A {{[0-9]+}} {{[0-9]+}} 64
+
+// READOBJ: Relocation section '.rela.rodata' at offset
+// READOBJ: 0000000000000010 {{[0-9a-f]+}}00000005 R_AMDGPU_REL64 0000000000000000 .text + 10
+// READOBJ: 0000000000000050 {{[0-9a-f]+}}00000005 R_AMDGPU_REL64 0000000000000000 .text + 110
+// READOBJ: 0000000000000090 {{[0-9a-f]+}}00000005 R_AMDGPU_REL64 0000000000000000 .text + 210
+// READOBJ: 00000000000000d0 {{[0-9a-f]+}}00000005 R_AMDGPU_REL64 0000000000000000 .text + 310
+
+// READOBJ: Symbol table '.symtab' contains {{[0-9]+}} entries:
+// READOBJ: {{[0-9]+}}: 0000000000000100  0 FUNC    LOCAL  PROTECTED 2 complete
+// READOBJ: {{[0-9]+}}: 0000000000000040 64 OBJECT  LOCAL  DEFAULT   3 complete.kd
+// READOBJ: {{[0-9]+}}: 0000000000000300  0 FUNC    LOCAL  PROTECTED 2 disabled_user_sgpr
+// READOBJ: {{[0-9]+}}: 00000000000000c0 64 OBJECT  LOCAL  DEFAULT   3 disabled_user_sgpr.kd
+// READOBJ: {{[0-9]+}}: 0000000000000000  0 FUNC    LOCAL  PROTECTED 2 minimal
+// READOBJ: {{[0-9]+}}: 0000000000000000 64 OBJECT  LOCAL  DEFAULT   3 minimal.kd
+// READOBJ: {{[0-9]+}}: 0000000000000200  0 FUNC    LOCAL  PROTECTED 2 special_sgpr
+// READOBJ: {{[0-9]+}}: 0000000000000080 64 OBJECT  LOCAL  DEFAULT   3 special_sgpr.kd
+
+// OBJDUMP: Contents of section .rodata
+// Note, relocation for KERNEL_CODE_ENTRY_BYTE_OFFSET is not resolved here.
+// minimal
+// OBJDUMP-NEXT: 0000 00000000 00000000 00000000 00000000
+// OBJDUMP-NEXT: 0010 00000000 00000000 00000000 00000000
+// OBJDUMP-NEXT: 0020 00000000 00000000 00000000 00000000
+// OBJDUMP-NEXT: 0030 0000ac00 80000000 00000000 00000000
+// complete
+// OBJDUMP-NEXT: 0040 01000000 01000000 08000000 00000000
+// OBJDUMP-NEXT: 0050 00000000 00000000 00000000 00000000
+// OBJDUMP-NEXT: 0060 00000000 00000000 00000000 00000000
+// OBJDUMP-NEXT: 0070 c2500104 1f0f007f 7f000000 00000000
+// special_sgpr
+// OBJDUMP-NEXT: 0080 00000000 00000000 00000000 00000000
+// OBJDUMP-NEXT: 0090 00000000 00000000 00000000 00000000
+// OBJDUMP-NEXT: 00a0 00000000 00000000 00000000 00000000
+// OBJDUMP-NEXT: 00b0 00010000 80000000 00000000 00000000
+// disabled_user_sgpr
+// OBJDUMP-NEXT: 00c0 00000000 00000000 00000000 00000000
+// OBJDUMP-NEXT: 00d0 00000000 00000000 00000000 00000000
+// OBJDUMP-NEXT: 00e0 00000000 00000000 00000000 00000000
+// OBJDUMP-NEXT: 00f0 0000ac00 80000000 00000000 00000000
+
+.text
+// ASM: .text
+
+.amdgcn_target "amdgcn-amd-amdhsa--gfx904:xnack+"
+// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx904:xnack+"
+
+.p2align 8
+.type minimal,@function
+minimal:
+  s_endpgm
+
+.p2align 8
+.type complete,@function
+complete:
+  s_endpgm
+
+.p2align 8
+.type special_sgpr,@function
+special_sgpr:
+  s_endpgm
+
+.p2align 8
+.type disabled_user_sgpr,@function
+disabled_user_sgpr:
+  s_endpgm
+
+.rodata
+// ASM: .rodata
+
+// Test that only specifying required directives is allowed, and that defaulted
+// values are omitted.
+.p2align 6
+.amdhsa_kernel minimal
+  .amdhsa_next_free_vgpr 0
+  .amdhsa_next_free_sgpr 0
+.end_amdhsa_kernel
+
+// ASM: .amdhsa_kernel minimal
+// ASM: .amdhsa_next_free_vgpr 0
+// ASM-NEXT: .amdhsa_next_free_sgpr 0
+// ASM: .end_amdhsa_kernel
+
+// Test that we can specify all available directives with non-default values.
+.p2align 6
+.amdhsa_kernel complete
+  .amdhsa_group_segment_fixed_size 1
+  .amdhsa_private_segment_fixed_size 1
+  .amdhsa_kernarg_size 8
+  .amdhsa_user_sgpr_private_segment_buffer 1
+  .amdhsa_user_sgpr_dispatch_ptr 1
+  .amdhsa_user_sgpr_queue_ptr 1
+  .amdhsa_user_sgpr_kernarg_segment_ptr 1
+  .amdhsa_user_sgpr_dispatch_id 1
+  .amdhsa_user_sgpr_flat_scratch_init 1
+  .amdhsa_user_sgpr_private_segment_size 1
+  .amdhsa_system_sgpr_private_segment_wavefront_offset 1
+  .amdhsa_system_sgpr_workgroup_id_x 0
+  .amdhsa_system_sgpr_workgroup_id_y 1
+  .amdhsa_system_sgpr_workgroup_id_z 1
+  .amdhsa_system_sgpr_workgroup_info 1
+  .amdhsa_system_vgpr_workitem_id 1
+  .amdhsa_next_free_vgpr 9
+  .amdhsa_next_free_sgpr 27
+  .amdhsa_reserve_vcc 0
+  .amdhsa_reserve_flat_scratch 0
+  .amdhsa_reserve_xnack_mask 1
+  .amdhsa_float_round_mode_32 1
+  .amdhsa_float_round_mode_16_64 1
+  .amdhsa_float_denorm_mode_32 1
+  .amdhsa_float_denorm_mode_16_64 0
+  .amdhsa_dx10_clamp 0
+  .amdhsa_ieee_mode 0
+  .amdhsa_fp16_overflow 1
+  .amdhsa_exception_fp_ieee_invalid_op 1
+  .amdhsa_exception_fp_denorm_src 1
+  .amdhsa_exception_fp_ieee_div_zero 1
+  .amdhsa_exception_fp_ieee_overflow 1
+  .amdhsa_exception_fp_ieee_underflow 1
+  .amdhsa_exception_fp_ieee_inexact 1
+  .amdhsa_exception_int_div_zero 1
+.end_amdhsa_kernel
+
+// ASM: .amdhsa_kernel complete
+// ASM-NEXT: .amdhsa_group_segment_fixed_size 1
+// ASM-NEXT: .amdhsa_private_segment_fixed_size 1
+// ASM-NEXT: .amdhsa_kernarg_size 8
+// ASM-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
+// ASM-NEXT: .amdhsa_user_sgpr_dispatch_ptr 1
+// ASM-NEXT: .amdhsa_user_sgpr_queue_ptr 1
+// ASM-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 1
+// ASM-NEXT: .amdhsa_user_sgpr_dispatch_id 1
+// ASM-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1
+// ASM-NEXT: .amdhsa_user_sgpr_private_segment_size 1
+// ASM-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
+// ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_x 0
+// ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1
+// ASM-NEXT: .amdhsa_system_sgpr_workgroup_id_z 1
+// ASM-NEXT: .amdhsa_system_sgpr_workgroup_info 1
+// ASM-NEXT: .amdhsa_system_vgpr_workitem_id 1
+// ASM-NEXT: .amdhsa_next_free_vgpr 9
+// ASM-NEXT: .amdhsa_next_free_sgpr 27
+// ASM-NEXT: .amdhsa_reserve_vcc 0
+// ASM-NEXT: .amdhsa_reserve_flat_scratch 0
+// ASM-NEXT: .amdhsa_reserve_xnack_mask 1
+// ASM-NEXT: .amdhsa_float_round_mode_32 1
+// ASM-NEXT: .amdhsa_float_round_mode_16_64 1
+// ASM-NEXT: .amdhsa_float_denorm_mode_32 1
+// ASM-NEXT: .amdhsa_float_denorm_mode_16_64 0
+// ASM-NEXT: .amdhsa_dx10_clamp 0
+// ASM-NEXT: .amdhsa_ieee_mode 0
+// ASM-NEXT: .amdhsa_fp16_overflow 1
+// ASM-NEXT: .amdhsa_exception_fp_ieee_invalid_op 1
+// ASM-NEXT: .amdhsa_exception_fp_denorm_src 1
+// ASM-NEXT: .amdhsa_exception_fp_ieee_div_zero 1
+// ASM-NEXT: .amdhsa_exception_fp_ieee_overflow 1
+// ASM-NEXT: .amdhsa_exception_fp_ieee_underflow 1
+// ASM-NEXT: .amdhsa_exception_fp_ieee_inexact 1
+// ASM-NEXT: .amdhsa_exception_int_div_zero 1
+// ASM-NEXT: .end_amdhsa_kernel
+
+// Test that we are including special SGPR usage in the granulated count.
+.p2align 6
+.amdhsa_kernel special_sgpr
+  // Same next_free_sgpr as "complete", but...
+  .amdhsa_next_free_sgpr 27
+  // ...on GFX9 this should require an additional 6 SGPRs, pushing us from
+  // 3 granules to 4
+  .amdhsa_reserve_flat_scratch 1
+
+  .amdhsa_reserve_vcc 0
+  .amdhsa_reserve_xnack_mask 1
+
+  .amdhsa_float_denorm_mode_16_64 0
+  .amdhsa_dx10_clamp 0
+  .amdhsa_ieee_mode 0
+  .amdhsa_next_free_vgpr 0
+.end_amdhsa_kernel
+
+// ASM: .amdhsa_kernel special_sgpr
+// ASM: .amdhsa_next_free_vgpr 0
+// ASM-NEXT: .amdhsa_next_free_sgpr 27
+// ASM-NEXT: .amdhsa_reserve_vcc 0
+// ASM-NEXT: .amdhsa_reserve_xnack_mask 1
+// ASM: .amdhsa_float_denorm_mode_16_64 0
+// ASM-NEXT: .amdhsa_dx10_clamp 0
+// ASM-NEXT: .amdhsa_ieee_mode 0
+// ASM: .end_amdhsa_kernel
+
+// Test that explicitly disabling user_sgpr's does not affect the user_sgpr
+// count, i.e. this should produce the same descriptor as minimal.
+.p2align 6
+.amdhsa_kernel disabled_user_sgpr
+  .amdhsa_user_sgpr_private_segment_buffer 0
+  .amdhsa_next_free_vgpr 0
+  .amdhsa_next_free_sgpr 0
+.end_amdhsa_kernel
+
+// ASM: .amdhsa_kernel disabled_user_sgpr
+// ASM: .amdhsa_next_free_vgpr 0
+// ASM-NEXT: .amdhsa_next_free_sgpr 0
+// ASM: .end_amdhsa_kernel
+
+.section .foo
+
+.byte .amdgcn.gfx_generation_number
+// ASM: .byte 9
+
+.byte .amdgcn.gfx_generation_minor
+// ASM: .byte 0
+
+.byte .amdgcn.gfx_generation_stepping
+// ASM: .byte 4
+
+.byte .amdgcn.next_free_vgpr
+// ASM: .byte 0
+.byte .amdgcn.next_free_sgpr
+// ASM: .byte 0
+
+v_mov_b32_e32 v7, s10
+
+.byte .amdgcn.next_free_vgpr
+// ASM: .byte 8
+.byte .amdgcn.next_free_sgpr
+// ASM: .byte 11
+
+.set .amdgcn.next_free_vgpr, 0
+.set .amdgcn.next_free_sgpr, 0
+
+.byte .amdgcn.next_free_vgpr
+// ASM: .byte 0
+.byte .amdgcn.next_free_sgpr
+// ASM: .byte 0
+
+v_mov_b32_e32 v16, s3
+
+.byte .amdgcn.next_free_vgpr
+// ASM: .byte 17
+.byte .amdgcn.next_free_sgpr
+// ASM: .byte 4
+
+// Metadata
+
+.amdgpu_metadata
+  amdhsa.version:
+    - 3
+    - 0
+  amdhsa.kernels:
+    - .name:       amd_kernel_code_t_test_all
+      .symbol: amd_kernel_code_t_test_all@kd
+      .kernarg_segment_size: 8
+      .group_segment_fixed_size: 16
+      .private_segment_fixed_size: 32
+      .kernarg_segment_align: 64
+      .wavefront_size: 128
+      .sgpr_count: 14
+      .vgpr_count: 40
+      .max_flat_workgroup_size: 256
+    - .name:       amd_kernel_code_t_minimal
+      .symbol: amd_kernel_code_t_minimal@kd
+      .kernarg_segment_size: 8
+      .group_segment_fixed_size: 16
+      .private_segment_fixed_size: 32
+      .kernarg_segment_align: 64
+      .wavefront_size: 128
+      .sgpr_count: 14
+      .vgpr_count: 40
+      .max_flat_workgroup_size: 256
+.end_amdgpu_metadata
+
+// ASM:       .amdgpu_metadata
+// ASM:      amdhsa.kernels:  
+// ASM:        - .group_segment_fixed_size: 16
+// ASM:          .kernarg_segment_align: 64
+// ASM:          .kernarg_segment_size: 8
+// ASM:          .max_flat_workgroup_size: 256
+// ASM:          .name:           amd_kernel_code_t_test_all
+// ASM:          .private_segment_fixed_size: 32
+// ASM:          .sgpr_count:     14
+// ASM:          .symbol:         'amd_kernel_code_t_test_all@kd'
+// ASM:          .vgpr_count:     40
+// ASM:          .wavefront_size: 128
+// ASM:        - .group_segment_fixed_size: 16
+// ASM:          .kernarg_segment_align: 64
+// ASM:          .kernarg_segment_size: 8
+// ASM:          .max_flat_workgroup_size: 256
+// ASM:          .name:           amd_kernel_code_t_minimal
+// ASM:          .private_segment_fixed_size: 32
+// ASM:          .sgpr_count:     14
+// ASM:          .symbol:         'amd_kernel_code_t_minimal@kd'
+// ASM:          .vgpr_count:     40
+// ASM:          .wavefront_size: 128
+// ASM:      amdhsa.version:  
+// ASM-NEXT:   - 3
+// ASM-NEXT:   - 0
+// ASM:       .end_amdgpu_metadata

llvm/test/MC/AMDGPU/hsa_isa_version_attrs.s

 // RUN: llvm-mc -arch=amdgcn -mcpu=gfx801 -mattr=-fast-fmaf -show-encoding %s | FileCheck --check-prefix=GFX8 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -mattr=-mad-mix-insts -show-encoding %s | FileCheck --check-prefix=GFX9 %s
-// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32 -show-encoding %s | FileCheck --check-prefix=GFX10 %s
+// RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -mattr=-mad-mix-insts,-xnack -show-encoding %s | FileCheck --check-prefix=GFX9 %s
 
 .hsa_code_object_isa
 // GFX8:  .hsa_code_object_isa 8,0,1,"AMD","AMDGPU"
 // GFX9:  .hsa_code_object_isa 9,0,0,"AMD","AMDGPU"
-// GFX10: .hsa_code_object_isa 10,1,0,"AMD","AMDGPU"

llvm/test/MC/AMDGPU/isa-version-hsa.s

 // RUN: not llvm-mc -triple amdgcn-amd-unknown -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=OSABI-UNK-ERR %s
 // RUN: not llvm-mc -triple amdgcn-amd-unknown -mcpu=iceland %s 2>&1 | FileCheck --check-prefix=OSABI-UNK-ERR %s
 // RUN: llvm-mc -triple amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=gfx802 %s | FileCheck --check-prefix=OSABI-HSA %s
 // RUN: llvm-mc -triple amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=iceland %s | FileCheck --check-prefix=OSABI-HSA %s
 // RUN: not llvm-mc -triple amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=gfx803 %s 2>&1 | FileCheck --check-prefix=OSABI-HSA-ERR %s
 // RUN: not llvm-mc -triple amdgcn-amd-amdpal -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=OSABI-PAL-ERR %s
 // RUN: not llvm-mc -triple amdgcn-amd-amdpal -mcpu=iceland %s 2>&1 | FileCheck --check-prefix=OSABI-PAL-ERR %s
 
 // OSABI-HSA: .amd_amdgpu_isa "amdgcn-amd-amdhsa--gfx802"
-// OSABI-UNK-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line
-// OSABI-HSA-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line
-// OSABI-PAL-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line
+// OSABI-UNK-ERR: error: target id must match options
+// OSABI-HSA-ERR: error: target id must match options
+// OSABI-PAL-ERR: error: target id must match options
 .amd_amdgpu_isa "amdgcn-amd-amdhsa--gfx802"

llvm/test/MC/AMDGPU/isa-version-pal.s

 // RUN: not llvm-mc -triple amdgcn-amd-unknown -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=OSABI-UNK-ERR %s
 // RUN: not llvm-mc -triple amdgcn-amd-unknown -mcpu=iceland %s 2>&1 | FileCheck --check-prefix=OSABI-UNK-ERR %s
 // RUN: not llvm-mc -triple amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=OSABI-HSA-ERR %s
 // RUN: not llvm-mc -triple amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=iceland %s 2>&1 | FileCheck --check-prefix=OSABI-HSA-ERR %s
 // RUN: llvm-mc -triple amdgcn-amd-amdpal -mcpu=gfx802 %s | FileCheck --check-prefix=OSABI-PAL %s
 // RUN: llvm-mc -triple amdgcn-amd-amdpal -mcpu=iceland %s | FileCheck --check-prefix=OSABI-PAL %s
 // RUN: not llvm-mc -triple amdgcn-amd-unknown -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=OSABI-UNK-ERR %s
 
 // OSABI-PAL: .amd_amdgpu_isa "amdgcn-amd-amdpal--gfx802"
-// OSABI-UNK-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line
-// OSABI-HSA-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line
-// OSABI-PAL-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line
+// OSABI-UNK-ERR: error: target id must match options
+// OSABI-HSA-ERR: error: target id must match options
+// OSABI-PAL-ERR: error: target id must match options
 .amd_amdgpu_isa "amdgcn-amd-amdpal--gfx802"

llvm/test/MC/AMDGPU/isa-version-unk.s

 // RUN: llvm-mc -triple amdgcn-amd-unknown -mcpu=gfx802 %s | FileCheck --check-prefix=OSABI-UNK %s
 // RUN: llvm-mc -triple amdgcn-amd-unknown -mcpu=iceland %s | FileCheck --check-prefix=OSABI-UNK %s
 // RUN: not llvm-mc -triple amdgcn-amd-unknown -mcpu=gfx803 %s 2>&1 | FileCheck --check-prefix=OSABI-UNK-ERR %s
 // RUN: not llvm-mc -triple amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=OSABI-HSA-ERR %s
 // RUN: not llvm-mc -triple amdgcn-amd-amdhsa --amdhsa-code-object-version=2 -mcpu=iceland %s 2>&1 | FileCheck --check-prefix=OSABI-HSA-ERR %s
 // RUN: not llvm-mc -triple amdgcn-amd-amdpal -mcpu=gfx802 %s 2>&1 | FileCheck --check-prefix=OSABI-PAL-ERR %s
 // RUN: not llvm-mc -triple amdgcn-amd-amdpal -mcpu=iceland %s 2>&1 | FileCheck --check-prefix=OSABI-PAL-ERR %s
 
 // OSABI-UNK: .amd_amdgpu_isa "amdgcn-amd-unknown--gfx802"
-// OSABI-UNK-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line
-// OSABI-HSA-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line
-// OSABI-PAL-ERR: error: .amd_amdgpu_isa directive does not match triple and/or mcpu arguments specified through the command line
+// OSABI-UNK-ERR: error: target id must match options
+// OSABI-HSA-ERR: error: target id must match options
+// OSABI-PAL-ERR: error: target id must match options
 .amd_amdgpu_isa "amdgcn-amd-unknown--gfx802"

llvm/test/MC/AMDGPU/round-trip.s

-# RUN: llvm-mc -preserve-comments -triple amdgcn-amd-amdhsa %s >%t-1.s
-# RUN: llvm-mc -preserve-comments -triple amdgcn-amd-amdhsa %t-1.s >%t-2.s
+# RUN: llvm-mc -preserve-comments -triple amdgcn-amd- %s >%t-1.s
+# RUN: llvm-mc -preserve-comments -triple amdgcn-amd- %t-1.s >%t-2.s
 # RUN: diff %t-1.s %t-2.s
 
 # Test that AMDGPU assembly round-trips when run through MC; the first
 # transition from hand-written to "canonical" output may introduce some small
 # differences, so we don't include the initial input in the comparison.
 
 .text
 
 # The AMDGPU asm parser didn't consume the end of statement
 # consistently, which led to extra empty lines in the output.
 s_nop 0

llvm/test/Object/AMDGPU/elf-header-flags-sramecc.yaml

 # RUN: yaml2obj --docnum=1 %s -o %t.o.1
 # RUN: llvm-readobj -S --file-headers %t.o.1 | FileCheck --check-prefixes=ELF-SRAM-ECC-NONE %s
 # RUN: obj2yaml %t.o.1 | FileCheck --check-prefixes=YAML-SRAM-ECC-NONE %s
 # RUN: yaml2obj --docnum=2 %s -o %t.o.2
 # RUN: llvm-readobj -S --file-headers %t.o.2 | FileCheck --check-prefixes=ELF-SRAM-ECC-GFX900 %s
 # RUN: obj2yaml %t.o.2 | FileCheck --check-prefixes=YAML-SRAM-ECC-GFX900 %s
 # RUN: yaml2obj --docnum=3 %s -o %t.o.3
 # RUN: llvm-readobj -S --file-headers %t.o.3 | FileCheck --check-prefixes=ELF-SRAM-ECC-XNACK-GFX900 %s
 # RUN: obj2yaml %t.o.3 | FileCheck --check-prefixes=YAML-SRAM-ECC-XNACK-GFX900 %s
 
 # ELF-SRAM-ECC-NONE:      Flags [
-# ELF-SRAM-ECC-NONE-NEXT:   EF_AMDGPU_SRAM_ECC (0x200)
+# ELF-SRAM-ECC-NONE-NEXT:   EF_AMDGPU_FEATURE_SRAMECC_V3 (0x200)
 # ELF-SRAM-ECC-NONE-NEXT: ]
 
 # ELF-SRAM-ECC-GFX900:      Flags [
+# ELF-SRAM-ECC-GFX900-NEXT:   EF_AMDGPU_FEATURE_SRAMECC_V3 (0x200)
 # ELF-SRAM-ECC-GFX900-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
-# ELF-SRAM-ECC-GFX900-NEXT:   EF_AMDGPU_SRAM_ECC           (0x200)
 # ELF-SRAM-ECC-GFX900-NEXT: ]
 
 # ELF-SRAM-ECC-XNACK-GFX900:      Flags [
+# ELF-SRAM-ECC-XNACK-GFX900-NEXT:   EF_AMDGPU_FEATURE_SRAMECC_V3 (0x200)
+# ELF-SRAM-ECC-XNACK-GFX900-NEXT:   EF_AMDGPU_FEATURE_XNACK_V3   (0x100)
 # ELF-SRAM-ECC-XNACK-GFX900-NEXT:   EF_AMDGPU_MACH_AMDGCN_GFX900 (0x2C)
-# ELF-SRAM-ECC-XNACK-GFX900-NEXT:   EF_AMDGPU_SRAM_ECC           (0x200)
-# ELF-SRAM-ECC-XNACK-GFX900-NEXT:   EF_AMDGPU_XNACK              (0x100)
 # ELF-SRAM-ECC-XNACK-GFX900-NEXT: ]
 
-# YAML-SRAM-ECC-NONE:         Flags: [ EF_AMDGPU_MACH_NONE, EF_AMDGPU_SRAM_ECC ]
-# YAML-SRAM-ECC-GFX900:       Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX900, EF_AMDGPU_SRAM_ECC ]
-# YAML-SRAM-ECC-XNACK-GFX900: Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX900, EF_AMDGPU_XNACK, EF_AMDGPU_SRAM_ECC ]
+# YAML-SRAM-ECC-NONE:         Flags: [ EF_AMDGPU_MACH_NONE, EF_AMDGPU_FEATURE_SRAMECC_V3 ]
+# YAML-SRAM-ECC-GFX900:       Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX900, EF_AMDGPU_FEATURE_SRAMECC_V3 ]
+# YAML-SRAM-ECC-XNACK-GFX900: Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX900, EF_AMDGPU_FEATURE_XNACK_V3, EF_AMDGPU_FEATURE_SRAMECC_V3 ]
 
 # Doc1
 --- !ELF
 FileHeader:
   Class:   ELFCLASS64
   Data:    ELFDATA2LSB
   OSABI:   ELFOSABI_NONE
   Type:    ET_REL
   Machine: EM_AMDGPU
-  Flags:   [ EF_AMDGPU_SRAM_ECC ]
+  Flags:   [ EF_AMDGPU_FEATURE_SRAMECC_V3 ]
 ...
 
 # Doc2
 --- !ELF
 FileHeader:
   Class:   ELFCLASS64
   Data:    ELFDATA2LSB
   OSABI:   ELFOSABI_NONE
   Type:    ET_REL
   Machine: EM_AMDGPU
-  Flags:   [ EF_AMDGPU_MACH_AMDGCN_GFX900, EF_AMDGPU_SRAM_ECC ]
+  Flags:   [ EF_AMDGPU_MACH_AMDGCN_GFX900, EF_AMDGPU_FEATURE_SRAMECC_V3 ]
 ...
 
 # Doc3
 --- !ELF
 FileHeader:
   Class:   ELFCLASS64
   Data:    ELFDATA2LSB
   OSABI:   ELFOSABI_NONE
   Type:    ET_REL
   Machine: EM_AMDGPU
-  Flags:   [ EF_AMDGPU_MACH_AMDGCN_GFX900, EF_AMDGPU_XNACK, EF_AMDGPU_SRAM_ECC ]
+  Flags:   [ EF_AMDGPU_MACH_AMDGCN_GFX900, EF_AMDGPU_FEATURE_XNACK_V3, EF_AMDGPU_FEATURE_SRAMECC_V3 ]
 ...

llvm/test/Object/AMDGPU/elf-header-flags-xnack.yaml

 # RUN: yaml2obj --docnum=1 %s -o %t.o.1
 # RUN: llvm-readobj -S --file-headers %t.o.1 | FileCheck --check-prefixes=ELF-ALL,ELF-XNACK-NONE %s
 # RUN: obj2yaml %t.o.1 | FileCheck --check-prefixes=YAML-XNACK-NONE %s
 # RUN: yaml2obj --docnum=2 %s -o %t.o.2
 # RUN: llvm-readobj -S --file-headers %t.o.2 | FileCheck --check-prefixes=ELF-ALL,ELF-XNACK-GFX801 %s
 # RUN: obj2yaml %t.o.2 | FileCheck --check-prefixes=YAML-XNACK-GFX801 %s
 
 # ELF-ALL:          Flags [
-# ELF-XNACK-NONE:     EF_AMDGPU_XNACK              (0x100)
+# ELF-XNACK-NONE:     EF_AMDGPU_FEATURE_XNACK_V3   (0x100)
+# ELF-XNACK-GFX801:   EF_AMDGPU_FEATURE_XNACK_V3   (0x100)
 # ELF-XNACK-GFX801:   EF_AMDGPU_MACH_AMDGCN_GFX801 (0x28)
-# ELF-XNACK-GFX801:   EF_AMDGPU_XNACK              (0x100)
 # ELF-ALL:          ]
 
-# YAML-XNACK-NONE:   Flags: [ EF_AMDGPU_MACH_NONE, EF_AMDGPU_XNACK ]
-# YAML-XNACK-GFX801: Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX801, EF_AMDGPU_XNACK ]
+# YAML-XNACK-NONE:   Flags: [ EF_AMDGPU_MACH_NONE, EF_AMDGPU_FEATURE_XNACK_V3 ]
+# YAML-XNACK-GFX801: Flags: [ EF_AMDGPU_MACH_AMDGCN_GFX801, EF_AMDGPU_FEATURE_XNACK_V3 ]
 
 # Doc1
 --- !ELF
 FileHeader:
   Class:   ELFCLASS64
   Data:    ELFDATA2LSB
   OSABI:   ELFOSABI_NONE
   Type:    ET_REL
   Machine: EM_AMDGPU
-  Flags:   [ EF_AMDGPU_XNACK ]
+  Flags:   [ EF_AMDGPU_FEATURE_XNACK_V3 ]
 ...
 
 # Doc2
 --- !ELF
 FileHeader:
   Class:   ELFCLASS64
   Data:    ELFDATA2LSB
   OSABI:   ELFOSABI_NONE
   Type:    ET_REL
   Machine: EM_AMDGPU
-  Flags:   [ EF_AMDGPU_MACH_AMDGCN_GFX801, EF_AMDGPU_XNACK ]
+  Flags:   [ EF_AMDGPU_MACH_AMDGCN_GFX801, EF_AMDGPU_FEATURE_XNACK_V3 ]
 ...

llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-failure.s

 
 ;; Test failure by setting one of the reserved bytes to non-zero value.
 
 .type my_kernel.kd, @object
 .size my_kernel.kd, 64
 my_kernel.kd:
   .long 0x00000000           ;; group_segment_fixed_size
   .long 0x00000000           ;; private_segment_fixed_size
-  .quad 0x00FF000000000000   ;; reserved bytes.
+  .long 0x00000000           ;; kernarg_segment_size.
+  .long 0x00000000           ;; reserved bytes.
   .quad 0x0000000000000000   ;; kernel_code_entry_byte_offset, any value works.
 
   ;; 20 reserved bytes.
-  .quad 0x0000000000000000
+  .quad 0x00FF000000000000   ;; reserved bytes.
   .quad 0x0000000000000000
   .long 0x00000000
 
   .long 0x00000000           ;; compute_PGM_RSRC3
   .long 0x00000000           ;; compute_PGM_RSRC1
   .long 0x00000000           ;; compute_PGM_RSRC2
   .short 0x0000              ;; additional fields.
 
   ;; 6 reserved bytes.
   .long 0x0000000
   .short 0x0000

llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-sgpr.s

 ;; Test disassembly for GRANULATED_WAVEFRONT_SGPR_COUNT in the kernel descriptor.
 
 ; RUN: split-file %s %t.dir
 
-; RUN: llvm-mc %t.dir/1.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t1
+; RUN: llvm-mc %t.dir/1.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t1
 ; RUN: llvm-objdump --disassemble-symbols=my_kernel_1.kd %t1 | tail -n +8 \
-; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t1-re-assemble
+; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t1-re-assemble
 ; RUN: diff %t1 %t1-re-assemble
 
-; RUN: llvm-mc %t.dir/2.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t2
+; RUN: llvm-mc %t.dir/2.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t2
 ; RUN: llvm-objdump --disassemble-symbols=my_kernel_2.kd %t2 | tail -n +8 \
-; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t2-re-assemble
+; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t2-re-assemble
 ; RUN: diff %t2 %t2-re-assemble
 
-; RUN: llvm-mc %t.dir/3.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t3
+; RUN: llvm-mc %t.dir/3.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t3
 ; RUN: llvm-objdump --disassemble-symbols=my_kernel_3.kd %t3 | tail -n +8 \
-; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t3-re-assemble
+; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t3-re-assemble
 ; RUN: diff %t3 %t3-re-assemble
 
 
 ;--- 1.s
 ;; Only set next_free_sgpr.
 .amdhsa_kernel my_kernel_1
   .amdhsa_next_free_vgpr 0
   .amdhsa_next_free_sgpr 42
   .amdhsa_reserve_flat_scratch 0
   .amdhsa_reserve_xnack_mask 0
   .amdhsa_reserve_vcc 0
 .end_amdhsa_kernel
 
 ;--- 2.s
 ;; Only set other directives.
 .amdhsa_kernel my_kernel_2
   .amdhsa_next_free_vgpr 0
   .amdhsa_next_free_sgpr 0
   .amdhsa_reserve_flat_scratch 1
-  .amdhsa_reserve_xnack_mask 1
+  .amdhsa_reserve_xnack_mask 0
   .amdhsa_reserve_vcc 1
 .end_amdhsa_kernel
 
 ;--- 3.s
 ;; Set all affecting directives.
 .amdhsa_kernel my_kernel_3
   .amdhsa_next_free_vgpr 0
   .amdhsa_next_free_sgpr 35
   .amdhsa_reserve_flat_scratch 1
-  .amdhsa_reserve_xnack_mask 1
+  .amdhsa_reserve_xnack_mask 0
   .amdhsa_reserve_vcc 1
 .end_amdhsa_kernel

llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-vgpr.s

 ;; Test disassembly for GRANULATED_WORKITEM_VGPR_COUNT in the kernel descriptor.
 
 ; RUN: split-file %s %t.dir
 
-; RUN: llvm-mc %t.dir/1.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t1
+; RUN: llvm-mc %t.dir/1.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t1
 ; RUN: llvm-objdump --disassemble-symbols=my_kernel_1.kd %t1 | tail -n +8 \
-; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t1-re-assemble
+; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t1-re-assemble
 ; RUN: diff %t1 %t1-re-assemble
 
-; RUN: llvm-mc %t.dir/2.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t2
+; RUN: llvm-mc %t.dir/2.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t2
 ; RUN: llvm-objdump --disassemble-symbols=my_kernel_2.kd %t2 | tail -n +8 \
-; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t2-re-assemble
+; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t2-re-assemble
 ; RUN: diff %t2 %t2-re-assemble
 
-; RUN: llvm-mc %t.dir/3.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t3
+; RUN: llvm-mc %t.dir/3.s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t3
 ; RUN: llvm-objdump --disassemble-symbols=my_kernel_3.kd %t3 | tail -n +8 \
-; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t3-re-assemble
+; RUN: | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t3-re-assemble
 ; RUN: diff %t3 %t3-re-assemble
 
 ;--- 1.s
 .amdhsa_kernel my_kernel_1
   .amdhsa_next_free_vgpr 23
   .amdhsa_next_free_sgpr 0
 .end_amdhsa_kernel
 

llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s

 ;; Entirely zeroed kernel descriptor (for GFX10).
 
-; RUN: llvm-mc %s --triple=amdgcn-amd-amdhsa -mcpu=gfx1010 -filetype=obj -o %t
+; RUN: llvm-mc %s --triple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=-xnack -filetype=obj -o %t
 ; RUN: llvm-objdump -s -j .text %t | FileCheck --check-prefix=OBJDUMP %s
 
 ;; TODO:
 ;; This file and kd-zeroed-raw.s should produce the same output for the kernel
 ;; descriptor - a block of 64 zeroed bytes. But looks like the assembler sets
 ;; the FWD_PROGRESS bit in COMPUTE_PGM_RSRC1 to 1 even when the directive
 ;; mentions 0 (see line 36).
 

llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx9.s

 ;; Entirely zeroed kernel descriptor (for GFX9).
 
-; RUN: llvm-mc %s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t1
+; RUN: llvm-mc %s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t1
 ; RUN: llvm-objdump --disassemble-symbols=my_kernel.kd %t1 \
-; RUN: | tail -n +8 | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t2
+; RUN: | tail -n +8 | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t2
 ; RUN: diff %t1 %t2
 
 ; RUN: llvm-objdump -s -j .text %t1 | FileCheck --check-prefix=OBJDUMP %s
 
 ; OBJDUMP:      0000 00000000 00000000 00000000 00000000
 ; OBJDUMP-NEXT: 0010 00000000 00000000 00000000 00000000
 ; OBJDUMP-NEXT: 0020 00000000 00000000 00000000 00000000
 ; OBJDUMP-NEXT: 0030 00000000 00000000 00000000 00000000

llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-raw.s

-; RUN: llvm-mc %s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t1
+; RUN: llvm-mc %s --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t1
 ; RUN: llvm-objdump --disassemble-symbols=my_kernel.kd %t1 \
-; RUN: | tail -n +8 | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -filetype=obj -o %t2
+; RUN: | tail -n +8 | llvm-mc --triple=amdgcn-amd-amdhsa -mcpu=gfx908 -mattr=-xnack -filetype=obj -o %t2
 ; RUN: llvm-objdump -s -j .text %t2 | FileCheck --check-prefix=OBJDUMP %s
 
 ;; Not running lit-test over gfx10 (see kd-zeroed-gfx10.s for details).
 ;; kd-zeroed-raw.s and kd-zeroed-*.s should produce the same output for the
 ;; kernel descriptor - a block of 64 zeroed bytes.
 
 ;; The disassembly will produce the contents of kd-zeroed-*.s which on being
 ;; assembled contains additional relocation info. A diff over the entire object

llvm/test/tools/llvm-readobj/ELF/note-amd.s

 // REQUIRES: x86-registered-target
 // RUN: llvm-mc -filetype=obj -triple x86_64-pc-linux-gnu %s -o %t.o
 
 // RUN: llvm-readobj --notes %t.o | FileCheck %s --check-prefix=LLVM
 // RUN: llvm-readelf --notes %t.o | FileCheck %s --check-prefix=GNU
 
 // GNU:      Displaying notes found in: .note.no.desc
 // GNU-NEXT:   Owner                Data size        Description
-// GNU-NEXT:   AMD                  0x00000000       NT_AMD_AMDGPU_HSA_METADATA (HSA Metadata)
-// GNU-NEXT:     HSA Metadata:
-// GNU-NEXT: {{^ +$}}
-// GNU-NEXT:   AMD                  0x00000000       NT_AMD_AMDGPU_ISA (ISA Version)
-// GNU-NEXT:     ISA Version:
-// GNU-NEXT: {{^ +$}}
+// GNU-NEXT:   AMD                  0x00000000       NT_AMD_HSA_METADATA (AMD HSA Metadata)
+// GNU-NEXT:     AMD HSA Metadata:
+// GNU-NEXT:         Invalid AMD HSA Metadata
+// GNU-NEXT:   AMD                  0x00000000       NT_AMD_HSA_ISA_NAME (AMD HSA ISA Name)
+// GNU-NEXT:     AMD HSA ISA Name:
+// GNU-NEXT:         Invalid AMD HSA ISA Name
 // GNU-NEXT: Displaying notes found in: .note.desc
 // GNU-NEXT:   Owner                Data size        Description
-// GNU-NEXT:   AMD                  0x0000000a       NT_AMD_AMDGPU_HSA_METADATA (HSA Metadata)
-// GNU-NEXT:     HSA Metadata:
-// GNU-NEXT:     meta_blah
-// GNU-NEXT:   AMD                  0x00000009       NT_AMD_AMDGPU_ISA (ISA Version)
-// GNU-NEXT:     ISA Version:
-// GNU-NEXT:     isa_blah
+// GNU-NEXT:   AMD                  0x0000000a       NT_AMD_HSA_METADATA (AMD HSA Metadata)
+// GNU-NEXT:     AMD HSA Metadata:
+// GNU-NEXT:         meta_blah
+// GNU-NEXT:   AMD                  0x00000009       NT_AMD_HSA_ISA_NAME (AMD HSA ISA Name)
+// GNU-NEXT:     AMD HSA ISA Name:
+// GNU-NEXT:         isa_blah
 // GNU-NEXT: Displaying notes found in: .note.other
 // GNU-NEXT:   Owner                Data size        Description
-// GNU-NEXT:   AMD                  0x00000000       NT_AMD_AMDGPU_PAL_METADATA (PAL Metadata)
+// GNU-NEXT:   AMD                  0x00000000       NT_AMD_PAL_METADATA (AMD PAL Metadata)
+// GNI-NEXT:     AMD PAL Metadata:
 
 // LLVM:      Notes [
 // LLVM-NEXT:   NoteSection {
 // LLVM-NEXT:     Name: .note.no.desc
 // LLVM-NEXT:     Offset:
 // LLVM-NEXT:     Size:
 // LLVM-NEXT:     Note {
 // LLVM-NEXT:       Owner: AMD
 // LLVM-NEXT:       Data size: 0x0
-// LLVM-NEXT:       Type: NT_AMD_AMDGPU_HSA_METADATA (HSA Metadata)
-// LLVM-NEXT:       HSA Metadata:
+// LLVM-NEXT:       Type: NT_AMD_HSA_METADATA (AMD HSA Metadata)
+// LLVM-NEXT:       AMD HSA Metadata:
 // LLVM-NEXT:     }
 // LLVM-NEXT:     Note {
 // LLVM-NEXT:       Owner: AMD
 // LLVM-NEXT:       Data size: 0x0
-// LLVM-NEXT:       Type: NT_AMD_AMDGPU_ISA (ISA Version)
-// LLVM-NEXT:       ISA Version:
+// LLVM-NEXT:       Type: NT_AMD_HSA_ISA_NAME (AMD HSA ISA Name)
+// LLVM-NEXT:       AMD HSA ISA Name:
 // LLVM-NEXT:     }
 // LLVM-NEXT:   }
 // LLVM-NEXT:   NoteSection {
 // LLVM-NEXT:     Name: .note.desc
 // LLVM-NEXT:     Offset:
 // LLVM-NEXT:     Size:
 // LLVM-NEXT:     Note {
 // LLVM-NEXT:       Owner: AMD
 // LLVM-NEXT:       Data size: 0xA
-// LLVM-NEXT:       Type: NT_AMD_AMDGPU_HSA_METADATA (HSA Metadata)
-// LLVM-NEXT:       HSA Metadata: meta_blah
+// LLVM-NEXT:       Type: NT_AMD_HSA_METADATA (AMD HSA Metadata)
+// LLVM-NEXT:       AMD HSA Metadata: meta_blah
 // LLVM-NEXT:     }
 // LLVM-NEXT:     Note {
 // LLVM-NEXT:       Owner: AMD
 // LLVM-NEXT:       Data size: 0x9
-// LLVM-NEXT:       Type: NT_AMD_AMDGPU_ISA (ISA Version)
-// LLVM-NEXT:       ISA Version: isa_blah
+// LLVM-NEXT:       Type: NT_AMD_HSA_ISA_NAME (AMD HSA ISA Name)
+// LLVM-NEXT:       AMD HSA ISA Name: isa_blah
 // LLVM-NEXT:     }
 // LLVM-NEXT:   }
 // LLVM-NEXT:   NoteSection {
 // LLVM-NEXT:     Name: .note.other
 // LLVM-NEXT:     Offset:
 // LLVM-NEXT:     Size:
 // LLVM-NEXT:     Note {
 // LLVM-NEXT:       Owner: AMD
 // LLVM-NEXT:       Data size: 0x0
-// LLVM-NEXT:       Type: NT_AMD_AMDGPU_PAL_METADATA (PAL Metadata)
+// LLVM-NEXT:       Type: NT_AMD_PAL_METADATA (AMD PAL Metadata)
+// LLVM-NEXT:       AMD PAL Metadata:
 // LLVM-NEXT:     }
 // LLVM-NEXT:   }
 // LLVM-NEXT: ]
 
 .section ".note.no.desc", "a"
   .align 4
   .long 4 /* namesz */
   .long 0 /* descsz */
-  .long 10 /* type = NT_AMD_AMDGPU_HSA_METADATA */
+  .long 10 /* type = NT_AMD_HSA_METADATA */
   .asciz "AMD"
   .long 4 /* namesz */
   .long 0 /* descsz */
-  .long 11 /* type = NT_AMD_AMDGPU_ISA */
+  .long 11 /* type = NT_AMD_HSA_ISA_NAME */
   .asciz "AMD"
 .section ".note.desc", "a"
   .align 4
   .long 4 /* namesz */
   .long end.meta - begin.meta /* descsz */
-  .long 10 /* type = NT_AMD_AMDGPU_HSA_METADATA */
+  .long 10 /* type = NT_AMD_HSA_METADATA */
   .asciz "AMD"
 begin.meta:
   .asciz "meta_blah"
 end.meta:
   .align 4
   .long 4 /* namesz */
   .long end.isa - begin.isa /* descsz */
-  .long 11 /* type = NT_AMD_AMDGPU_ISA */
+  .long 11 /* type = NT_AMD_HSA_ISA_NAME */
   .asciz "AMD"
 begin.isa:
   .asciz "isa_blah"
 end.isa:
   .align 4
 .section ".note.other", "a"
   .align 4
   .long 4 /* namesz */
   .long 0 /* descsz */
-  .long 12 /* type = NT_AMD_AMDGPU_PAL_METADATA */
+  .long 12 /* type = NT_AMD_PAL_METADATA */
   .asciz "AMD"

llvm/tools/llvm-readobj/ELFDumper.cpp

static const EnumEntry<unsigned> ElfHeaderMipsFlags[] = {
   ENUM_ENT(EF_MIPS_ARCH_32, "mips32"),
   ENUM_ENT(EF_MIPS_ARCH_64, "mips64"),
   ENUM_ENT(EF_MIPS_ARCH_32R2, "mips32r2"),
   ENUM_ENT(EF_MIPS_ARCH_64R2, "mips64r2"),
   ENUM_ENT(EF_MIPS_ARCH_32R6, "mips32r6"),
   ENUM_ENT(EF_MIPS_ARCH_64R6, "mips64r6")
 };
 
-static const EnumEntry<unsigned> ElfHeaderAMDGPUFlags[] = {
+static const EnumEntry<unsigned> ElfHeaderAMDGPUFlagsABIVersion3[] = {
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_NONE),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_R600),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_R630),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RS880),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RV670),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RV710),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RV730),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RV770),
static const EnumEntry<unsigned> ElfHeaderAMDGPUFlagsABIVersion3[] = {
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX90C),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1010),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1011),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1012),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1030),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1031),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1032),
   LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1033),
-  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_XNACK),
-  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_SRAM_ECC)
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_FEATURE_XNACK_V3),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_FEATURE_SRAMECC_V3)
+};
+
+static const EnumEntry<unsigned> ElfHeaderAMDGPUFlagsABIVersion4[] = {
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_NONE),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_R600),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_R630),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RS880),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RV670),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RV710),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RV730),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_RV770),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_CEDAR),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_CYPRESS),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_JUNIPER),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_REDWOOD),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_SUMO),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_BARTS),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_CAICOS),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_CAYMAN),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_R600_TURKS),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX600),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX601),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX700),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX701),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX702),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX703),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX704),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX801),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX802),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX803),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX810),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX900),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX902),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX904),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX906),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX908),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX909),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1010),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1011),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1012),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1030),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1031),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1032),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_MACH_AMDGCN_GFX1033),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_FEATURE_XNACK_ANY_V4),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_FEATURE_XNACK_OFF_V4),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_FEATURE_XNACK_ON_V4),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_FEATURE_SRAMECC_ANY_V4),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_FEATURE_SRAMECC_OFF_V4),
+  LLVM_READOBJ_ENUM_ENT(ELF, EF_AMDGPU_FEATURE_SRAMECC_ON_V4)
 };
 
 static const EnumEntry<unsigned> ElfHeaderRISCVFlags[] = {
   ENUM_ENT(EF_RISCV_RVC, "RVC"),
   ENUM_ENT(EF_RISCV_FLOAT_ABI_SINGLE, "single-float ABI"),
   ENUM_ENT(EF_RISCV_FLOAT_ABI_DOUBLE, "double-float ABI"),
   ENUM_ENT(EF_RISCV_FLOAT_ABI_QUAD, "quad-float ABI"),
   ENUM_ENT(EF_RISCV_RVE, "RVE")
struct AMDNote {
   std::string Value;
 };
 
 template <typename ELFT>
 static AMDNote getAMDNote(uint32_t NoteType, ArrayRef<uint8_t> Desc) {
   switch (NoteType) {
   default:
     return {"", ""};
-  case ELF::NT_AMD_AMDGPU_HSA_METADATA:
+  case ELF::NT_AMD_HSA_CODE_OBJECT_VERSION: {
+    struct CodeObjectVersion {
+      uint32_t MajorVersion;
+      uint32_t MinorVersion;
+    };
+    if (Desc.size() != sizeof(CodeObjectVersion))
+      return {"AMD HSA Code Object Version",
+              "Invalid AMD HSA Code Object Version"};
+    std::string VersionString;
+    raw_string_ostream StrOS(VersionString);
+    auto Version = reinterpret_cast<const CodeObjectVersion *>(Desc.data());
+    StrOS << "[Major: " << Version->MajorVersion
+          << ", Minor: " << Version->MinorVersion << "]";
+    return {"AMD HSA Code Object Version", VersionString};
+  }
+  case ELF::NT_AMD_HSA_HSAIL: {
+    struct HSAILProperties {
+      uint32_t HSAILMajorVersion;
+      uint32_t HSAILMinorVersion;
+      uint8_t Profile;
+      uint8_t MachineModel;
+      uint8_t DefaultFloatRound;
+    };
+    if (Desc.size() != sizeof(HSAILProperties))
+      return {"AMD HSA HSAIL Properties", "Invalid AMD HSA HSAIL Properties"};
+    auto Properties = reinterpret_cast<const HSAILProperties *>(Desc.data());
+    std::string HSAILPropetiesString;
+    raw_string_ostream StrOS(HSAILPropetiesString);
+    StrOS << "[HSAIL Major: " << Properties->HSAILMajorVersion
+          << ", HSAIL Minor: " << Properties->HSAILMinorVersion
+          << ", Profile: " << Properties->Profile
+          << ", Machine Model: " << Properties->MachineModel
+          << ", Default Float Round: " << Properties->DefaultFloatRound << "]";
+    return {"AMD HSA HSAIL Properties", HSAILPropetiesString};
+  }
+  case ELF::NT_AMD_HSA_ISA_VERSION: {
+    struct IsaVersion {
+      uint16_t VendorNameSize;
+      uint16_t ArchitectureNameSize;
+      uint32_t Major;
+      uint32_t Minor;
+      uint32_t Stepping;
+    };
+    if (Desc.size() < sizeof(IsaVersion))
+      return {"AMD HSA ISA Version", "Invalid AMD HSA ISA Version"};
+    auto Isa = reinterpret_cast<const IsaVersion *>(Desc.data());
+    if (Desc.size() < sizeof(IsaVersion) +
+                          Isa->VendorNameSize + Isa->ArchitectureNameSize ||
+        Isa->VendorNameSize == 0 || Isa->ArchitectureNameSize == 0)
+      return {"AMD HSA ISA Version", "Invalid AMD HSA ISA Version"};
+    std::string IsaString;
+    raw_string_ostream StrOS(IsaString);
+    StrOS << "[Vendor: "
+          << StringRef((const char*)Desc.data() + sizeof(IsaVersion), Isa->VendorNameSize - 1)
+          << ", Architecture: "
+          << StringRef((const char*)Desc.data() + sizeof(IsaVersion) + Isa->VendorNameSize,
+                       Isa->ArchitectureNameSize - 1)
+          << ", Major: " << Isa->Major << ", Minor: " << Isa->Minor
+          << ", Stepping: " << Isa->Stepping << "]";
+    return {"AMD HSA ISA Version", IsaString};
+  }
+  case ELF::NT_AMD_HSA_METADATA: {
+    if (Desc.size() == 0)
+      return {"AMD HSA Metadata", "Invalid AMD HSA Metadata"};
     return {
-        "HSA Metadata",
-        std::string(reinterpret_cast<const char *>(Desc.data()), Desc.size())};
-  case ELF::NT_AMD_AMDGPU_ISA:
+        "AMD HSA Metadata",
+        std::string(reinterpret_cast<const char *>(Desc.data()), Desc.size() - 1)};
+  }
+  case ELF::NT_AMD_HSA_ISA_NAME: {
+    if (Desc.size() == 0)
+      return {"AMD HSA ISA Name", "Invalid AMD HSA ISA Name"};
     return {
-        "ISA Version",
+        "AMD HSA ISA Name",
         std::string(reinterpret_cast<const char *>(Desc.data()), Desc.size())};
   }
+  case ELF::NT_AMD_PAL_METADATA: {
+    struct PALMetadata {
+      uint32_t Key;
+      uint32_t Value;
+    };
+    auto Isa = reinterpret_cast<const PALMetadata *>(Desc.data());
+    std::string MetadataString;
+    raw_string_ostream StrOS(MetadataString);
+    for (size_t I = 0, E = Desc.size() / sizeof(PALMetadata); I < E; ++E) {
+      StrOS << "[" << Isa[I].Key << ": " << Isa[I].Value << "]";
+    }
+    return {"AMD PAL Metadata", MetadataString};
+  }
+  }
 }
 
 struct AMDGPUNote {
   std::string Type;
   std::string Value;
 };
 
 template <typename ELFT>
 static AMDGPUNote getAMDGPUNote(uint32_t NoteType, ArrayRef<uint8_t> Desc) {
   switch (NoteType) {
   default:
     return {"", ""};
   case ELF::NT_AMDGPU_METADATA: {
     StringRef MsgPackString =
         StringRef(reinterpret_cast<const char *>(Desc.data()), Desc.size());
     msgpack::Document MsgPackDoc;
     if (!MsgPackDoc.readFromBlob(MsgPackString, /*Multi=*/false))
       return {"AMDGPU Metadata", "Invalid AMDGPU Metadata"};
 
     AMDGPU::HSAMD::V3::MetadataVerifier Verifier(true);
-    std::string HSAMetadataString;
+    std::string MetadataString;
     if (!Verifier.verify(MsgPackDoc.getRoot()))
-      HSAMetadataString = "Invalid AMDGPU Metadata\n";
+      MetadataString = "Invalid AMDGPU Metadata\n";
 
-    raw_string_ostream StrOS(HSAMetadataString);
+    raw_string_ostream StrOS(MetadataString);
     MsgPackDoc.toYAML(StrOS);
 
     return {"AMDGPU Metadata", StrOS.str()};
   }
   }
 }
 
 struct CoreFileMapping {
static const NoteType FreeBSDNoteTypes[] = {
     {ELF::NT_FREEBSD_PROCSTAT_RLIMIT, "NT_PROCSTAT_RLIMIT (rlimit data)"},
     {ELF::NT_FREEBSD_PROCSTAT_OSREL, "NT_PROCSTAT_OSREL (osreldate data)"},
     {ELF::NT_FREEBSD_PROCSTAT_PSSTRINGS,
      "NT_PROCSTAT_PSSTRINGS (ps_strings data)"},
     {ELF::NT_FREEBSD_PROCSTAT_AUXV, "NT_PROCSTAT_AUXV (auxv data)"},
 };
 
 static const NoteType AMDNoteTypes[] = {
-    {ELF::NT_AMD_AMDGPU_HSA_METADATA,
-     "NT_AMD_AMDGPU_HSA_METADATA (HSA Metadata)"},
-    {ELF::NT_AMD_AMDGPU_ISA, "NT_AMD_AMDGPU_ISA (ISA Version)"},
-    {ELF::NT_AMD_AMDGPU_PAL_METADATA,
-     "NT_AMD_AMDGPU_PAL_METADATA (PAL Metadata)"},
+    {ELF::NT_AMD_HSA_CODE_OBJECT_VERSION,
+     "NT_AMD_HSA_CODE_OBJECT_VERSION (AMD HSA Code Object Version)"},
+    {ELF::NT_AMD_HSA_HSAIL, "NT_AMD_HSA_HSAIL (AMD HSA HSAIL Properties)"},
+    {ELF::NT_AMD_HSA_ISA_VERSION, "NT_AMD_HSA_ISA_VERSION (AMD HSA ISA Version)"},
+    {ELF::NT_AMD_HSA_METADATA, "NT_AMD_HSA_METADATA (AMD HSA Metadata)"},
+    {ELF::NT_AMD_HSA_ISA_NAME, "NT_AMD_HSA_ISA_NAME (AMD HSA ISA Name)"},
+    {ELF::NT_AMD_PAL_METADATA, "NT_AMD_PAL_METADATA (AMD PAL Metadata)"},
 };
 
 static const NoteType AMDGPUNoteTypes[] = {
     {ELF::NT_AMDGPU_METADATA, "NT_AMDGPU_METADATA (AMDGPU Metadata)"},
 };
 
 static const NoteType CoreNoteTypes[] = {
     {ELF::NT_PRSTATUS, "NT_PRSTATUS (prstatus structure)"},
const Elf_Ehdr &E = this->Obj.getHeader();
     W.printNumber("Version", E.e_version);
     W.printHex("Entry", E.e_entry);
     W.printHex("ProgramHeaderOffset", E.e_phoff);
     W.printHex("SectionHeaderOffset", E.e_shoff);
     if (E.e_machine == EM_MIPS)
       W.printFlags("Flags", E.e_flags, makeArrayRef(ElfHeaderMipsFlags),
                    unsigned(ELF::EF_MIPS_ARCH), unsigned(ELF::EF_MIPS_ABI),
                    unsigned(ELF::EF_MIPS_MACH));
-    else if (E.e_machine == EM_AMDGPU)
-      W.printFlags("Flags", E.e_flags, makeArrayRef(ElfHeaderAMDGPUFlags),
+    else if (E.e_machine == EM_AMDGPU) {
+      switch (E.e_ident[ELF::EI_ABIVERSION]) {
+      default:
+        break;
+      case 0:
+        // ELFOSABI_AMDGPU_PAL, ELFOSABI_AMDGPU_MESA3D support *_V3 flags.
+        LLVM_FALLTHROUGH;
+      case ELF::ELFABIVERSION_AMDGPU_HSA_V3:
+        W.printFlags("Flags", E.e_flags,
+                     makeArrayRef(ElfHeaderAMDGPUFlagsABIVersion3),
                      unsigned(ELF::EF_AMDGPU_MACH));
-    else if (E.e_machine == EM_RISCV)
+        break;
+      case ELF::ELFABIVERSION_AMDGPU_HSA_V4:
+        W.printFlags("Flags", E.e_flags,
+                     makeArrayRef(ElfHeaderAMDGPUFlagsABIVersion4),
+                     unsigned(ELF::EF_AMDGPU_MACH),
+                     unsigned(ELF::EF_AMDGPU_FEATURE_XNACK_V4),
+                     unsigned(ELF::EF_AMDGPU_FEATURE_SRAMECC_V4));
+        break;
+      }
+    } else if (E.e_machine == EM_RISCV)
       W.printFlags("Flags", E.e_flags, makeArrayRef(ElfHeaderRISCVFlags));
     else
       W.printFlags("Flags", E.e_flags);
     W.printNumber("HeaderSize", E.e_ehsize);
     W.printNumber("ProgramHeaderEntrySize", E.e_phentsize);
     W.printNumber("ProgramHeaderCount", E.e_phnum);
     W.printNumber("SectionHeaderEntrySize", E.e_shentsize);
     W.printString("SectionHeaderCount",