- User Since
- Apr 4 2014, 4:14 AM (245 w, 4 d)
Thu, Dec 13
It looks good to me, but @arsenm could you also take a look?
Wed, Dec 12
Tue, Dec 11
Can we have a mir test with more than two loads? I want to see a situation where 3 loads are foldable with the same offset, but lowest address is in the middle. I.e.:
Sun, Dec 9
Fri, Dec 7
Switched to MDT use.
Added tests with cross block defines.
Thu, Dec 6
Tue, Dec 4
Sun, Dec 2
Fri, Nov 30
Thu, Nov 29
As far as I understand if PredicateCodeUsesOperands is not used nothing changes.
The error is that condition is actually has to be negated. However, if I just negate it it goes into an endless loop inside the combiner. I need to fix our BRCOND lowering instead.
Wed, Nov 28
It does not validate in some tests. I will investigate it as I do not see right away what is wrong.
Added sext handling.
Tue, Nov 27
Mon, Nov 26
LGTM (for AMDGPU tests and core).
Essentially this is a limited version of shrinking. So I have several questions:
Tue, Nov 20
Mon, Nov 19
Nov 16 2018
Added negative checks to select-undef.ll and rebased.
Converted tests to non-undef vectors, added a test with an undef vector.
This is now based on D54646 and insert_vector_elt undef, ... results just in a splat.
Added test from D48376.