- User Since
- Apr 4 2014, 4:14 AM (219 w, 5 d)
Addressed review comments.
All prerequisites are submitted, this change is ready now.
Rebased to master.
Tue, Jun 19
Added some i16/f16/vector tests.
Mon, Jun 18
Updated x86 test after rebase.
Added x86 test for shifts with not reversed operands (as before the change).
- Added comment about shift VTs
- Renamed C1 into CBO
Only commute part of the change.
- Fixed handling of non-commutative operations if arguments are swapped.
- Added tests for non-commutative operations with all-const value.
- Retitled patch accordingly.
Sun, Jun 17
Sat, Jun 16
Updated x86 test with utils/update_llc_test_checks.py
Updated x86 asm to contain full ISA.
Added x86 test.
Updated amdgcn test.
Fri, Jun 15
Thu, Jun 14
Wed, Jun 13
Tue, Jun 12
Changed comments as requested.
Mon, Jun 11
Thank you! I am in favor of this change even despite what we have discussed today. If we eventually want to create target ISD nodes it could be done on top of it and separately, but currently I see no such need.
A separate note: SIISelLowering.cpp has really overgrown, it is already about 8000 lines. Maybe we shall consider splitting it into separate pieces as a separate change. Like this stuff is something like SIImageLowering.cpp.
Ah! I see the reviews to fold it into a bfe. I have no concern then, LGTM.
In general for AMDGPU two shifts are better. Any shift immediate can be folded right into the shift instruction while a rather big mask produced by this change would require either extra 4 bytes in the encoding or even worse a move and a register.
Thu, Jun 7
Wed, Jun 6
Tue, Jun 5
Mon, Jun 4
Fri, Jun 1
Thu, May 31
Wed, May 30
Replaced custom instruction with TargetOpcode::BUNDLE.