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Differential D95303

[RISCV] Implement vlsegff intrinsics.
ClosedPublic

Authored by HsiangKai on Jan 23 2021, 10:53 PM.

Details

Reviewers
craig.topper
evandro
frasercrmck
rogfer01
Commits
rGb69932b550ac: [RISCV] Implement vlsegff intrinsics.

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Event Timeline

HsiangKai created this revision.Jan 23 2021, 10:53 PM
Herald added subscribers: NickHung, luismarques, apazos and 23 others. · View Herald TranscriptJan 23 2021, 10:53 PM
HsiangKai requested review of this revision.Jan 23 2021, 10:53 PM
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Harbormaster completed remote builds in B86444: Diff 318811.Jan 23 2021, 11:35 PM
craig.topper added a comment.Jan 25 2021, 10:30 AM

LGTM with that comment.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp
1526

Since this contains ReadVL result and the chain, something like "Results" would be a better name.

1570

Same here

craig.topper accepted this revision.Jan 25 2021, 11:41 AM
This revision is now accepted and ready to land.Jan 25 2021, 11:41 AM
This revision was landed with ongoing or failed builds.Jan 25 2021, 8:03 PM
Closed by commit rGb69932b550ac: [RISCV] Implement vlsegff intrinsics. (authored by HsiangKai). · Explain Why
This revision was automatically updated to reflect the committed changes.
HsiangKai added a commit: rGb69932b550ac: [RISCV] Implement vlsegff intrinsics..

Revision Contents

PathSize
llvm/
include/
llvm/
IR/
29 lines
lib/
Target/
RISCV/
2 lines
72 lines
3 lines
85 lines
20 lines
test/
CodeGen/
RISCV/
rvv/
89 lines
5239 lines
89 lines
5681 lines

Diff 319194

llvm/include/llvm/IR/IntrinsicsRISCV.td

Show First 20 Lines • Show All 518 Lines • ▼ Show 20 Lines class RISCVUSSegLoadMask<int nf>
: Intrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>, : Intrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
!add(nf, -1))), !add(nf, -1))),
!listconcat(!listsplat(LLVMMatchType<0>, nf), !listconcat(!listsplat(LLVMMatchType<0>, nf),
[LLVMPointerToElt<0>, [LLVMPointerToElt<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty]), llvm_anyint_ty]),
[NoCapture<ArgIndex<nf>>, IntrReadMem]>, RISCVVIntrinsic; [NoCapture<ArgIndex<nf>>, IntrReadMem]>, RISCVVIntrinsic;
// For unit stride fault-only-first segment load
// Input: (pointer, vl)
// Output: (data, vl)
// NOTE: We model this with default memory properties since we model writing
// VL as a side effect. IntrReadMem, IntrHasSideEffects does not work.
class RISCVUSSegLoadFF<int nf>
: Intrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
!add(nf, -1)), [llvm_anyint_ty]),
[LLVMPointerToElt<0>, LLVMMatchType<1>],
[NoCapture<ArgIndex<0>>]>, RISCVVIntrinsic;
// For unit stride fault-only-first segment load with mask
// Input: (maskedoff, pointer, mask, vl)
// Output: (data, vl)
// NOTE: We model this with default memory properties since we model writing
// VL as a side effect. IntrReadMem, IntrHasSideEffects does not work.
class RISCVUSSegLoadFFMask<int nf>
: Intrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
!add(nf, -1)), [llvm_anyint_ty]),
!listconcat(!listsplat(LLVMMatchType<0>, nf),
[LLVMPointerToElt<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMMatchType<1>]),
[NoCapture<ArgIndex<nf>>]>, RISCVVIntrinsic;
// For stride segment load // For stride segment load
// Input: (pointer, offset, vl) // Input: (pointer, offset, vl)
class RISCVSSegLoad<int nf> class RISCVSSegLoad<int nf>
: Intrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>, : Intrinsic<!listconcat([llvm_anyvector_ty], !listsplat(LLVMMatchType<0>,
!add(nf, -1))), !add(nf, -1))),
[LLVMPointerToElt<0>, llvm_anyint_ty, LLVMMatchType<1>], [LLVMPointerToElt<0>, llvm_anyint_ty, LLVMMatchType<1>],
[NoCapture<ArgIndex<0>>, IntrReadMem]>, RISCVVIntrinsic; [NoCapture<ArgIndex<0>>, IntrReadMem]>, RISCVVIntrinsic;
// For stride segment load with mask // For stride segment load with mask
▲ Show 20 Lines • Show All 191 Lines • ▼ Show 20 Lineslet TargetPrefix = "riscv" in {
multiclass RISCVAMO { multiclass RISCVAMO {
def "int_riscv_" # NAME : RISCVAMONoMask; def "int_riscv_" # NAME : RISCVAMONoMask;
def "int_riscv_" # NAME # "_mask" : RISCVAMOMask; def "int_riscv_" # NAME # "_mask" : RISCVAMOMask;
} }
multiclass RISCVUSSegLoad<int nf> { multiclass RISCVUSSegLoad<int nf> {
def "int_riscv_" # NAME : RISCVUSSegLoad<nf>; def "int_riscv_" # NAME : RISCVUSSegLoad<nf>;
def "int_riscv_" # NAME # "_mask" : RISCVUSSegLoadMask<nf>; def "int_riscv_" # NAME # "_mask" : RISCVUSSegLoadMask<nf>;
} }
multiclass RISCVUSSegLoadFF<int nf> {
def "int_riscv_" # NAME : RISCVUSSegLoadFF<nf>;
def "int_riscv_" # NAME # "_mask" : RISCVUSSegLoadFFMask<nf>;
}
multiclass RISCVSSegLoad<int nf> { multiclass RISCVSSegLoad<int nf> {
def "int_riscv_" # NAME : RISCVSSegLoad<nf>; def "int_riscv_" # NAME : RISCVSSegLoad<nf>;
def "int_riscv_" # NAME # "_mask" : RISCVSSegLoadMask<nf>; def "int_riscv_" # NAME # "_mask" : RISCVSSegLoadMask<nf>;
} }
multiclass RISCVISegLoad<int nf> { multiclass RISCVISegLoad<int nf> {
def "int_riscv_" # NAME : RISCVISegLoad<nf>; def "int_riscv_" # NAME : RISCVISegLoad<nf>;
def "int_riscv_" # NAME # "_mask" : RISCVISegLoadMask<nf>; def "int_riscv_" # NAME # "_mask" : RISCVISegLoadMask<nf>;
} }
▲ Show 20 Lines • Show All 301 Lines • ▼ Show 20 Lineslet TargetPrefix = "riscv" in {
def int_riscv_vid_mask : Intrinsic<[llvm_anyvector_ty], def int_riscv_vid_mask : Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, [LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty], llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic; [IntrNoMem]>, RISCVVIntrinsic;
foreach nf = [2, 3, 4, 5, 6, 7, 8] in { foreach nf = [2, 3, 4, 5, 6, 7, 8] in {
defm vlseg # nf : RISCVUSSegLoad<nf>; defm vlseg # nf : RISCVUSSegLoad<nf>;
defm vlseg # nf # ff : RISCVUSSegLoadFF<nf>;
defm vlsseg # nf : RISCVSSegLoad<nf>; defm vlsseg # nf : RISCVSSegLoad<nf>;
defm vloxseg # nf : RISCVISegLoad<nf>; defm vloxseg # nf : RISCVISegLoad<nf>;
defm vluxseg # nf : RISCVISegLoad<nf>; defm vluxseg # nf : RISCVISegLoad<nf>;
defm vsseg # nf : RISCVUSSegStore<nf>; defm vsseg # nf : RISCVUSSegStore<nf>;
defm vssseg # nf : RISCVSSegStore<nf>; defm vssseg # nf : RISCVSSegStore<nf>;
defm vsoxseg # nf : RISCVISegStore<nf>; defm vsoxseg # nf : RISCVISegStore<nf>;
defm vsuxseg # nf : RISCVISegStore<nf>; defm vsuxseg # nf : RISCVISegStore<nf>;
} }
} // TargetPrefix = "riscv" } // TargetPrefix = "riscv"

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Linespublic:
bool MatchSLLIUW(SDNode *N) const; bool MatchSLLIUW(SDNode *N) const;
bool selectVSplat(SDValue N, SDValue &SplatVal); bool selectVSplat(SDValue N, SDValue &SplatVal);
bool selectVSplatSimm5(SDValue N, SDValue &SplatVal); bool selectVSplatSimm5(SDValue N, SDValue &SplatVal);
bool selectVSplatUimm5(SDValue N, SDValue &SplatVal); bool selectVSplatUimm5(SDValue N, SDValue &SplatVal);
void selectVLSEG(SDNode *Node, unsigned IntNo, bool IsStrided); void selectVLSEG(SDNode *Node, unsigned IntNo, bool IsStrided);
void selectVLSEGMask(SDNode *Node, unsigned IntNo, bool IsStrided); void selectVLSEGMask(SDNode *Node, unsigned IntNo, bool IsStrided);
void selectVLSEGFF(SDNode *Node);
void selectVLSEGFFMask(SDNode *Node);
void selectVLXSEG(SDNode *Node, unsigned IntNo); void selectVLXSEG(SDNode *Node, unsigned IntNo);
void selectVLXSEGMask(SDNode *Node, unsigned IntNo); void selectVLXSEGMask(SDNode *Node, unsigned IntNo);
void selectVSSEG(SDNode *Node, unsigned IntNo, bool IsStrided); void selectVSSEG(SDNode *Node, unsigned IntNo, bool IsStrided);
void selectVSSEGMask(SDNode *Node, unsigned IntNo, bool IsStrided); void selectVSSEGMask(SDNode *Node, unsigned IntNo, bool IsStrided);
void selectVSXSEG(SDNode *Node, unsigned IntNo); void selectVSXSEG(SDNode *Node, unsigned IntNo);
void selectVSXSEGMask(SDNode *Node, unsigned IntNo); void selectVSXSEGMask(SDNode *Node, unsigned IntNo);
// Include the pieces autogenerated from the target description. // Include the pieces autogenerated from the target description.
#include "RISCVGenDAGISel.inc" #include "RISCVGenDAGISel.inc"
private: private:
void doPeepholeLoadStoreADDI(); void doPeepholeLoadStoreADDI();
}; };
} }
#endif #endif

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Show First 20 Lines • Show All 216 Lines • ▼ Show 20 Lines for (unsigned I = 0; I < NF; ++I)
ReplaceUses(SDValue(Node, I), ReplaceUses(SDValue(Node, I),
CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL, CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL,
VT, SuperReg)); VT, SuperReg));
ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); ReplaceUses(SDValue(Node, NF), SDValue(Load, 1));
CurDAG->RemoveDeadNode(Node); CurDAG->RemoveDeadNode(Node);
} }
void RISCVDAGToDAGISel::selectVLSEGFF(SDNode *Node) {
SDLoc DL(Node);
unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
unsigned NF = Node->getNumValues() - 2; // Do not count Chain and Glue.
EVT VT = Node->getValueType(0);
unsigned ScalarSize = VT.getScalarSizeInBits();
MVT XLenVT = Subtarget->getXLenVT();
RISCVVLMUL LMUL = getLMUL(VT);
SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT);
SmallVector<SDValue, 5> Operands;
Operands.push_back(Node->getOperand(2)); // Base pointer.
Operands.push_back(Node->getOperand(3)); // VL.
Operands.push_back(SEW);
Operands.push_back(Node->getOperand(0)); // Chain.
const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(
IntNo, ScalarSize, static_cast<unsigned>(LMUL),
static_cast<unsigned>(RISCVVLMUL::LMUL_1));
SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other,
MVT::Glue, Operands);
SDValue SuperReg = SDValue(Load, 0);
for (unsigned I = 0; I < NF; ++I)
ReplaceUses(SDValue(Node, I),
CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL,
VT, SuperReg));
ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); // Chain.
ReplaceUses(SDValue(Node, NF + 1), SDValue(Load, 2)); // Glue.
CurDAG->RemoveDeadNode(Node);
}
void RISCVDAGToDAGISel::selectVLSEGFFMask(SDNode *Node) {
SDLoc DL(Node);
unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
unsigned NF = Node->getNumValues() - 2; // Do not count Chain and Glue.
EVT VT = Node->getValueType(0);
unsigned ScalarSize = VT.getScalarSizeInBits();
MVT XLenVT = Subtarget->getXLenVT();
RISCVVLMUL LMUL = getLMUL(VT);
SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT);
SmallVector<SDValue, 8> Regs(Node->op_begin() + 2, Node->op_begin() + 2 + NF);
SDValue MaskedOff = createTuple(*CurDAG, Regs, NF, LMUL);
SmallVector<SDValue, 7> Operands;
Operands.push_back(MaskedOff);
Operands.push_back(Node->getOperand(NF + 2)); // Base pointer.
Operands.push_back(Node->getOperand(NF + 3)); // Mask.
Operands.push_back(Node->getOperand(NF + 4)); // VL.
Operands.push_back(SEW);
Operands.push_back(Node->getOperand(0)); /// Chain.
const RISCVZvlssegTable::RISCVZvlsseg *P = RISCVZvlssegTable::getPseudo(
IntNo, ScalarSize, static_cast<unsigned>(LMUL),
static_cast<unsigned>(RISCVVLMUL::LMUL_1));
SDNode *Load = CurDAG->getMachineNode(P->Pseudo, DL, MVT::Untyped, MVT::Other,
MVT::Glue, Operands);
SDValue SuperReg = SDValue(Load, 0);
for (unsigned I = 0; I < NF; ++I)
ReplaceUses(SDValue(Node, I),
CurDAG->getTargetExtractSubreg(getSubregIndexByEVT(VT, I), DL,
VT, SuperReg));
ReplaceUses(SDValue(Node, NF), SDValue(Load, 1)); // Chain.
ReplaceUses(SDValue(Node, NF + 1), SDValue(Load, 2)); // Glue.
CurDAG->RemoveDeadNode(Node);
}
void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, unsigned IntNo) { void RISCVDAGToDAGISel::selectVLXSEG(SDNode *Node, unsigned IntNo) {
SDLoc DL(Node); SDLoc DL(Node);
unsigned NF = Node->getNumValues() - 1; unsigned NF = Node->getNumValues() - 1;
EVT VT = Node->getValueType(0); EVT VT = Node->getValueType(0);
unsigned ScalarSize = VT.getScalarSizeInBits(); unsigned ScalarSize = VT.getScalarSizeInBits();
MVT XLenVT = Subtarget->getXLenVT(); MVT XLenVT = Subtarget->getXLenVT();
RISCVVLMUL LMUL = getLMUL(VT); RISCVVLMUL LMUL = getLMUL(VT);
SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT); SDValue SEW = CurDAG->getTargetConstant(ScalarSize, DL, XLenVT);
▲ Show 20 Lines • Show All 461 Lines • ▼ Show 20 Lines case ISD::INTRINSIC_VOID: {
case Intrinsic::riscv_vsuxseg7_mask: case Intrinsic::riscv_vsuxseg7_mask:
case Intrinsic::riscv_vsuxseg8_mask: { case Intrinsic::riscv_vsuxseg8_mask: {
selectVSXSEGMask(Node, IntNo); selectVSXSEGMask(Node, IntNo);
return; return;
} }
} }
break; break;
} }
case RISCVISD::VLSEGFF: {
selectVLSEGFF(Node);
return;
}
case RISCVISD::VLSEGFF_MASK: {
selectVLSEGFFMask(Node);
return;
}
} }
// Select the default instruction. // Select the default instruction.
SelectCode(Node); SelectCode(Node);
} }
bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand( bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand(
const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) { const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) {
▲ Show 20 Lines • Show All 340 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelLowering.h

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Linesenum NodeType : unsigned {
SPLAT_VECTOR_I64, SPLAT_VECTOR_I64,
// Read VLENB CSR // Read VLENB CSR
READ_VLENB, READ_VLENB,
// Truncates a RVV integer vector by one power-of-two. // Truncates a RVV integer vector by one power-of-two.
TRUNCATE_VECTOR, TRUNCATE_VECTOR,
// Unit-stride fault-only-first load // Unit-stride fault-only-first load
VLEFF, VLEFF,
VLEFF_MASK, VLEFF_MASK,
// Unit-stride fault-only-first segment load
VLSEGFF,
VLSEGFF_MASK,
// read vl CSR // read vl CSR
READ_VL, READ_VL,
// Matches the semantics of vslideup/vslidedown. The first operand is the // Matches the semantics of vslideup/vslidedown. The first operand is the
// pass-thru operand, the second is the source vector, and the third is the // pass-thru operand, the second is the source vector, and the third is the
// XLenVT index (either constant or non-constant). // XLenVT index (either constant or non-constant).
VSLIDEUP, VSLIDEUP,
VSLIDEDOWN, VSLIDEDOWN,
// Matches the semantics of the unmasked vid.v instruction. // Matches the semantics of the unmasked vid.v instruction.
▲ Show 20 Lines • Show All 247 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Show First 20 Lines • Show All 1,463 Lines • ▼ Show 20 Lines if (const RISCVVIntrinsicsTable::RISCVVIntrinsicInfo *II =
ScalarOp = DAG.getNode(ExtOpc, DL, Subtarget.getXLenVT(), ScalarOp); ScalarOp = DAG.getNode(ExtOpc, DL, Subtarget.getXLenVT(), ScalarOp);
return DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, Op->getVTList(), return DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, Op->getVTList(),
Operands); Operands);
} }
} }
} }
} }
unsigned NF = 1;
switch (IntNo) { switch (IntNo) {
default: default:
return SDValue(); // Don't custom lower most intrinsics. return SDValue(); // Don't custom lower most intrinsics.
case Intrinsic::riscv_vleff: { case Intrinsic::riscv_vleff: {
SDLoc DL(Op); SDLoc DL(Op);
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Other, MVT::Glue); SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Other, MVT::Glue);
SDValue Load = DAG.getNode(RISCVISD::VLEFF, DL, VTs, Op.getOperand(0), SDValue Load = DAG.getNode(RISCVISD::VLEFF, DL, VTs, Op.getOperand(0),
Op.getOperand(2), Op.getOperand(3)); Op.getOperand(2), Op.getOperand(3));
VTs = DAG.getVTList(Op->getValueType(1), MVT::Other); VTs = DAG.getVTList(Op->getValueType(1), MVT::Other);
SDValue ReadVL = DAG.getNode(RISCVISD::READ_VL, DL, VTs, Load.getValue(2)); SDValue ReadVL = DAG.getNode(RISCVISD::READ_VL, DL, VTs, Load.getValue(2));
return DAG.getMergeValues({Load, ReadVL, Load.getValue(1)}, DL); return DAG.getMergeValues({Load, ReadVL, Load.getValue(1)}, DL);
} }
case Intrinsic::riscv_vleff_mask: { case Intrinsic::riscv_vleff_mask: {
SDLoc DL(Op); SDLoc DL(Op);
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Other, MVT::Glue); SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Other, MVT::Glue);
SDValue Load = DAG.getNode(RISCVISD::VLEFF_MASK, DL, VTs, Op.getOperand(0), SDValue Load = DAG.getNode(RISCVISD::VLEFF_MASK, DL, VTs, Op.getOperand(0),
Op.getOperand(2), Op.getOperand(3), Op.getOperand(2), Op.getOperand(3),
Op.getOperand(4), Op.getOperand(5)); Op.getOperand(4), Op.getOperand(5));
VTs = DAG.getVTList(Op->getValueType(1), MVT::Other); VTs = DAG.getVTList(Op->getValueType(1), MVT::Other);
SDValue ReadVL = DAG.getNode(RISCVISD::READ_VL, DL, VTs, Load.getValue(2)); SDValue ReadVL = DAG.getNode(RISCVISD::READ_VL, DL, VTs, Load.getValue(2));
return DAG.getMergeValues({Load, ReadVL, Load.getValue(1)}, DL); return DAG.getMergeValues({Load, ReadVL, Load.getValue(1)}, DL);
} }
case Intrinsic::riscv_vlseg8ff:
NF++;
LLVM_FALLTHROUGH;
case Intrinsic::riscv_vlseg7ff:
NF++;
LLVM_FALLTHROUGH;
case Intrinsic::riscv_vlseg6ff:
NF++;
LLVM_FALLTHROUGH;
case Intrinsic::riscv_vlseg5ff:
NF++;
LLVM_FALLTHROUGH;
case Intrinsic::riscv_vlseg4ff:
NF++;
LLVM_FALLTHROUGH;
case Intrinsic::riscv_vlseg3ff:
NF++;
LLVM_FALLTHROUGH;
case Intrinsic::riscv_vlseg2ff: {
NF++;
SDLoc DL(Op);
SmallVector<EVT, 8> EVTs(NF, Op.getValueType());
EVTs.push_back(MVT::Other);
EVTs.push_back(MVT::Glue);
SDVTList VTs = DAG.getVTList(EVTs);
SDValue Load =
DAG.getNode(RISCVISD::VLSEGFF, DL, VTs, Op.getOperand(0),
Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
VTs = DAG.getVTList(Op->getValueType(NF), MVT::Other);
SDValue ReadVL = DAG.getNode(RISCVISD::READ_VL, DL, VTs,
/*Glue*/ Load.getValue(NF + 1));
SmallVector<SDValue, 8> Results;
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Since this contains ReadVL result and the chain, something like "Results" would be a better name.

craig.topper: Since this contains ReadVL result and the chain, something like "Results" would be a better…
for (unsigned i = 0; i < NF; ++i)
Results.push_back(Load.getValue(i));
Results.push_back(ReadVL);
Results.push_back(Load.getValue(NF)); // Chain.
return DAG.getMergeValues(Results, DL);
}
case Intrinsic::riscv_vlseg8ff_mask:
NF++;
LLVM_FALLTHROUGH;
case Intrinsic::riscv_vlseg7ff_mask:
NF++;
LLVM_FALLTHROUGH;
case Intrinsic::riscv_vlseg6ff_mask:
NF++;
LLVM_FALLTHROUGH;
case Intrinsic::riscv_vlseg5ff_mask:
NF++;
LLVM_FALLTHROUGH;
case Intrinsic::riscv_vlseg4ff_mask:
NF++;
LLVM_FALLTHROUGH;
case Intrinsic::riscv_vlseg3ff_mask:
NF++;
LLVM_FALLTHROUGH;
case Intrinsic::riscv_vlseg2ff_mask: {
NF++;
SDLoc DL(Op);
SmallVector<EVT, 8> EVTs(NF, Op.getValueType());
EVTs.push_back(MVT::Other);
EVTs.push_back(MVT::Glue);
SDVTList VTs = DAG.getVTList(EVTs);
SmallVector<SDValue, 13> LoadOps;
LoadOps.push_back(Op.getOperand(0)); // Chain.
LoadOps.push_back(Op.getOperand(1)); // Intrinsic ID.
for (unsigned i = 0; i < NF; ++i)
LoadOps.push_back(Op.getOperand(2 + i)); // MaskedOff.
LoadOps.push_back(Op.getOperand(2 + NF)); // Base.
LoadOps.push_back(Op.getOperand(3 + NF)); // Mask.
LoadOps.push_back(Op.getOperand(4 + NF)); // VL.
SDValue Load = DAG.getNode(RISCVISD::VLSEGFF_MASK, DL, VTs, LoadOps);
VTs = DAG.getVTList(Op->getValueType(NF), MVT::Other);
SDValue ReadVL = DAG.getNode(RISCVISD::READ_VL, DL, VTs,
/*Glue*/ Load.getValue(NF + 1));
SmallVector<SDValue, 8> Results;
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Same here

craig.topper: Same here
for (unsigned i = 0; i < NF; ++i)
Results.push_back(Load.getValue(i));
Results.push_back(ReadVL);
Results.push_back(Load.getValue(NF)); // Chain.
return DAG.getMergeValues(Results, DL);
}
} }
} }
// Returns the opcode of the target-specific SDNode that implements the 32-bit // Returns the opcode of the target-specific SDNode that implements the 32-bit
// form of the given Opcode. // form of the given Opcode.
static RISCVISD::NodeType getRISCVWOpcode(unsigned Opcode) { static RISCVISD::NodeType getRISCVWOpcode(unsigned Opcode) {
switch (Opcode) { switch (Opcode) {
default: default:
▲ Show 20 Lines • Show All 2,512 Lines • ▼ Show 20 Lines#define NODE_NAME_CASE(NODE) \
NODE_NAME_CASE(GORCI) NODE_NAME_CASE(GORCI)
NODE_NAME_CASE(GORCIW) NODE_NAME_CASE(GORCIW)
NODE_NAME_CASE(VMV_X_S) NODE_NAME_CASE(VMV_X_S)
NODE_NAME_CASE(SPLAT_VECTOR_I64) NODE_NAME_CASE(SPLAT_VECTOR_I64)
NODE_NAME_CASE(READ_VLENB) NODE_NAME_CASE(READ_VLENB)
NODE_NAME_CASE(TRUNCATE_VECTOR) NODE_NAME_CASE(TRUNCATE_VECTOR)
NODE_NAME_CASE(VLEFF) NODE_NAME_CASE(VLEFF)
NODE_NAME_CASE(VLEFF_MASK) NODE_NAME_CASE(VLEFF_MASK)
NODE_NAME_CASE(VLSEGFF)
NODE_NAME_CASE(VLSEGFF_MASK)
NODE_NAME_CASE(READ_VL) NODE_NAME_CASE(READ_VL)
NODE_NAME_CASE(VSLIDEUP) NODE_NAME_CASE(VSLIDEUP)
NODE_NAME_CASE(VSLIDEDOWN) NODE_NAME_CASE(VSLIDEDOWN)
NODE_NAME_CASE(VID) NODE_NAME_CASE(VID)
} }
// clang-format on // clang-format on
return nullptr; return nullptr;
#undef NODE_NAME_CASE #undef NODE_NAME_CASE
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llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 450 Lines • ▼ Show 20 Lines string VInst = !subst("_M8", "",
!subst("_B16", "", !subst("_B16", "",
!subst("_B32", "", !subst("_B32", "",
!subst("_B64", "", !subst("_B64", "",
!subst("_MASK", "", !subst("_MASK", "",
!subst("Pseudo", "", PseudoInst)))))))))))))))); !subst("Pseudo", "", PseudoInst))))))))))))))));
} }
class ToLowerCase<string Upper> { class ToLowerCase<string Upper> {
string L = !subst("VLSEG", "vlseg", string L = !subst("FF", "ff",
!subst("VLSEG", "vlseg",
!subst("VLSSEG", "vlsseg", !subst("VLSSEG", "vlsseg",
!subst("VSSEG", "vsseg", !subst("VSSEG", "vsseg",
!subst("VSSSEG", "vssseg", !subst("VSSSEG", "vssseg",
!subst("VLOXSEG", "vloxseg", !subst("VLOXSEG", "vloxseg",
!subst("VLUXSEG", "vluxseg", !subst("VLUXSEG", "vluxseg",
!subst("VSOXSEG", "vsoxseg", !subst("VSOXSEG", "vsoxseg",
!subst("VSUXSEG", "vsuxseg", Upper)))))))); !subst("VSUXSEG", "vsuxseg", Upper)))))))));
} }
// Example: PseudoVLSEG2E32_V_M2 -> int_riscv_vlseg2 // Example: PseudoVLSEG2E32_V_M2 -> int_riscv_vlseg2
// Example: PseudoVLSEG2E32_V_M2_MASK -> int_riscv_vlseg2_mask // Example: PseudoVLSEG2E32_V_M2_MASK -> int_riscv_vlseg2_mask
class PseudoToIntrinsic<string PseudoInst, bit IsMasked> { class PseudoToIntrinsic<string PseudoInst, bit IsMasked> {
string Intrinsic = !strconcat("int_riscv_", string Intrinsic = !strconcat("int_riscv_",
ToLowerCase< ToLowerCase<
!subst("E8", "", !subst("E8", "",
▲ Show 20 Lines • Show All 1,264 Lines • ▼ Show 20 Lines
} }
multiclass VPseudoConversionV_W { multiclass VPseudoConversionV_W {
defvar constraint = "@earlyclobber $rd"; defvar constraint = "@earlyclobber $rd";
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint>; defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint>;
} }
multiclass VPseudoUSSegLoad { multiclass VPseudoUSSegLoad<bit isFF> {
foreach eew = EEWList in { foreach eew = EEWList in {
foreach lmul = MxSet<eew>.m in { foreach lmul = MxSet<eew>.m in {
defvar LInfo = lmul.MX; defvar LInfo = lmul.MX;
let VLMul = lmul.value in { let VLMul = lmul.value in {
foreach nf = NFSet<lmul>.L in { foreach nf = NFSet<lmul>.L in {
defvar vreg = SegRegClass<lmul, nf>.RC; defvar vreg = SegRegClass<lmul, nf>.RC;
def nf # "E" # eew # "_V_" # LInfo : VPseudoUSSegLoadNoMask<vreg, eew>; defvar FFStr = !if(isFF, "FF", "");
def nf # "E" # eew # "_V_" # LInfo # "_MASK" : VPseudoUSSegLoadMask<vreg, eew>; def nf # "E" # eew # FFStr # "_V_" # LInfo :
VPseudoUSSegLoadNoMask<vreg, eew>;
def nf # "E" # eew # FFStr # "_V_" # LInfo # "_MASK" :
VPseudoUSSegLoadMask<vreg, eew>;
} }
} }
} }
} }
} }
multiclass VPseudoSSegLoad { multiclass VPseudoSSegLoad {
foreach eew = EEWList in { foreach eew = EEWList in {
▲ Show 20 Lines • Show All 1,317 Lines • ▼ Show 20 Lines
let hasSideEffects = 1, Defs = [VL] in let hasSideEffects = 1, Defs = [VL] in
foreach eew = EEWList in { foreach eew = EEWList in {
defm PseudoVLE # eew # FF : VPseudoUSLoad; defm PseudoVLE # eew # FF : VPseudoUSLoad;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 7.8. Vector Load/Store Segment Instructions // 7.8. Vector Load/Store Segment Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm PseudoVLSEG : VPseudoUSSegLoad; defm PseudoVLSEG : VPseudoUSSegLoad</*fault-only-first*/false>;
defm PseudoVLSSEG : VPseudoSSegLoad; defm PseudoVLSSEG : VPseudoSSegLoad;
defm PseudoVLOXSEG : VPseudoISegLoad; defm PseudoVLOXSEG : VPseudoISegLoad;
defm PseudoVLUXSEG : VPseudoISegLoad; defm PseudoVLUXSEG : VPseudoISegLoad;
defm PseudoVSSEG : VPseudoUSSegStore; defm PseudoVSSEG : VPseudoUSSegStore;
defm PseudoVSSSEG : VPseudoSSegStore; defm PseudoVSSSEG : VPseudoSSegStore;
defm PseudoVSOXSEG : VPseudoISegStore; defm PseudoVSOXSEG : VPseudoISegStore;
defm PseudoVSUXSEG : VPseudoISegStore; defm PseudoVSUXSEG : VPseudoISegStore;
// vlseg<nf>e<eew>ff.v may update VL register
let hasSideEffects = 1, Defs = [VL] in
defm PseudoVLSEG : VPseudoUSSegLoad</*fault-only-first*/true>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 8. Vector AMO Operations // 8. Vector AMO Operations
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm PseudoVAMOSWAP : VPseudoAMO; defm PseudoVAMOSWAP : VPseudoAMO;
defm PseudoVAMOADD : VPseudoAMO; defm PseudoVAMOADD : VPseudoAMO;
defm PseudoVAMOXOR : VPseudoAMO; defm PseudoVAMOXOR : VPseudoAMO;
defm PseudoVAMOAND : VPseudoAMO; defm PseudoVAMOAND : VPseudoAMO;
defm PseudoVAMOOR : VPseudoAMO; defm PseudoVAMOOR : VPseudoAMO;
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llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \
; RUN: -verify-machineinstrs < %s | FileCheck %s
declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i32)
declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i32)
define void @test_vlseg2ff_dead_value(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_dead_value:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v0, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 2
store i32 %1, i32* %outvl
ret void
}
define void @test_vlseg2ff_mask_dead_value(<vscale x 16 x i16> %val, i16* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_dead_value:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v8, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 2
store i32 %1, i32* %outvl
ret void
}
define <vscale x 16 x i16> @test_vlseg2ff_dead_vl(i16* %base, i32 %vl) {
; CHECK-LABEL: test_vlseg2ff_dead_vl:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 1
ret <vscale x 16 x i16> %1
}
define <vscale x 16 x i16> @test_vlseg2ff_mask_dead_vl(<vscale x 16 x i16> %val, i16* %base, i32 %vl, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlseg2ff_mask_dead_vl:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 1
ret <vscale x 16 x i16> %1
}
define void @test_vlseg2ff_dead_all(i16* %base, i32 %vl) {
; CHECK-LABEL: test_vlseg2ff_dead_all:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v0, (a0)
; CHECK-NEXT: ret
entry:
tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i32 %vl)
ret void
}
define void @test_vlseg2ff_mask_dead_all(<vscale x 16 x i16> %val, i16* %base, i32 %vl, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlseg2ff_mask_dead_all:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v8, (a0), v0.t
; CHECK-NEXT: ret
entry:
tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl)
ret void
}

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll

  • This file was added.
  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \
; RUN: -verify-machineinstrs < %s | FileCheck %s
declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i32)
declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i32)
define <vscale x 16 x i16> @test_vlseg2ff_nxv16i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 16 x i16> %1
}
define <vscale x 16 x i16> @test_vlseg2ff_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 16 x i16> %1
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg2ff.nxv1i8(i8* , i32)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i8> @test_vlseg2ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vlseg2e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg2ff.nxv1i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlseg2ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 1 x i8> %1
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg3ff.nxv1i8(i8* , i32)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i8> @test_vlseg3ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vlseg3e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg3ff.nxv1i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlseg3ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 1 x i8> %1
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg4ff.nxv1i8(i8* , i32)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i8> @test_vlseg4ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vlseg4e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg4ff.nxv1i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlseg4ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 1 x i8> %1
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg5ff.nxv1i8(i8* , i32)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i8> @test_vlseg5ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vlseg5e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg5ff.nxv1i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlseg5ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 1 x i8> %1
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg6ff.nxv1i8(i8* , i32)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i8> @test_vlseg6ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vlseg6e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg6ff.nxv1i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlseg6ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 1 x i8> %1
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg7ff.nxv1i8(i8* , i32)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i8> @test_vlseg7ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vlseg7e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg7ff.nxv1i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlseg7ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 1 x i8> %1
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg8ff.nxv1i8(i8* , i32)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i8> @test_vlseg8ff_nxv1i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vlseg8e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg8ff.nxv1i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlseg8ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 1 x i8> %1
}
declare {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg2ff.nxv16i8(i8* , i32)
declare {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32)
define <vscale x 16 x i8> @test_vlseg2ff_nxv16i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vlseg2e8ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg2ff.nxv16i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 16 x i8> %1
}
define <vscale x 16 x i8> @test_vlseg2ff_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vlseg2e8ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 16 x i8> %1
}
declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg3ff.nxv16i8(i8* , i32)
declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32)
define <vscale x 16 x i8> @test_vlseg3ff_nxv16i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vlseg3e8ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg3ff.nxv16i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 16 x i8> %1
}
define <vscale x 16 x i8> @test_vlseg3ff_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vlseg3e8ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 16 x i8> %1
}
declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg4ff.nxv16i8(i8* , i32)
declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i32)
define <vscale x 16 x i8> @test_vlseg4ff_nxv16i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vlseg4e8ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg4ff.nxv16i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 16 x i8> %1
}
define <vscale x 16 x i8> @test_vlseg4ff_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vmv2r.v v12, v6
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vlseg4e8ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 16 x i8> %1
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg2ff.nxv2i32(i32* , i32)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i32> @test_vlseg2ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg2e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg2ff.nxv2i32(i32* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlseg2ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 2 x i32> %1
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg3ff.nxv2i32(i32* , i32)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg3ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i32> @test_vlseg3ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg3e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg3ff.nxv2i32(i32* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlseg3ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg3ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 2 x i32> %1
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg4ff.nxv2i32(i32* , i32)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg4ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i32> @test_vlseg4ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg4e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg4ff.nxv2i32(i32* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlseg4ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg4ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 2 x i32> %1
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg5ff.nxv2i32(i32* , i32)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg5ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i32> @test_vlseg5ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg5e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg5ff.nxv2i32(i32* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlseg5ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg5ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 2 x i32> %1
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg6ff.nxv2i32(i32* , i32)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg6ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i32> @test_vlseg6ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg6e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg6ff.nxv2i32(i32* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlseg6ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg6ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 2 x i32> %1
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg7ff.nxv2i32(i32* , i32)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg7ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i32> @test_vlseg7ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg7e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg7ff.nxv2i32(i32* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlseg7ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg7ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 2 x i32> %1
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg8ff.nxv2i32(i32* , i32)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg8ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i32> @test_vlseg8ff_nxv2i32(i32* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg8e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg8ff.nxv2i32(i32* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlseg8ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} @llvm.riscv.vlseg8ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 2 x i32> %1
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg2ff.nxv4i16(i16* , i32)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)
define <vscale x 4 x i16> @test_vlseg2ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg2ff.nxv4i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlseg2ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 4 x i16> %1
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg3ff.nxv4i16(i16* , i32)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)
define <vscale x 4 x i16> @test_vlseg3ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg3ff.nxv4i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlseg3ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 4 x i16> %1
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg4ff.nxv4i16(i16* , i32)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)
define <vscale x 4 x i16> @test_vlseg4ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg4ff.nxv4i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlseg4ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 4 x i16> %1
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg5ff.nxv4i16(i16* , i32)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg5ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)
define <vscale x 4 x i16> @test_vlseg5ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg5ff.nxv4i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlseg5ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg5ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 4 x i16> %1
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg6ff.nxv4i16(i16* , i32)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg6ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)
define <vscale x 4 x i16> @test_vlseg6ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg6ff.nxv4i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlseg6ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg6ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 4 x i16> %1
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg7ff.nxv4i16(i16* , i32)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg7ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)
define <vscale x 4 x i16> @test_vlseg7ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg7ff.nxv4i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlseg7ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg7ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 4 x i16> %1
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg8ff.nxv4i16(i16* , i32)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg8ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i32)
define <vscale x 4 x i16> @test_vlseg8ff_nxv4i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg8ff.nxv4i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlseg8ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} @llvm.riscv.vlseg8ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 4 x i16> %1
}
declare {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg2ff.nxv1i32(i32* , i32)
declare {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i32> @test_vlseg2ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg2e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg2ff.nxv1i32(i32* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 1 x i32> %1
}
define <vscale x 1 x i32> @test_vlseg2ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 1 x i32> %1
}
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg3ff.nxv1i32(i32* , i32)
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg3ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i32> @test_vlseg3ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg3e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg3ff.nxv1i32(i32* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 1 x i32> %1
}
define <vscale x 1 x i32> @test_vlseg3ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg3ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 1 x i32> %1
}
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg4ff.nxv1i32(i32* , i32)
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg4ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i32> @test_vlseg4ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg4e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg4ff.nxv1i32(i32* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 1 x i32> %1
}
define <vscale x 1 x i32> @test_vlseg4ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg4ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 1 x i32> %1
}
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg5ff.nxv1i32(i32* , i32)
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg5ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i32> @test_vlseg5ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg5e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg5ff.nxv1i32(i32* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 1 x i32> %1
}
define <vscale x 1 x i32> @test_vlseg5ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg5ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 1 x i32> %1
}
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg6ff.nxv1i32(i32* , i32)
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg6ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i32> @test_vlseg6ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg6e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg6ff.nxv1i32(i32* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 1 x i32> %1
}
define <vscale x 1 x i32> @test_vlseg6ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg6ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 1 x i32> %1
}
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg7ff.nxv1i32(i32* , i32)
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg7ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i32> @test_vlseg7ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg7e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg7ff.nxv1i32(i32* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 1 x i32> %1
}
define <vscale x 1 x i32> @test_vlseg7ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg7ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 1 x i32> %1
}
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg8ff.nxv1i32(i32* , i32)
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg8ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i32> @test_vlseg8ff_nxv1i32(i32* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg8e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg8ff.nxv1i32(i32* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 1 x i32> %1
}
define <vscale x 1 x i32> @test_vlseg8ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} @llvm.riscv.vlseg8ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 1 x i32> %1
}
declare {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg2ff.nxv8i16(i16* , i32)
declare {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32)
define <vscale x 8 x i16> @test_vlseg2ff_nxv8i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg2ff.nxv8i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 8 x i16> %1
}
define <vscale x 8 x i16> @test_vlseg2ff_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 8 x i16> %1
}
declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg3ff.nxv8i16(i16* , i32)
declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32)
define <vscale x 8 x i16> @test_vlseg3ff_nxv8i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vlseg3e16ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg3ff.nxv8i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 8 x i16> %1
}
define <vscale x 8 x i16> @test_vlseg3ff_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vlseg3e16ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 8 x i16> %1
}
declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg4ff.nxv8i16(i16* , i32)
declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i32)
define <vscale x 8 x i16> @test_vlseg4ff_nxv8i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vlseg4e16ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg4ff.nxv8i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 8 x i16> %1
}
define <vscale x 8 x i16> @test_vlseg4ff_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vmv2r.v v12, v6
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vlseg4e16ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 8 x i16> %1
}
declare {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg2ff.nxv8i8(i8* , i32)
declare {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)
define <vscale x 8 x i8> @test_vlseg2ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vlseg2e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg2ff.nxv8i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 8 x i8> %1
}
define <vscale x 8 x i8> @test_vlseg2ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 8 x i8> %1
}
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg3ff.nxv8i8(i8* , i32)
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)
define <vscale x 8 x i8> @test_vlseg3ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vlseg3e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg3ff.nxv8i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 8 x i8> %1
}
define <vscale x 8 x i8> @test_vlseg3ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 8 x i8> %1
}
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg4ff.nxv8i8(i8* , i32)
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)
define <vscale x 8 x i8> @test_vlseg4ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vlseg4e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg4ff.nxv8i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 8 x i8> %1
}
define <vscale x 8 x i8> @test_vlseg4ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 8 x i8> %1
}
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg5ff.nxv8i8(i8* , i32)
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)
define <vscale x 8 x i8> @test_vlseg5ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vlseg5e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg5ff.nxv8i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 8 x i8> %1
}
define <vscale x 8 x i8> @test_vlseg5ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 8 x i8> %1
}
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg6ff.nxv8i8(i8* , i32)
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)
define <vscale x 8 x i8> @test_vlseg6ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vlseg6e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg6ff.nxv8i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 8 x i8> %1
}
define <vscale x 8 x i8> @test_vlseg6ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 8 x i8> %1
}
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg7ff.nxv8i8(i8* , i32)
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)
define <vscale x 8 x i8> @test_vlseg7ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vlseg7e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg7ff.nxv8i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 8 x i8> %1
}
define <vscale x 8 x i8> @test_vlseg7ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 8 x i8> %1
}
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg8ff.nxv8i8(i8* , i32)
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i32)
define <vscale x 8 x i8> @test_vlseg8ff_nxv8i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vlseg8e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg8ff.nxv8i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 8 x i8> %1
}
define <vscale x 8 x i8> @test_vlseg8ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 8 x i8> %1
}
declare {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} @llvm.riscv.vlseg2ff.nxv8i32(i32* , i32)
declare {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i1>, i32)
define <vscale x 8 x i32> @test_vlseg2ff_nxv8i32(i32* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vlseg2e32ff.v v4, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} @llvm.riscv.vlseg2ff.nxv8i32(i32* %base, i32 %vl)
%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 8 x i32> %1
}
define <vscale x 8 x i32> @test_vlseg2ff_mask_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vlseg2e32ff.v v4, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 8 x i32> %1
}
declare {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg2ff.nxv4i8(i8* , i32)
declare {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)
define <vscale x 4 x i8> @test_vlseg2ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vlseg2e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg2ff.nxv4i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 4 x i8> %1
}
define <vscale x 4 x i8> @test_vlseg2ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 4 x i8> %1
}
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg3ff.nxv4i8(i8* , i32)
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)
define <vscale x 4 x i8> @test_vlseg3ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vlseg3e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg3ff.nxv4i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 4 x i8> %1
}
define <vscale x 4 x i8> @test_vlseg3ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 4 x i8> %1
}
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg4ff.nxv4i8(i8* , i32)
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)
define <vscale x 4 x i8> @test_vlseg4ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vlseg4e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg4ff.nxv4i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 4 x i8> %1
}
define <vscale x 4 x i8> @test_vlseg4ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 4 x i8> %1
}
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg5ff.nxv4i8(i8* , i32)
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)
define <vscale x 4 x i8> @test_vlseg5ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vlseg5e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg5ff.nxv4i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 4 x i8> %1
}
define <vscale x 4 x i8> @test_vlseg5ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 4 x i8> %1
}
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg6ff.nxv4i8(i8* , i32)
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)
define <vscale x 4 x i8> @test_vlseg6ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vlseg6e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg6ff.nxv4i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 4 x i8> %1
}
define <vscale x 4 x i8> @test_vlseg6ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 4 x i8> %1
}
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg7ff.nxv4i8(i8* , i32)
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)
define <vscale x 4 x i8> @test_vlseg7ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vlseg7e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg7ff.nxv4i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 4 x i8> %1
}
define <vscale x 4 x i8> @test_vlseg7ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 4 x i8> %1
}
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg8ff.nxv4i8(i8* , i32)
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i32)
define <vscale x 4 x i8> @test_vlseg8ff_nxv4i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vlseg8e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg8ff.nxv4i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 4 x i8> %1
}
define <vscale x 4 x i8> @test_vlseg8ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 4 x i8> %1
}
declare {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg2ff.nxv1i16(i16* , i32)
declare {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i16> @test_vlseg2ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg2ff.nxv1i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 1 x i16> %1
}
define <vscale x 1 x i16> @test_vlseg2ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 1 x i16> %1
}
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg3ff.nxv1i16(i16* , i32)
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i16> @test_vlseg3ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg3ff.nxv1i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 1 x i16> %1
}
define <vscale x 1 x i16> @test_vlseg3ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 1 x i16> %1
}
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg4ff.nxv1i16(i16* , i32)
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i16> @test_vlseg4ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg4ff.nxv1i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 1 x i16> %1
}
define <vscale x 1 x i16> @test_vlseg4ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 1 x i16> %1
}
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg5ff.nxv1i16(i16* , i32)
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg5ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i16> @test_vlseg5ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg5ff.nxv1i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 1 x i16> %1
}
define <vscale x 1 x i16> @test_vlseg5ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg5ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 1 x i16> %1
}
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg6ff.nxv1i16(i16* , i32)
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg6ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i16> @test_vlseg6ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg6ff.nxv1i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 1 x i16> %1
}
define <vscale x 1 x i16> @test_vlseg6ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg6ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 1 x i16> %1
}
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg7ff.nxv1i16(i16* , i32)
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg7ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i16> @test_vlseg7ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg7ff.nxv1i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 1 x i16> %1
}
define <vscale x 1 x i16> @test_vlseg7ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg7ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 1 x i16> %1
}
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg8ff.nxv1i16(i16* , i32)
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg8ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i32)
define <vscale x 1 x i16> @test_vlseg8ff_nxv1i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg8ff.nxv1i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 1 x i16> %1
}
define <vscale x 1 x i16> @test_vlseg8ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} @llvm.riscv.vlseg8ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 1 x i16> %1
}
declare {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} @llvm.riscv.vlseg2ff.nxv32i8(i8* , i32)
declare {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i1>, i32)
define <vscale x 32 x i8> @test_vlseg2ff_nxv32i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vlseg2e8ff.v v4, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} @llvm.riscv.vlseg2ff.nxv32i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 32 x i8> %1
}
define <vscale x 32 x i8> @test_vlseg2ff_mask_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i32 %vl, <vscale x 32 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vlseg2e8ff.v v4, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 32 x i8> %1
}
declare {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg2ff.nxv2i8(i8* , i32)
declare {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i8> @test_vlseg2ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vlseg2e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg2ff.nxv2i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 2 x i8> %1
}
define <vscale x 2 x i8> @test_vlseg2ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg2ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 2 x i8> %1
}
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg3ff.nxv2i8(i8* , i32)
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i8> @test_vlseg3ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vlseg3e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg3ff.nxv2i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 2 x i8> %1
}
define <vscale x 2 x i8> @test_vlseg3ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg3ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 2 x i8> %1
}
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg4ff.nxv2i8(i8* , i32)
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i8> @test_vlseg4ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vlseg4e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg4ff.nxv2i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 2 x i8> %1
}
define <vscale x 2 x i8> @test_vlseg4ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg4ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 2 x i8> %1
}
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg5ff.nxv2i8(i8* , i32)
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i8> @test_vlseg5ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vlseg5e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg5ff.nxv2i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 2 x i8> %1
}
define <vscale x 2 x i8> @test_vlseg5ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg5ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 2 x i8> %1
}
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg6ff.nxv2i8(i8* , i32)
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i8> @test_vlseg6ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vlseg6e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg6ff.nxv2i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 2 x i8> %1
}
define <vscale x 2 x i8> @test_vlseg6ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg6ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 2 x i8> %1
}
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg7ff.nxv2i8(i8* , i32)
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i8> @test_vlseg7ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vlseg7e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg7ff.nxv2i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 2 x i8> %1
}
define <vscale x 2 x i8> @test_vlseg7ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg7ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 2 x i8> %1
}
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg8ff.nxv2i8(i8* , i32)
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i8> @test_vlseg8ff_nxv2i8(i8* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vlseg8e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg8ff.nxv2i8(i8* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 2 x i8> %1
}
define <vscale x 2 x i8> @test_vlseg8ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} @llvm.riscv.vlseg8ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 2 x i8> %1
}
declare {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg2ff.nxv2i16(i16* , i32)
declare {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i16> @test_vlseg2ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg2ff.nxv2i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 2 x i16> %1
}
define <vscale x 2 x i16> @test_vlseg2ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg2ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 2 x i16> %1
}
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg3ff.nxv2i16(i16* , i32)
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i16> @test_vlseg3ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg3ff.nxv2i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 2 x i16> %1
}
define <vscale x 2 x i16> @test_vlseg3ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg3ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 2 x i16> %1
}
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg4ff.nxv2i16(i16* , i32)
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i16> @test_vlseg4ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg4ff.nxv2i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 2 x i16> %1
}
define <vscale x 2 x i16> @test_vlseg4ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg4ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 2 x i16> %1
}
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg5ff.nxv2i16(i16* , i32)
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg5ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i16> @test_vlseg5ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg5ff.nxv2i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 2 x i16> %1
}
define <vscale x 2 x i16> @test_vlseg5ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg5ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 2 x i16> %1
}
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg6ff.nxv2i16(i16* , i32)
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg6ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i16> @test_vlseg6ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg6ff.nxv2i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 2 x i16> %1
}
define <vscale x 2 x i16> @test_vlseg6ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg6ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 2 x i16> %1
}
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg7ff.nxv2i16(i16* , i32)
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg7ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i16> @test_vlseg7ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg7ff.nxv2i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 2 x i16> %1
}
define <vscale x 2 x i16> @test_vlseg7ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg7ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 2 x i16> %1
}
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg8ff.nxv2i16(i16* , i32)
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg8ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i32)
define <vscale x 2 x i16> @test_vlseg8ff_nxv2i16(i16* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg8ff.nxv2i16(i16* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 2 x i16> %1
}
define <vscale x 2 x i16> @test_vlseg8ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} @llvm.riscv.vlseg8ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 2 x i16> %1
}
declare {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg2ff.nxv4i32(i32* , i32)
declare {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32)
define <vscale x 4 x i32> @test_vlseg2ff_nxv4i32(i32* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vlseg2e32ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg2ff.nxv4i32(i32* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 4 x i32> %1
}
define <vscale x 4 x i32> @test_vlseg2ff_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vlseg2e32ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg2ff.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 4 x i32> %1
}
declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg3ff.nxv4i32(i32* , i32)
declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg3ff.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32)
define <vscale x 4 x i32> @test_vlseg3ff_nxv4i32(i32* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vlseg3e32ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg3ff.nxv4i32(i32* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 4 x i32> %1
}
define <vscale x 4 x i32> @test_vlseg3ff_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vlseg3e32ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg3ff.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 4 x i32> %1
}
declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg4ff.nxv4i32(i32* , i32)
declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg4ff.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i32)
define <vscale x 4 x i32> @test_vlseg4ff_nxv4i32(i32* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vlseg4e32ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg4ff.nxv4i32(i32* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 4 x i32> %1
}
define <vscale x 4 x i32> @test_vlseg4ff_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vmv2r.v v12, v6
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vlseg4e32ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} @llvm.riscv.vlseg4ff.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 4 x i32> %1
}
declare {<vscale x 16 x half>,<vscale x 16 x half>, i32} @llvm.riscv.vlseg2ff.nxv16f16(half* , i32)
declare {<vscale x 16 x half>,<vscale x 16 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i1>, i32)
define <vscale x 16 x half> @test_vlseg2ff_nxv16f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>, i32} @llvm.riscv.vlseg2ff.nxv16f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 16 x half> %1
}
define <vscale x 16 x half> @test_vlseg2ff_mask_nxv16f16(<vscale x 16 x half> %val, half* %base, i32 %vl, <vscale x 16 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 16 x half> %1
}
declare {<vscale x 4 x double>,<vscale x 4 x double>, i32} @llvm.riscv.vlseg2ff.nxv4f64(double* , i32)
declare {<vscale x 4 x double>,<vscale x 4 x double>, i32} @llvm.riscv.vlseg2ff.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i1>, i32)
define <vscale x 4 x double> @test_vlseg2ff_nxv4f64(double* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
; CHECK-NEXT: vlseg2e64ff.v v4, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>, i32} @llvm.riscv.vlseg2ff.nxv4f64(double* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 4 x double> %1
}
define <vscale x 4 x double> @test_vlseg2ff_mask_nxv4f64(<vscale x 4 x double> %val, double* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
; CHECK-NEXT: vlseg2e64ff.v v4, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>, i32} @llvm.riscv.vlseg2ff.mask.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 4 x double> %1
}
declare {<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg2ff.nxv1f64(double* , i32)
declare {<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg2ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)
define <vscale x 1 x double> @test_vlseg2ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg2e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg2ff.nxv1f64(double* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 1 x double> %1
}
define <vscale x 1 x double> @test_vlseg2ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg2e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg2ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 1 x double> %1
}
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg3ff.nxv1f64(double* , i32)
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg3ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)
define <vscale x 1 x double> @test_vlseg3ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg3e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg3ff.nxv1f64(double* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 1 x double> %1
}
define <vscale x 1 x double> @test_vlseg3ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg3e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg3ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 1 x double> %1
}
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg4ff.nxv1f64(double* , i32)
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg4ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)
define <vscale x 1 x double> @test_vlseg4ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg4e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg4ff.nxv1f64(double* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 1 x double> %1
}
define <vscale x 1 x double> @test_vlseg4ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg4e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg4ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 1 x double> %1
}
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg5ff.nxv1f64(double* , i32)
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg5ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)
define <vscale x 1 x double> @test_vlseg5ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg5e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg5ff.nxv1f64(double* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 1 x double> %1
}
define <vscale x 1 x double> @test_vlseg5ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg5e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg5ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 1 x double> %1
}
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg6ff.nxv1f64(double* , i32)
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg6ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)
define <vscale x 1 x double> @test_vlseg6ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg6e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg6ff.nxv1f64(double* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 1 x double> %1
}
define <vscale x 1 x double> @test_vlseg6ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg6e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg6ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 1 x double> %1
}
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg7ff.nxv1f64(double* , i32)
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg7ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)
define <vscale x 1 x double> @test_vlseg7ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg7e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg7ff.nxv1f64(double* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 1 x double> %1
}
define <vscale x 1 x double> @test_vlseg7ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg7e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg7ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 1 x double> %1
}
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg8ff.nxv1f64(double* , i32)
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg8ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i32)
define <vscale x 1 x double> @test_vlseg8ff_nxv1f64(double* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg8e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg8ff.nxv1f64(double* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 1 x double> %1
}
define <vscale x 1 x double> @test_vlseg8ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg8e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} @llvm.riscv.vlseg8ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 1 x double> %1
}
declare {<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg2ff.nxv2f32(float* , i32)
declare {<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)
define <vscale x 2 x float> @test_vlseg2ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg2e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg2ff.nxv2f32(float* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 2 x float> %1
}
define <vscale x 2 x float> @test_vlseg2ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 2 x float> %1
}
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg3ff.nxv2f32(float* , i32)
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg3ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)
define <vscale x 2 x float> @test_vlseg3ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg3e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg3ff.nxv2f32(float* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 2 x float> %1
}
define <vscale x 2 x float> @test_vlseg3ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg3ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 2 x float> %1
}
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg4ff.nxv2f32(float* , i32)
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg4ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)
define <vscale x 2 x float> @test_vlseg4ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg4e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg4ff.nxv2f32(float* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 2 x float> %1
}
define <vscale x 2 x float> @test_vlseg4ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg4ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 2 x float> %1
}
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg5ff.nxv2f32(float* , i32)
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg5ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)
define <vscale x 2 x float> @test_vlseg5ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg5e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg5ff.nxv2f32(float* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 2 x float> %1
}
define <vscale x 2 x float> @test_vlseg5ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg5ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 2 x float> %1
}
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg6ff.nxv2f32(float* , i32)
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg6ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)
define <vscale x 2 x float> @test_vlseg6ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg6e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg6ff.nxv2f32(float* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 2 x float> %1
}
define <vscale x 2 x float> @test_vlseg6ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg6ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 2 x float> %1
}
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg7ff.nxv2f32(float* , i32)
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg7ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)
define <vscale x 2 x float> @test_vlseg7ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg7e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg7ff.nxv2f32(float* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 2 x float> %1
}
define <vscale x 2 x float> @test_vlseg7ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg7ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 2 x float> %1
}
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg8ff.nxv2f32(float* , i32)
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg8ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i32)
define <vscale x 2 x float> @test_vlseg8ff_nxv2f32(float* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg8e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg8ff.nxv2f32(float* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 2 x float> %1
}
define <vscale x 2 x float> @test_vlseg8ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} @llvm.riscv.vlseg8ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 2 x float> %1
}
declare {<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg2ff.nxv1f16(half* , i32)
declare {<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)
define <vscale x 1 x half> @test_vlseg2ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg2ff.nxv1f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 1 x half> %1
}
define <vscale x 1 x half> @test_vlseg2ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 1 x half> %1
}
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg3ff.nxv1f16(half* , i32)
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)
define <vscale x 1 x half> @test_vlseg3ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg3ff.nxv1f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 1 x half> %1
}
define <vscale x 1 x half> @test_vlseg3ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 1 x half> %1
}
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg4ff.nxv1f16(half* , i32)
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)
define <vscale x 1 x half> @test_vlseg4ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg4ff.nxv1f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 1 x half> %1
}
define <vscale x 1 x half> @test_vlseg4ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 1 x half> %1
}
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg5ff.nxv1f16(half* , i32)
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg5ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)
define <vscale x 1 x half> @test_vlseg5ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg5ff.nxv1f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 1 x half> %1
}
define <vscale x 1 x half> @test_vlseg5ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg5ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 1 x half> %1
}
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg6ff.nxv1f16(half* , i32)
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg6ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)
define <vscale x 1 x half> @test_vlseg6ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg6ff.nxv1f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 1 x half> %1
}
define <vscale x 1 x half> @test_vlseg6ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg6ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 1 x half> %1
}
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg7ff.nxv1f16(half* , i32)
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg7ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)
define <vscale x 1 x half> @test_vlseg7ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg7ff.nxv1f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 1 x half> %1
}
define <vscale x 1 x half> @test_vlseg7ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg7ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 1 x half> %1
}
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg8ff.nxv1f16(half* , i32)
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg8ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i32)
define <vscale x 1 x half> @test_vlseg8ff_nxv1f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg8ff.nxv1f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 1 x half> %1
}
define <vscale x 1 x half> @test_vlseg8ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} @llvm.riscv.vlseg8ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 1 x half> %1
}
declare {<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg2ff.nxv1f32(float* , i32)
declare {<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)
define <vscale x 1 x float> @test_vlseg2ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg2e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg2ff.nxv1f32(float* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 1 x float> %1
}
define <vscale x 1 x float> @test_vlseg2ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 1 x float> %1
}
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg3ff.nxv1f32(float* , i32)
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg3ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)
define <vscale x 1 x float> @test_vlseg3ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg3e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg3ff.nxv1f32(float* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 1 x float> %1
}
define <vscale x 1 x float> @test_vlseg3ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg3ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 1 x float> %1
}
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg4ff.nxv1f32(float* , i32)
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg4ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)
define <vscale x 1 x float> @test_vlseg4ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg4e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg4ff.nxv1f32(float* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 1 x float> %1
}
define <vscale x 1 x float> @test_vlseg4ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg4ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 1 x float> %1
}
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg5ff.nxv1f32(float* , i32)
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg5ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)
define <vscale x 1 x float> @test_vlseg5ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg5e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg5ff.nxv1f32(float* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 1 x float> %1
}
define <vscale x 1 x float> @test_vlseg5ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg5ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 1 x float> %1
}
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg6ff.nxv1f32(float* , i32)
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg6ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)
define <vscale x 1 x float> @test_vlseg6ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg6e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg6ff.nxv1f32(float* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 1 x float> %1
}
define <vscale x 1 x float> @test_vlseg6ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg6ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 1 x float> %1
}
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg7ff.nxv1f32(float* , i32)
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg7ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)
define <vscale x 1 x float> @test_vlseg7ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg7e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg7ff.nxv1f32(float* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 1 x float> %1
}
define <vscale x 1 x float> @test_vlseg7ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg7ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 1 x float> %1
}
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg8ff.nxv1f32(float* , i32)
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg8ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i32)
define <vscale x 1 x float> @test_vlseg8ff_nxv1f32(float* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg8e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg8ff.nxv1f32(float* %base, i32 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 1 x float> %1
}
define <vscale x 1 x float> @test_vlseg8ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i32 %vl, <vscale x 1 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} @llvm.riscv.vlseg8ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 1 x float> %1
}
declare {<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg2ff.nxv8f16(half* , i32)
declare {<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32)
define <vscale x 8 x half> @test_vlseg2ff_nxv8f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg2ff.nxv8f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 8 x half> %1
}
define <vscale x 8 x half> @test_vlseg2ff_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 8 x half> %1
}
declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg3ff.nxv8f16(half* , i32)
declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32)
define <vscale x 8 x half> @test_vlseg3ff_nxv8f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vlseg3e16ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg3ff.nxv8f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 8 x half> %1
}
define <vscale x 8 x half> @test_vlseg3ff_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vlseg3e16ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 8 x half> %1
}
declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg4ff.nxv8f16(half* , i32)
declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i32)
define <vscale x 8 x half> @test_vlseg4ff_nxv8f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vlseg4e16ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg4ff.nxv8f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 8 x half> %1
}
define <vscale x 8 x half> @test_vlseg4ff_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vmv2r.v v12, v6
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vlseg4e16ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 8 x half> %1
}
declare {<vscale x 8 x float>,<vscale x 8 x float>, i32} @llvm.riscv.vlseg2ff.nxv8f32(float* , i32)
declare {<vscale x 8 x float>,<vscale x 8 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i1>, i32)
define <vscale x 8 x float> @test_vlseg2ff_nxv8f32(float* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vlseg2e32ff.v v4, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>, i32} @llvm.riscv.vlseg2ff.nxv8f32(float* %base, i32 %vl)
%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 8 x float> %1
}
define <vscale x 8 x float> @test_vlseg2ff_mask_nxv8f32(<vscale x 8 x float> %val, float* %base, i32 %vl, <vscale x 8 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vlseg2e32ff.v v4, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 8 x float> %1
}
declare {<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg2ff.nxv2f64(double* , i32)
declare {<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg2ff.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32)
define <vscale x 2 x double> @test_vlseg2ff_nxv2f64(double* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vlseg2e64ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg2ff.nxv2f64(double* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 2 x double> %1
}
define <vscale x 2 x double> @test_vlseg2ff_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
; CHECK-NEXT: vlseg2e64ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg2ff.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 2 x double> %1
}
declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg3ff.nxv2f64(double* , i32)
declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg3ff.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32)
define <vscale x 2 x double> @test_vlseg3ff_nxv2f64(double* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vlseg3e64ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg3ff.nxv2f64(double* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 2 x double> %1
}
define <vscale x 2 x double> @test_vlseg3ff_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
; CHECK-NEXT: vlseg3e64ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg3ff.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 2 x double> %1
}
declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg4ff.nxv2f64(double* , i32)
declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg4ff.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i32)
define <vscale x 2 x double> @test_vlseg4ff_nxv2f64(double* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vlseg4e64ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg4ff.nxv2f64(double* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 2 x double> %1
}
define <vscale x 2 x double> @test_vlseg4ff_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vmv2r.v v12, v6
; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
; CHECK-NEXT: vlseg4e64ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} @llvm.riscv.vlseg4ff.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 2 x double> %1
}
declare {<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg2ff.nxv4f16(half* , i32)
declare {<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)
define <vscale x 4 x half> @test_vlseg2ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg2ff.nxv4f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 4 x half> %1
}
define <vscale x 4 x half> @test_vlseg2ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 4 x half> %1
}
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg3ff.nxv4f16(half* , i32)
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)
define <vscale x 4 x half> @test_vlseg3ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg3ff.nxv4f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 4 x half> %1
}
define <vscale x 4 x half> @test_vlseg3ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 4 x half> %1
}
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg4ff.nxv4f16(half* , i32)
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)
define <vscale x 4 x half> @test_vlseg4ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg4ff.nxv4f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 4 x half> %1
}
define <vscale x 4 x half> @test_vlseg4ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 4 x half> %1
}
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg5ff.nxv4f16(half* , i32)
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg5ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)
define <vscale x 4 x half> @test_vlseg5ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg5ff.nxv4f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 4 x half> %1
}
define <vscale x 4 x half> @test_vlseg5ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg5ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 4 x half> %1
}
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg6ff.nxv4f16(half* , i32)
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg6ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)
define <vscale x 4 x half> @test_vlseg6ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg6ff.nxv4f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 4 x half> %1
}
define <vscale x 4 x half> @test_vlseg6ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg6ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 4 x half> %1
}
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg7ff.nxv4f16(half* , i32)
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg7ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)
define <vscale x 4 x half> @test_vlseg7ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg7ff.nxv4f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 4 x half> %1
}
define <vscale x 4 x half> @test_vlseg7ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg7ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 4 x half> %1
}
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg8ff.nxv4f16(half* , i32)
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg8ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i32)
define <vscale x 4 x half> @test_vlseg8ff_nxv4f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg8ff.nxv4f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 4 x half> %1
}
define <vscale x 4 x half> @test_vlseg8ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} @llvm.riscv.vlseg8ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 4 x half> %1
}
declare {<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg2ff.nxv2f16(half* , i32)
declare {<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)
define <vscale x 2 x half> @test_vlseg2ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg2ff.nxv2f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 2 x half> %1
}
define <vscale x 2 x half> @test_vlseg2ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg2ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 2 x half> %1
}
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg3ff.nxv2f16(half* , i32)
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)
define <vscale x 2 x half> @test_vlseg3ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg3ff.nxv2f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 2 x half> %1
}
define <vscale x 2 x half> @test_vlseg3ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg3ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 2 x half> %1
}
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg4ff.nxv2f16(half* , i32)
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)
define <vscale x 2 x half> @test_vlseg4ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg4ff.nxv2f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 2 x half> %1
}
define <vscale x 2 x half> @test_vlseg4ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg4ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 2 x half> %1
}
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg5ff.nxv2f16(half* , i32)
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg5ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)
define <vscale x 2 x half> @test_vlseg5ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg5ff.nxv2f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 2 x half> %1
}
define <vscale x 2 x half> @test_vlseg5ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg5ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 5
store i32 %2, i32* %outvl
ret <vscale x 2 x half> %1
}
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg6ff.nxv2f16(half* , i32)
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg6ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)
define <vscale x 2 x half> @test_vlseg6ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg6ff.nxv2f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 2 x half> %1
}
define <vscale x 2 x half> @test_vlseg6ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg6ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 6
store i32 %2, i32* %outvl
ret <vscale x 2 x half> %1
}
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg7ff.nxv2f16(half* , i32)
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg7ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)
define <vscale x 2 x half> @test_vlseg7ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg7ff.nxv2f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 2 x half> %1
}
define <vscale x 2 x half> @test_vlseg7ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg7ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 7
store i32 %2, i32* %outvl
ret <vscale x 2 x half> %1
}
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg8ff.nxv2f16(half* , i32)
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg8ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i32)
define <vscale x 2 x half> @test_vlseg8ff_nxv2f16(half* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg8ff.nxv2f16(half* %base, i32 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 2 x half> %1
}
define <vscale x 2 x half> @test_vlseg8ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i32 %vl, <vscale x 2 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} @llvm.riscv.vlseg8ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i32} %0, 8
store i32 %2, i32* %outvl
ret <vscale x 2 x half> %1
}
declare {<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg2ff.nxv4f32(float* , i32)
declare {<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32)
define <vscale x 4 x float> @test_vlseg2ff_nxv4f32(float* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vlseg2e32ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg2ff.nxv4f32(float* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 4 x float> %1
}
define <vscale x 4 x float> @test_vlseg2ff_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vlseg2e32ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg2ff.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 2
store i32 %2, i32* %outvl
ret <vscale x 4 x float> %1
}
declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg3ff.nxv4f32(float* , i32)
declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg3ff.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32)
define <vscale x 4 x float> @test_vlseg3ff_nxv4f32(float* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vlseg3e32ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg3ff.nxv4f32(float* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 4 x float> %1
}
define <vscale x 4 x float> @test_vlseg3ff_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vlseg3e32ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg3ff.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 3
store i32 %2, i32* %outvl
ret <vscale x 4 x float> %1
}
declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg4ff.nxv4f32(float* , i32)
declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg4ff.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i32)
define <vscale x 4 x float> @test_vlseg4ff_nxv4f32(float* %base, i32 %vl, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vlseg4e32ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg4ff.nxv4f32(float* %base, i32 %vl)
%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 4 x float> %1
}
define <vscale x 4 x float> @test_vlseg4ff_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i32 %vl, <vscale x 4 x i1> %mask, i32* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vmv2r.v v12, v6
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vlseg4e32ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sw a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} @llvm.riscv.vlseg4ff.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i32 %vl)
%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 1
%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i32} %0, 4
store i32 %2, i32* %outvl
ret <vscale x 4 x float> %1
}

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \
; RUN: -verify-machineinstrs < %s | FileCheck %s
declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i64)
declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64)
define void @test_vlseg2ff_dead_value(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_dead_value:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v0, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2
store i64 %1, i64* %outvl
ret void
}
define void @test_vlseg2ff_mask_dead_value(<vscale x 16 x i16> %val, i16* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_dead_value:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v8, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2
store i64 %1, i64* %outvl
ret void
}
define <vscale x 16 x i16> @test_vlseg2ff_dead_vl(i16* %base, i64 %vl) {
; CHECK-LABEL: test_vlseg2ff_dead_vl:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
ret <vscale x 16 x i16> %1
}
define <vscale x 16 x i16> @test_vlseg2ff_mask_dead_vl(<vscale x 16 x i16> %val, i16* %base, i64 %vl, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlseg2ff_mask_dead_vl:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
ret <vscale x 16 x i16> %1
}
define void @test_vlseg2ff_dead_all(i16* %base, i64 %vl) {
; CHECK-LABEL: test_vlseg2ff_dead_all:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v0, (a0)
; CHECK-NEXT: ret
entry:
tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i64 %vl)
ret void
}
define void @test_vlseg2ff_mask_dead_all(<vscale x 16 x i16> %val, i16* %base, i64 %vl, <vscale x 16 x i1> %mask) {
; CHECK-LABEL: test_vlseg2ff_mask_dead_all:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 def $v8m4_v12m4
; CHECK-NEXT: vmv4r.v v12, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v8, (a0), v0.t
; CHECK-NEXT: ret
entry:
tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl)
ret void
}

llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll

  • This file was added.
  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zvlsseg,+experimental-zfh \
; RUN: -verify-machineinstrs < %s | FileCheck %s
declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* , i64)
declare {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16>,<vscale x 16 x i16>, i16*, <vscale x 16 x i1>, i64)
define <vscale x 16 x i16> @test_vlseg2ff_nxv16i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.nxv16i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 16 x i16> %1
}
define <vscale x 16 x i16> @test_vlseg2ff_mask_nxv16i16(<vscale x 16 x i16> %val, i16* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i16(<vscale x 16 x i16> %val,<vscale x 16 x i16> %val, i16* %base, <vscale x 16 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 16 x i16>,<vscale x 16 x i16>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 16 x i16> %1
}
declare {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg2ff.nxv4i32(i32* , i64)
declare {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64)
define <vscale x 4 x i32> @test_vlseg2ff_nxv4i32(i32* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vlseg2e32ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg2ff.nxv4i32(i32* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 4 x i32> %1
}
define <vscale x 4 x i32> @test_vlseg2ff_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vlseg2e32ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 4 x i32> %1
}
declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg3ff.nxv4i32(i32* , i64)
declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg3ff.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64)
define <vscale x 4 x i32> @test_vlseg3ff_nxv4i32(i32* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vlseg3e32ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg3ff.nxv4i32(i32* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 4 x i32> %1
}
define <vscale x 4 x i32> @test_vlseg3ff_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vlseg3e32ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg3ff.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 4 x i32> %1
}
declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg4ff.nxv4i32(i32* , i64)
declare {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg4ff.mask.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i32*, <vscale x 4 x i1>, i64)
define <vscale x 4 x i32> @test_vlseg4ff_nxv4i32(i32* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vlseg4e32ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg4ff.nxv4i32(i32* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 4 x i32> %1
}
define <vscale x 4 x i32> @test_vlseg4ff_mask_nxv4i32(<vscale x 4 x i32> %val, i32* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vmv2r.v v12, v6
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vlseg4e32ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} @llvm.riscv.vlseg4ff.mask.nxv4i32(<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val,<vscale x 4 x i32> %val, i32* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 4 x i32> %1
}
declare {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg2ff.nxv16i8(i8* , i64)
declare {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64)
define <vscale x 16 x i8> @test_vlseg2ff_nxv16i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vlseg2e8ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg2ff.nxv16i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 16 x i8> %1
}
define <vscale x 16 x i8> @test_vlseg2ff_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vlseg2e8ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 16 x i8> %1
}
declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg3ff.nxv16i8(i8* , i64)
declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64)
define <vscale x 16 x i8> @test_vlseg3ff_nxv16i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vlseg3e8ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg3ff.nxv16i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 16 x i8> %1
}
define <vscale x 16 x i8> @test_vlseg3ff_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vlseg3e8ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 16 x i8> %1
}
declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg4ff.nxv16i8(i8* , i64)
declare {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv16i8(<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i8*, <vscale x 16 x i1>, i64)
define <vscale x 16 x i8> @test_vlseg4ff_nxv16i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vlseg4e8ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg4ff.nxv16i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 16 x i8> %1
}
define <vscale x 16 x i8> @test_vlseg4ff_mask_nxv16i8(<vscale x 16 x i8> %val, i8* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vmv2r.v v12, v6
; CHECK-NEXT: vsetvli a1, a1, e8,m2,tu,mu
; CHECK-NEXT: vlseg4e8ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv16i8(<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val,<vscale x 16 x i8> %val, i8* %base, <vscale x 16 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>,<vscale x 16 x i8>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 16 x i8> %1
}
declare {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg2ff.nxv1i64(i64* , i64)
declare {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i64> @test_vlseg2ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg2e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg2ff.nxv1i64(i64* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 1 x i64> %1
}
define <vscale x 1 x i64> @test_vlseg2ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg2e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 1 x i64> %1
}
declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg3ff.nxv1i64(i64* , i64)
declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i64> @test_vlseg3ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg3e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg3ff.nxv1i64(i64* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 1 x i64> %1
}
define <vscale x 1 x i64> @test_vlseg3ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg3e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 1 x i64> %1
}
declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg4ff.nxv1i64(i64* , i64)
declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i64> @test_vlseg4ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg4e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg4ff.nxv1i64(i64* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 1 x i64> %1
}
define <vscale x 1 x i64> @test_vlseg4ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg4e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 1 x i64> %1
}
declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg5ff.nxv1i64(i64* , i64)
declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i64> @test_vlseg5ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg5e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg5ff.nxv1i64(i64* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 1 x i64> %1
}
define <vscale x 1 x i64> @test_vlseg5ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg5e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 1 x i64> %1
}
declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg6ff.nxv1i64(i64* , i64)
declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i64> @test_vlseg6ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg6e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg6ff.nxv1i64(i64* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 1 x i64> %1
}
define <vscale x 1 x i64> @test_vlseg6ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg6e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 1 x i64> %1
}
declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg7ff.nxv1i64(i64* , i64)
declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i64> @test_vlseg7ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg7e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg7ff.nxv1i64(i64* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 1 x i64> %1
}
define <vscale x 1 x i64> @test_vlseg7ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg7e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 1 x i64> %1
}
declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg8ff.nxv1i64(i64* , i64)
declare {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i64(<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i64> @test_vlseg8ff_nxv1i64(i64* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg8e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg8ff.nxv1i64(i64* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 1 x i64> %1
}
define <vscale x 1 x i64> @test_vlseg8ff_mask_nxv1i64(<vscale x 1 x i64> %val, i64* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg8e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i64(<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val,<vscale x 1 x i64> %val, i64* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>,<vscale x 1 x i64>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 1 x i64> %1
}
declare {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg2ff.nxv1i32(i32* , i64)
declare {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i32> @test_vlseg2ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg2e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg2ff.nxv1i32(i32* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 1 x i32> %1
}
define <vscale x 1 x i32> @test_vlseg2ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 1 x i32> %1
}
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg3ff.nxv1i32(i32* , i64)
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i32> @test_vlseg3ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg3e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg3ff.nxv1i32(i32* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 1 x i32> %1
}
define <vscale x 1 x i32> @test_vlseg3ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 1 x i32> %1
}
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg4ff.nxv1i32(i32* , i64)
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i32> @test_vlseg4ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg4e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg4ff.nxv1i32(i32* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 1 x i32> %1
}
define <vscale x 1 x i32> @test_vlseg4ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 1 x i32> %1
}
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg5ff.nxv1i32(i32* , i64)
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i32> @test_vlseg5ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg5e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg5ff.nxv1i32(i32* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 1 x i32> %1
}
define <vscale x 1 x i32> @test_vlseg5ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 1 x i32> %1
}
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg6ff.nxv1i32(i32* , i64)
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i32> @test_vlseg6ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg6e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg6ff.nxv1i32(i32* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 1 x i32> %1
}
define <vscale x 1 x i32> @test_vlseg6ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 1 x i32> %1
}
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg7ff.nxv1i32(i32* , i64)
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i32> @test_vlseg7ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg7e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg7ff.nxv1i32(i32* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 1 x i32> %1
}
define <vscale x 1 x i32> @test_vlseg7ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 1 x i32> %1
}
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg8ff.nxv1i32(i32* , i64)
declare {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i32(<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i32*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i32> @test_vlseg8ff_nxv1i32(i32* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg8e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg8ff.nxv1i32(i32* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 1 x i32> %1
}
define <vscale x 1 x i32> @test_vlseg8ff_mask_nxv1i32(<vscale x 1 x i32> %val, i32* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i32(<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val,<vscale x 1 x i32> %val, i32* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>,<vscale x 1 x i32>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 1 x i32> %1
}
declare {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg2ff.nxv8i16(i16* , i64)
declare {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64)
define <vscale x 8 x i16> @test_vlseg2ff_nxv8i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg2ff.nxv8i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 8 x i16> %1
}
define <vscale x 8 x i16> @test_vlseg2ff_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 8 x i16> %1
}
declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg3ff.nxv8i16(i16* , i64)
declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64)
define <vscale x 8 x i16> @test_vlseg3ff_nxv8i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vlseg3e16ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg3ff.nxv8i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 8 x i16> %1
}
define <vscale x 8 x i16> @test_vlseg3ff_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vlseg3e16ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 8 x i16> %1
}
declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg4ff.nxv8i16(i16* , i64)
declare {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv8i16(<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i16*, <vscale x 8 x i1>, i64)
define <vscale x 8 x i16> @test_vlseg4ff_nxv8i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vlseg4e16ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg4ff.nxv8i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 8 x i16> %1
}
define <vscale x 8 x i16> @test_vlseg4ff_mask_nxv8i16(<vscale x 8 x i16> %val, i16* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vmv2r.v v12, v6
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vlseg4e16ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv8i16(<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val,<vscale x 8 x i16> %val, i16* %base, <vscale x 8 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>,<vscale x 8 x i16>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 8 x i16> %1
}
declare {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg2ff.nxv4i8(i8* , i64)
declare {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)
define <vscale x 4 x i8> @test_vlseg2ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vlseg2e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg2ff.nxv4i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 4 x i8> %1
}
define <vscale x 4 x i8> @test_vlseg2ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 4 x i8> %1
}
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg3ff.nxv4i8(i8* , i64)
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)
define <vscale x 4 x i8> @test_vlseg3ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vlseg3e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg3ff.nxv4i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 4 x i8> %1
}
define <vscale x 4 x i8> @test_vlseg3ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 4 x i8> %1
}
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg4ff.nxv4i8(i8* , i64)
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)
define <vscale x 4 x i8> @test_vlseg4ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vlseg4e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg4ff.nxv4i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 4 x i8> %1
}
define <vscale x 4 x i8> @test_vlseg4ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 4 x i8> %1
}
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg5ff.nxv4i8(i8* , i64)
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)
define <vscale x 4 x i8> @test_vlseg5ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vlseg5e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg5ff.nxv4i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 4 x i8> %1
}
define <vscale x 4 x i8> @test_vlseg5ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 4 x i8> %1
}
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg6ff.nxv4i8(i8* , i64)
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)
define <vscale x 4 x i8> @test_vlseg6ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vlseg6e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg6ff.nxv4i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 4 x i8> %1
}
define <vscale x 4 x i8> @test_vlseg6ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 4 x i8> %1
}
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg7ff.nxv4i8(i8* , i64)
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)
define <vscale x 4 x i8> @test_vlseg7ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vlseg7e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg7ff.nxv4i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 4 x i8> %1
}
define <vscale x 4 x i8> @test_vlseg7ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 4 x i8> %1
}
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg8ff.nxv4i8(i8* , i64)
declare {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv4i8(<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i8*, <vscale x 4 x i1>, i64)
define <vscale x 4 x i8> @test_vlseg8ff_nxv4i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vlseg8e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg8ff.nxv4i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 4 x i8> %1
}
define <vscale x 4 x i8> @test_vlseg8ff_mask_nxv4i8(<vscale x 4 x i8> %val, i8* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,tu,mu
; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv4i8(<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val,<vscale x 4 x i8> %val, i8* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>,<vscale x 4 x i8>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 4 x i8> %1
}
declare {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg2ff.nxv1i16(i16* , i64)
declare {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i16> @test_vlseg2ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg2ff.nxv1i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 1 x i16> %1
}
define <vscale x 1 x i16> @test_vlseg2ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 1 x i16> %1
}
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg3ff.nxv1i16(i16* , i64)
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i16> @test_vlseg3ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg3ff.nxv1i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 1 x i16> %1
}
define <vscale x 1 x i16> @test_vlseg3ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 1 x i16> %1
}
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg4ff.nxv1i16(i16* , i64)
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i16> @test_vlseg4ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg4ff.nxv1i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 1 x i16> %1
}
define <vscale x 1 x i16> @test_vlseg4ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 1 x i16> %1
}
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg5ff.nxv1i16(i16* , i64)
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i16> @test_vlseg5ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg5ff.nxv1i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 1 x i16> %1
}
define <vscale x 1 x i16> @test_vlseg5ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 1 x i16> %1
}
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg6ff.nxv1i16(i16* , i64)
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i16> @test_vlseg6ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg6ff.nxv1i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 1 x i16> %1
}
define <vscale x 1 x i16> @test_vlseg6ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 1 x i16> %1
}
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg7ff.nxv1i16(i16* , i64)
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i16> @test_vlseg7ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg7ff.nxv1i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 1 x i16> %1
}
define <vscale x 1 x i16> @test_vlseg7ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 1 x i16> %1
}
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg8ff.nxv1i16(i16* , i64)
declare {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i16(<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i16*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i16> @test_vlseg8ff_nxv1i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg8ff.nxv1i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 1 x i16> %1
}
define <vscale x 1 x i16> @test_vlseg8ff_mask_nxv1i16(<vscale x 1 x i16> %val, i16* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i16(<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val,<vscale x 1 x i16> %val, i16* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>,<vscale x 1 x i16>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 1 x i16> %1
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg2ff.nxv2i32(i32* , i64)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i32> @test_vlseg2ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg2e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg2ff.nxv2i32(i32* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlseg2ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 2 x i32> %1
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg3ff.nxv2i32(i32* , i64)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i32> @test_vlseg3ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg3e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg3ff.nxv2i32(i32* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlseg3ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 2 x i32> %1
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg4ff.nxv2i32(i32* , i64)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i32> @test_vlseg4ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg4e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg4ff.nxv2i32(i32* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlseg4ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 2 x i32> %1
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg5ff.nxv2i32(i32* , i64)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg5ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i32> @test_vlseg5ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg5e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg5ff.nxv2i32(i32* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlseg5ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg5ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 2 x i32> %1
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg6ff.nxv2i32(i32* , i64)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg6ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i32> @test_vlseg6ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg6e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg6ff.nxv2i32(i32* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlseg6ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg6ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 2 x i32> %1
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg7ff.nxv2i32(i32* , i64)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg7ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i32> @test_vlseg7ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg7e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg7ff.nxv2i32(i32* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlseg7ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg7ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 2 x i32> %1
}
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg8ff.nxv2i32(i32* , i64)
declare {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg8ff.mask.nxv2i32(<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i32*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i32> @test_vlseg8ff_nxv2i32(i32* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg8e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg8ff.nxv2i32(i32* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 2 x i32> %1
}
define <vscale x 2 x i32> @test_vlseg8ff_mask_nxv2i32(<vscale x 2 x i32> %val, i32* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} @llvm.riscv.vlseg8ff.mask.nxv2i32(<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val,<vscale x 2 x i32> %val, i32* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>,<vscale x 2 x i32>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 2 x i32> %1
}
declare {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg2ff.nxv8i8(i8* , i64)
declare {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)
define <vscale x 8 x i8> @test_vlseg2ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vlseg2e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg2ff.nxv8i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 8 x i8> %1
}
define <vscale x 8 x i8> @test_vlseg2ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 8 x i8> %1
}
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg3ff.nxv8i8(i8* , i64)
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)
define <vscale x 8 x i8> @test_vlseg3ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vlseg3e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg3ff.nxv8i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 8 x i8> %1
}
define <vscale x 8 x i8> @test_vlseg3ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 8 x i8> %1
}
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg4ff.nxv8i8(i8* , i64)
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)
define <vscale x 8 x i8> @test_vlseg4ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vlseg4e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg4ff.nxv8i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 8 x i8> %1
}
define <vscale x 8 x i8> @test_vlseg4ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 8 x i8> %1
}
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg5ff.nxv8i8(i8* , i64)
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)
define <vscale x 8 x i8> @test_vlseg5ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vlseg5e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg5ff.nxv8i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 8 x i8> %1
}
define <vscale x 8 x i8> @test_vlseg5ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 8 x i8> %1
}
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg6ff.nxv8i8(i8* , i64)
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)
define <vscale x 8 x i8> @test_vlseg6ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vlseg6e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg6ff.nxv8i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 8 x i8> %1
}
define <vscale x 8 x i8> @test_vlseg6ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 8 x i8> %1
}
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg7ff.nxv8i8(i8* , i64)
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)
define <vscale x 8 x i8> @test_vlseg7ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vlseg7e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg7ff.nxv8i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 8 x i8> %1
}
define <vscale x 8 x i8> @test_vlseg7ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 8 x i8> %1
}
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg8ff.nxv8i8(i8* , i64)
declare {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv8i8(<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i8*, <vscale x 8 x i1>, i64)
define <vscale x 8 x i8> @test_vlseg8ff_nxv8i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vlseg8e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg8ff.nxv8i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 8 x i8> %1
}
define <vscale x 8 x i8> @test_vlseg8ff_mask_nxv8i8(<vscale x 8 x i8> %val, i8* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e8,m1,tu,mu
; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv8i8(<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val,<vscale x 8 x i8> %val, i8* %base, <vscale x 8 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>,<vscale x 8 x i8>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 8 x i8> %1
}
declare {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} @llvm.riscv.vlseg2ff.nxv4i64(i64* , i64)
declare {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i64(<vscale x 4 x i64>,<vscale x 4 x i64>, i64*, <vscale x 4 x i1>, i64)
define <vscale x 4 x i64> @test_vlseg2ff_nxv4i64(i64* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
; CHECK-NEXT: vlseg2e64ff.v v4, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} @llvm.riscv.vlseg2ff.nxv4i64(i64* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 4 x i64> %1
}
define <vscale x 4 x i64> @test_vlseg2ff_mask_nxv4i64(<vscale x 4 x i64> %val, i64* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv4i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
; CHECK-NEXT: vlseg2e64ff.v v4, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i64(<vscale x 4 x i64> %val,<vscale x 4 x i64> %val, i64* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i64>,<vscale x 4 x i64>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 4 x i64> %1
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg2ff.nxv4i16(i16* , i64)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)
define <vscale x 4 x i16> @test_vlseg2ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg2ff.nxv4i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlseg2ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 4 x i16> %1
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg3ff.nxv4i16(i16* , i64)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)
define <vscale x 4 x i16> @test_vlseg3ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg3ff.nxv4i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlseg3ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 4 x i16> %1
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg4ff.nxv4i16(i16* , i64)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)
define <vscale x 4 x i16> @test_vlseg4ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg4ff.nxv4i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlseg4ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 4 x i16> %1
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg5ff.nxv4i16(i16* , i64)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg5ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)
define <vscale x 4 x i16> @test_vlseg5ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg5ff.nxv4i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlseg5ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg5ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 4 x i16> %1
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg6ff.nxv4i16(i16* , i64)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg6ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)
define <vscale x 4 x i16> @test_vlseg6ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg6ff.nxv4i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlseg6ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg6ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 4 x i16> %1
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg7ff.nxv4i16(i16* , i64)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg7ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)
define <vscale x 4 x i16> @test_vlseg7ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg7ff.nxv4i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlseg7ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg7ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 4 x i16> %1
}
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg8ff.nxv4i16(i16* , i64)
declare {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg8ff.mask.nxv4i16(<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i16*, <vscale x 4 x i1>, i64)
define <vscale x 4 x i16> @test_vlseg8ff_nxv4i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg8ff.nxv4i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 4 x i16> %1
}
define <vscale x 4 x i16> @test_vlseg8ff_mask_nxv4i16(<vscale x 4 x i16> %val, i16* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} @llvm.riscv.vlseg8ff.mask.nxv4i16(<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val,<vscale x 4 x i16> %val, i16* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>,<vscale x 4 x i16>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 4 x i16> %1
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg2ff.nxv1i8(i8* , i64)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i8> @test_vlseg2ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vlseg2e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg2ff.nxv1i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlseg2ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 1 x i8> %1
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg3ff.nxv1i8(i8* , i64)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i8> @test_vlseg3ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vlseg3e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg3ff.nxv1i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlseg3ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 1 x i8> %1
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg4ff.nxv1i8(i8* , i64)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i8> @test_vlseg4ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vlseg4e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg4ff.nxv1i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlseg4ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 1 x i8> %1
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg5ff.nxv1i8(i8* , i64)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i8> @test_vlseg5ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vlseg5e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg5ff.nxv1i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlseg5ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 1 x i8> %1
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg6ff.nxv1i8(i8* , i64)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i8> @test_vlseg6ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vlseg6e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg6ff.nxv1i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlseg6ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 1 x i8> %1
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg7ff.nxv1i8(i8* , i64)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i8> @test_vlseg7ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vlseg7e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg7ff.nxv1i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlseg7ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 1 x i8> %1
}
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg8ff.nxv1i8(i8* , i64)
declare {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i8(<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i8*, <vscale x 1 x i1>, i64)
define <vscale x 1 x i8> @test_vlseg8ff_nxv1i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vlseg8e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg8ff.nxv1i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 1 x i8> %1
}
define <vscale x 1 x i8> @test_vlseg8ff_mask_nxv1i8(<vscale x 1 x i8> %val, i8* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,tu,mu
; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv1i8(<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val,<vscale x 1 x i8> %val, i8* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>,<vscale x 1 x i8>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 1 x i8> %1
}
declare {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg2ff.nxv2i8(i8* , i64)
declare {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i8> @test_vlseg2ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vlseg2e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg2ff.nxv2i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 2 x i8> %1
}
define <vscale x 2 x i8> @test_vlseg2ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vlseg2e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 2 x i8> %1
}
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg3ff.nxv2i8(i8* , i64)
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i8> @test_vlseg3ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vlseg3e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg3ff.nxv2i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 2 x i8> %1
}
define <vscale x 2 x i8> @test_vlseg3ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vlseg3e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 2 x i8> %1
}
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg4ff.nxv2i8(i8* , i64)
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i8> @test_vlseg4ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vlseg4e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg4ff.nxv2i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 2 x i8> %1
}
define <vscale x 2 x i8> @test_vlseg4ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vlseg4e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 2 x i8> %1
}
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg5ff.nxv2i8(i8* , i64)
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i8> @test_vlseg5ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vlseg5e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg5ff.nxv2i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 2 x i8> %1
}
define <vscale x 2 x i8> @test_vlseg5ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vlseg5e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg5ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 2 x i8> %1
}
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg6ff.nxv2i8(i8* , i64)
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i8> @test_vlseg6ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vlseg6e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg6ff.nxv2i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 2 x i8> %1
}
define <vscale x 2 x i8> @test_vlseg6ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vlseg6e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg6ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 2 x i8> %1
}
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg7ff.nxv2i8(i8* , i64)
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i8> @test_vlseg7ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vlseg7e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg7ff.nxv2i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 2 x i8> %1
}
define <vscale x 2 x i8> @test_vlseg7ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vlseg7e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg7ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 2 x i8> %1
}
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg8ff.nxv2i8(i8* , i64)
declare {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv2i8(<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i8*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i8> @test_vlseg8ff_nxv2i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vlseg8e8ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg8ff.nxv2i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 2 x i8> %1
}
define <vscale x 2 x i8> @test_vlseg8ff_mask_nxv2i8(<vscale x 2 x i8> %val, i8* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,tu,mu
; CHECK-NEXT: vlseg8e8ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} @llvm.riscv.vlseg8ff.mask.nxv2i8(<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val,<vscale x 2 x i8> %val, i8* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>,<vscale x 2 x i8>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 2 x i8> %1
}
declare {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} @llvm.riscv.vlseg2ff.nxv8i32(i32* , i64)
declare {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i32(<vscale x 8 x i32>,<vscale x 8 x i32>, i32*, <vscale x 8 x i1>, i64)
define <vscale x 8 x i32> @test_vlseg2ff_nxv8i32(i32* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vlseg2e32ff.v v4, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} @llvm.riscv.vlseg2ff.nxv8i32(i32* %base, i64 %vl)
%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 8 x i32> %1
}
define <vscale x 8 x i32> @test_vlseg2ff_mask_nxv8i32(<vscale x 8 x i32> %val, i32* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vlseg2e32ff.v v4, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} @llvm.riscv.vlseg2ff.mask.nxv8i32(<vscale x 8 x i32> %val,<vscale x 8 x i32> %val, i32* %base, <vscale x 8 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x i32>,<vscale x 8 x i32>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 8 x i32> %1
}
declare {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} @llvm.riscv.vlseg2ff.nxv32i8(i8* , i64)
declare {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv32i8(<vscale x 32 x i8>,<vscale x 32 x i8>, i8*, <vscale x 32 x i1>, i64)
define <vscale x 32 x i8> @test_vlseg2ff_nxv32i8(i8* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vlseg2e8ff.v v4, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} @llvm.riscv.vlseg2ff.nxv32i8(i8* %base, i64 %vl)
%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 32 x i8> %1
}
define <vscale x 32 x i8> @test_vlseg2ff_mask_nxv32i8(<vscale x 32 x i8> %val, i8* %base, i64 %vl, <vscale x 32 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli a1, a1, e8,m4,tu,mu
; CHECK-NEXT: vlseg2e8ff.v v4, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} @llvm.riscv.vlseg2ff.mask.nxv32i8(<vscale x 32 x i8> %val,<vscale x 32 x i8> %val, i8* %base, <vscale x 32 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} %0, 1
%2 = extractvalue {<vscale x 32 x i8>,<vscale x 32 x i8>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 32 x i8> %1
}
declare {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg2ff.nxv2i16(i16* , i64)
declare {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i16> @test_vlseg2ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg2ff.nxv2i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 2 x i16> %1
}
define <vscale x 2 x i16> @test_vlseg2ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 2 x i16> %1
}
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg3ff.nxv2i16(i16* , i64)
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i16> @test_vlseg3ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg3ff.nxv2i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 2 x i16> %1
}
define <vscale x 2 x i16> @test_vlseg3ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 2 x i16> %1
}
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg4ff.nxv2i16(i16* , i64)
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i16> @test_vlseg4ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg4ff.nxv2i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 2 x i16> %1
}
define <vscale x 2 x i16> @test_vlseg4ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 2 x i16> %1
}
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg5ff.nxv2i16(i16* , i64)
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg5ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i16> @test_vlseg5ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg5ff.nxv2i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 2 x i16> %1
}
define <vscale x 2 x i16> @test_vlseg5ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg5ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 2 x i16> %1
}
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg6ff.nxv2i16(i16* , i64)
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg6ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i16> @test_vlseg6ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg6ff.nxv2i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 2 x i16> %1
}
define <vscale x 2 x i16> @test_vlseg6ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg6ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 2 x i16> %1
}
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg7ff.nxv2i16(i16* , i64)
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg7ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i16> @test_vlseg7ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg7ff.nxv2i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 2 x i16> %1
}
define <vscale x 2 x i16> @test_vlseg7ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg7ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 2 x i16> %1
}
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg8ff.nxv2i16(i16* , i64)
declare {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg8ff.mask.nxv2i16(<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i16*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i16> @test_vlseg8ff_nxv2i16(i16* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg8ff.nxv2i16(i16* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 2 x i16> %1
}
define <vscale x 2 x i16> @test_vlseg8ff_mask_nxv2i16(<vscale x 2 x i16> %val, i16* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} @llvm.riscv.vlseg8ff.mask.nxv2i16(<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val,<vscale x 2 x i16> %val, i16* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>,<vscale x 2 x i16>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 2 x i16> %1
}
declare {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg2ff.nxv2i64(i64* , i64)
declare {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i64> @test_vlseg2ff_nxv2i64(i64* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vlseg2e64ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg2ff.nxv2i64(i64* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 2 x i64> %1
}
define <vscale x 2 x i64> @test_vlseg2ff_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
; CHECK-NEXT: vlseg2e64ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg2ff.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 2 x i64> %1
}
declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg3ff.nxv2i64(i64* , i64)
declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i64> @test_vlseg3ff_nxv2i64(i64* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vlseg3e64ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg3ff.nxv2i64(i64* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 2 x i64> %1
}
define <vscale x 2 x i64> @test_vlseg3ff_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
; CHECK-NEXT: vlseg3e64ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg3ff.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 2 x i64> %1
}
declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg4ff.nxv2i64(i64* , i64)
declare {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64*, <vscale x 2 x i1>, i64)
define <vscale x 2 x i64> @test_vlseg4ff_nxv2i64(i64* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vlseg4e64ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg4ff.nxv2i64(i64* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 2 x i64> %1
}
define <vscale x 2 x i64> @test_vlseg4ff_mask_nxv2i64(<vscale x 2 x i64> %val, i64* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv2i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vmv2r.v v12, v6
; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
; CHECK-NEXT: vlseg4e64ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} @llvm.riscv.vlseg4ff.mask.nxv2i64(<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val,<vscale x 2 x i64> %val, i64* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 2 x i64> %1
}
declare {<vscale x 16 x half>,<vscale x 16 x half>, i64} @llvm.riscv.vlseg2ff.nxv16f16(half* , i64)
declare {<vscale x 16 x half>,<vscale x 16 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv16f16(<vscale x 16 x half>,<vscale x 16 x half>, half*, <vscale x 16 x i1>, i64)
define <vscale x 16 x half> @test_vlseg2ff_nxv16f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>, i64} @llvm.riscv.vlseg2ff.nxv16f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 16 x half> %1
}
define <vscale x 16 x half> @test_vlseg2ff_mask_nxv16f16(<vscale x 16 x half> %val, half* %base, i64 %vl, <vscale x 16 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v4, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 16 x half>,<vscale x 16 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv16f16(<vscale x 16 x half> %val,<vscale x 16 x half> %val, half* %base, <vscale x 16 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 16 x half>,<vscale x 16 x half>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 16 x half> %1
}
declare {<vscale x 4 x double>,<vscale x 4 x double>, i64} @llvm.riscv.vlseg2ff.nxv4f64(double* , i64)
declare {<vscale x 4 x double>,<vscale x 4 x double>, i64} @llvm.riscv.vlseg2ff.mask.nxv4f64(<vscale x 4 x double>,<vscale x 4 x double>, double*, <vscale x 4 x i1>, i64)
define <vscale x 4 x double> @test_vlseg2ff_nxv4f64(double* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m4,ta,mu
; CHECK-NEXT: vlseg2e64ff.v v4, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>, i64} @llvm.riscv.vlseg2ff.nxv4f64(double* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 4 x double> %1
}
define <vscale x 4 x double> @test_vlseg2ff_mask_nxv4f64(<vscale x 4 x double> %val, double* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli a1, a1, e64,m4,tu,mu
; CHECK-NEXT: vlseg2e64ff.v v4, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x double>,<vscale x 4 x double>, i64} @llvm.riscv.vlseg2ff.mask.nxv4f64(<vscale x 4 x double> %val,<vscale x 4 x double> %val, double* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x double>,<vscale x 4 x double>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 4 x double> %1
}
declare {<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg2ff.nxv1f64(double* , i64)
declare {<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg2ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)
define <vscale x 1 x double> @test_vlseg2ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg2e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg2ff.nxv1f64(double* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 1 x double> %1
}
define <vscale x 1 x double> @test_vlseg2ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg2e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg2ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 1 x double> %1
}
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg3ff.nxv1f64(double* , i64)
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg3ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)
define <vscale x 1 x double> @test_vlseg3ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg3e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg3ff.nxv1f64(double* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 1 x double> %1
}
define <vscale x 1 x double> @test_vlseg3ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg3e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg3ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 1 x double> %1
}
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg4ff.nxv1f64(double* , i64)
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg4ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)
define <vscale x 1 x double> @test_vlseg4ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg4e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg4ff.nxv1f64(double* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 1 x double> %1
}
define <vscale x 1 x double> @test_vlseg4ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg4e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg4ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 1 x double> %1
}
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg5ff.nxv1f64(double* , i64)
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg5ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)
define <vscale x 1 x double> @test_vlseg5ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg5e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg5ff.nxv1f64(double* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 1 x double> %1
}
define <vscale x 1 x double> @test_vlseg5ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg5e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg5ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 1 x double> %1
}
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg6ff.nxv1f64(double* , i64)
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg6ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)
define <vscale x 1 x double> @test_vlseg6ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg6e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg6ff.nxv1f64(double* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 1 x double> %1
}
define <vscale x 1 x double> @test_vlseg6ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg6e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg6ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 1 x double> %1
}
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg7ff.nxv1f64(double* , i64)
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg7ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)
define <vscale x 1 x double> @test_vlseg7ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg7e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg7ff.nxv1f64(double* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 1 x double> %1
}
define <vscale x 1 x double> @test_vlseg7ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg7e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg7ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 1 x double> %1
}
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg8ff.nxv1f64(double* , i64)
declare {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg8ff.mask.nxv1f64(<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, double*, <vscale x 1 x i1>, i64)
define <vscale x 1 x double> @test_vlseg8ff_nxv1f64(double* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m1,ta,mu
; CHECK-NEXT: vlseg8e64ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg8ff.nxv1f64(double* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 1 x double> %1
}
define <vscale x 1 x double> @test_vlseg8ff_mask_nxv1f64(<vscale x 1 x double> %val, double* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e64,m1,tu,mu
; CHECK-NEXT: vlseg8e64ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} @llvm.riscv.vlseg8ff.mask.nxv1f64(<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val,<vscale x 1 x double> %val, double* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>,<vscale x 1 x double>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 1 x double> %1
}
declare {<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg2ff.nxv2f32(float* , i64)
declare {<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)
define <vscale x 2 x float> @test_vlseg2ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg2e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg2ff.nxv2f32(float* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 2 x float> %1
}
define <vscale x 2 x float> @test_vlseg2ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 2 x float> %1
}
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg3ff.nxv2f32(float* , i64)
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg3ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)
define <vscale x 2 x float> @test_vlseg3ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg3e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg3ff.nxv2f32(float* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 2 x float> %1
}
define <vscale x 2 x float> @test_vlseg3ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg3ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 2 x float> %1
}
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg4ff.nxv2f32(float* , i64)
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg4ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)
define <vscale x 2 x float> @test_vlseg4ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg4e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg4ff.nxv2f32(float* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 2 x float> %1
}
define <vscale x 2 x float> @test_vlseg4ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg4ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 2 x float> %1
}
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg5ff.nxv2f32(float* , i64)
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg5ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)
define <vscale x 2 x float> @test_vlseg5ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg5e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg5ff.nxv2f32(float* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 2 x float> %1
}
define <vscale x 2 x float> @test_vlseg5ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg5ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 2 x float> %1
}
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg6ff.nxv2f32(float* , i64)
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg6ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)
define <vscale x 2 x float> @test_vlseg6ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg6e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg6ff.nxv2f32(float* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 2 x float> %1
}
define <vscale x 2 x float> @test_vlseg6ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg6ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 2 x float> %1
}
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg7ff.nxv2f32(float* , i64)
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg7ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)
define <vscale x 2 x float> @test_vlseg7ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg7e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg7ff.nxv2f32(float* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 2 x float> %1
}
define <vscale x 2 x float> @test_vlseg7ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg7ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 2 x float> %1
}
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg8ff.nxv2f32(float* , i64)
declare {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg8ff.mask.nxv2f32(<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, float*, <vscale x 2 x i1>, i64)
define <vscale x 2 x float> @test_vlseg8ff_nxv2f32(float* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vlseg8e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg8ff.nxv2f32(float* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 2 x float> %1
}
define <vscale x 2 x float> @test_vlseg8ff_mask_nxv2f32(<vscale x 2 x float> %val, float* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e32,m1,tu,mu
; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} @llvm.riscv.vlseg8ff.mask.nxv2f32(<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val,<vscale x 2 x float> %val, float* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>,<vscale x 2 x float>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 2 x float> %1
}
declare {<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg2ff.nxv1f16(half* , i64)
declare {<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)
define <vscale x 1 x half> @test_vlseg2ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg2ff.nxv1f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 1 x half> %1
}
define <vscale x 1 x half> @test_vlseg2ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 1 x half> %1
}
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg3ff.nxv1f16(half* , i64)
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)
define <vscale x 1 x half> @test_vlseg3ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg3ff.nxv1f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 1 x half> %1
}
define <vscale x 1 x half> @test_vlseg3ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 1 x half> %1
}
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg4ff.nxv1f16(half* , i64)
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)
define <vscale x 1 x half> @test_vlseg4ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg4ff.nxv1f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 1 x half> %1
}
define <vscale x 1 x half> @test_vlseg4ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 1 x half> %1
}
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg5ff.nxv1f16(half* , i64)
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg5ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)
define <vscale x 1 x half> @test_vlseg5ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg5ff.nxv1f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 1 x half> %1
}
define <vscale x 1 x half> @test_vlseg5ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg5ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 1 x half> %1
}
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg6ff.nxv1f16(half* , i64)
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg6ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)
define <vscale x 1 x half> @test_vlseg6ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg6ff.nxv1f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 1 x half> %1
}
define <vscale x 1 x half> @test_vlseg6ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg6ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 1 x half> %1
}
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg7ff.nxv1f16(half* , i64)
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg7ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)
define <vscale x 1 x half> @test_vlseg7ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg7ff.nxv1f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 1 x half> %1
}
define <vscale x 1 x half> @test_vlseg7ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg7ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 1 x half> %1
}
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg8ff.nxv1f16(half* , i64)
declare {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg8ff.mask.nxv1f16(<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, half*, <vscale x 1 x i1>, i64)
define <vscale x 1 x half> @test_vlseg8ff_nxv1f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg8ff.nxv1f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 1 x half> %1
}
define <vscale x 1 x half> @test_vlseg8ff_mask_nxv1f16(<vscale x 1 x half> %val, half* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,tu,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} @llvm.riscv.vlseg8ff.mask.nxv1f16(<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val,<vscale x 1 x half> %val, half* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>,<vscale x 1 x half>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 1 x half> %1
}
declare {<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg2ff.nxv1f32(float* , i64)
declare {<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)
define <vscale x 1 x float> @test_vlseg2ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg2e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg2ff.nxv1f32(float* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 1 x float> %1
}
define <vscale x 1 x float> @test_vlseg2ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg2e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 1 x float> %1
}
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg3ff.nxv1f32(float* , i64)
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg3ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)
define <vscale x 1 x float> @test_vlseg3ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg3e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg3ff.nxv1f32(float* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 1 x float> %1
}
define <vscale x 1 x float> @test_vlseg3ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg3e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg3ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 1 x float> %1
}
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg4ff.nxv1f32(float* , i64)
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg4ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)
define <vscale x 1 x float> @test_vlseg4ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg4e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg4ff.nxv1f32(float* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 1 x float> %1
}
define <vscale x 1 x float> @test_vlseg4ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg4e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg4ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 1 x float> %1
}
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg5ff.nxv1f32(float* , i64)
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg5ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)
define <vscale x 1 x float> @test_vlseg5ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg5e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg5ff.nxv1f32(float* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 1 x float> %1
}
define <vscale x 1 x float> @test_vlseg5ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg5e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg5ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 1 x float> %1
}
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg6ff.nxv1f32(float* , i64)
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg6ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)
define <vscale x 1 x float> @test_vlseg6ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg6e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg6ff.nxv1f32(float* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 1 x float> %1
}
define <vscale x 1 x float> @test_vlseg6ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg6e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg6ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 1 x float> %1
}
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg7ff.nxv1f32(float* , i64)
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg7ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)
define <vscale x 1 x float> @test_vlseg7ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg7e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg7ff.nxv1f32(float* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 1 x float> %1
}
define <vscale x 1 x float> @test_vlseg7ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg7e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg7ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 1 x float> %1
}
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg8ff.nxv1f32(float* , i64)
declare {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg8ff.mask.nxv1f32(<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, float*, <vscale x 1 x i1>, i64)
define <vscale x 1 x float> @test_vlseg8ff_nxv1f32(float* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vlseg8e32ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg8ff.nxv1f32(float* %base, i64 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 1 x float> %1
}
define <vscale x 1 x float> @test_vlseg8ff_mask_nxv1f32(<vscale x 1 x float> %val, float* %base, i64 %vl, <vscale x 1 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,tu,mu
; CHECK-NEXT: vlseg8e32ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} @llvm.riscv.vlseg8ff.mask.nxv1f32(<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val,<vscale x 1 x float> %val, float* %base, <vscale x 1 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>,<vscale x 1 x float>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 1 x float> %1
}
declare {<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg2ff.nxv8f16(half* , i64)
declare {<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64)
define <vscale x 8 x half> @test_vlseg2ff_nxv8f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg2ff.nxv8f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 8 x half> %1
}
define <vscale x 8 x half> @test_vlseg2ff_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 8 x half> %1
}
declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg3ff.nxv8f16(half* , i64)
declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64)
define <vscale x 8 x half> @test_vlseg3ff_nxv8f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vlseg3e16ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg3ff.nxv8f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 8 x half> %1
}
define <vscale x 8 x half> @test_vlseg3ff_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vlseg3e16ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 8 x half> %1
}
declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg4ff.nxv8f16(half* , i64)
declare {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv8f16(<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, half*, <vscale x 8 x i1>, i64)
define <vscale x 8 x half> @test_vlseg4ff_nxv8f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vlseg4e16ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg4ff.nxv8f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 8 x half> %1
}
define <vscale x 8 x half> @test_vlseg4ff_mask_nxv8f16(<vscale x 8 x half> %val, half* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vmv2r.v v12, v6
; CHECK-NEXT: vsetvli a1, a1, e16,m2,tu,mu
; CHECK-NEXT: vlseg4e16ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv8f16(<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val,<vscale x 8 x half> %val, half* %base, <vscale x 8 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>,<vscale x 8 x half>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 8 x half> %1
}
declare {<vscale x 8 x float>,<vscale x 8 x float>, i64} @llvm.riscv.vlseg2ff.nxv8f32(float* , i64)
declare {<vscale x 8 x float>,<vscale x 8 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv8f32(<vscale x 8 x float>,<vscale x 8 x float>, float*, <vscale x 8 x i1>, i64)
define <vscale x 8 x float> @test_vlseg2ff_nxv8f32(float* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vlseg2e32ff.v v4, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>, i64} @llvm.riscv.vlseg2ff.nxv8f32(float* %base, i64 %vl)
%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 8 x float> %1
}
define <vscale x 8 x float> @test_vlseg2ff_mask_nxv8f32(<vscale x 8 x float> %val, float* %base, i64 %vl, <vscale x 8 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv4r.v v4, v8
; CHECK-NEXT: vsetvli a1, a1, e32,m4,tu,mu
; CHECK-NEXT: vlseg2e32ff.v v4, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m4 killed $v8m4 killed $v4m4_v8m4
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 8 x float>,<vscale x 8 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv8f32(<vscale x 8 x float> %val,<vscale x 8 x float> %val, float* %base, <vscale x 8 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 8 x float>,<vscale x 8 x float>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 8 x float> %1
}
declare {<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg2ff.nxv2f64(double* , i64)
declare {<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg2ff.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64)
define <vscale x 2 x double> @test_vlseg2ff_nxv2f64(double* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vlseg2e64ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg2ff.nxv2f64(double* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 2 x double> %1
}
define <vscale x 2 x double> @test_vlseg2ff_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
; CHECK-NEXT: vlseg2e64ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg2ff.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 2 x double> %1
}
declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg3ff.nxv2f64(double* , i64)
declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg3ff.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64)
define <vscale x 2 x double> @test_vlseg3ff_nxv2f64(double* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vlseg3e64ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg3ff.nxv2f64(double* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 2 x double> %1
}
define <vscale x 2 x double> @test_vlseg3ff_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
; CHECK-NEXT: vlseg3e64ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg3ff.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 2 x double> %1
}
declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg4ff.nxv2f64(double* , i64)
declare {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg4ff.mask.nxv2f64(<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, double*, <vscale x 2 x i1>, i64)
define <vscale x 2 x double> @test_vlseg4ff_nxv2f64(double* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e64,m2,ta,mu
; CHECK-NEXT: vlseg4e64ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg4ff.nxv2f64(double* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 2 x double> %1
}
define <vscale x 2 x double> @test_vlseg4ff_mask_nxv2f64(<vscale x 2 x double> %val, double* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vmv2r.v v12, v6
; CHECK-NEXT: vsetvli a1, a1, e64,m2,tu,mu
; CHECK-NEXT: vlseg4e64ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} @llvm.riscv.vlseg4ff.mask.nxv2f64(<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val,<vscale x 2 x double> %val, double* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>,<vscale x 2 x double>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 2 x double> %1
}
declare {<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg2ff.nxv4f16(half* , i64)
declare {<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)
define <vscale x 4 x half> @test_vlseg2ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg2ff.nxv4f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 4 x half> %1
}
define <vscale x 4 x half> @test_vlseg2ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 4 x half> %1
}
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg3ff.nxv4f16(half* , i64)
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)
define <vscale x 4 x half> @test_vlseg3ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg3ff.nxv4f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 4 x half> %1
}
define <vscale x 4 x half> @test_vlseg3ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 4 x half> %1
}
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg4ff.nxv4f16(half* , i64)
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)
define <vscale x 4 x half> @test_vlseg4ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg4ff.nxv4f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 4 x half> %1
}
define <vscale x 4 x half> @test_vlseg4ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 4 x half> %1
}
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg5ff.nxv4f16(half* , i64)
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg5ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)
define <vscale x 4 x half> @test_vlseg5ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg5ff.nxv4f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 4 x half> %1
}
define <vscale x 4 x half> @test_vlseg5ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg5ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 4 x half> %1
}
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg6ff.nxv4f16(half* , i64)
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg6ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)
define <vscale x 4 x half> @test_vlseg6ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg6ff.nxv4f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 4 x half> %1
}
define <vscale x 4 x half> @test_vlseg6ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg6ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 4 x half> %1
}
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg7ff.nxv4f16(half* , i64)
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg7ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)
define <vscale x 4 x half> @test_vlseg7ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg7ff.nxv4f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 4 x half> %1
}
define <vscale x 4 x half> @test_vlseg7ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg7ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 4 x half> %1
}
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg8ff.nxv4f16(half* , i64)
declare {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg8ff.mask.nxv4f16(<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, half*, <vscale x 4 x i1>, i64)
define <vscale x 4 x half> @test_vlseg8ff_nxv4f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg8ff.nxv4f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 4 x half> %1
}
define <vscale x 4 x half> @test_vlseg8ff_mask_nxv4f16(<vscale x 4 x half> %val, half* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e16,m1,tu,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} @llvm.riscv.vlseg8ff.mask.nxv4f16(<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val,<vscale x 4 x half> %val, half* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>,<vscale x 4 x half>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 4 x half> %1
}
declare {<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg2ff.nxv2f16(half* , i64)
declare {<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)
define <vscale x 2 x half> @test_vlseg2ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg2ff.nxv2f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 2 x half> %1
}
define <vscale x 2 x half> @test_vlseg2ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg2e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg2ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 2 x half> %1
}
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg3ff.nxv2f16(half* , i64)
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)
define <vscale x 2 x half> @test_vlseg3ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg3ff.nxv2f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 2 x half> %1
}
define <vscale x 2 x half> @test_vlseg3ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg3e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg3ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 2 x half> %1
}
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg4ff.nxv2f16(half* , i64)
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)
define <vscale x 2 x half> @test_vlseg4ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg4ff.nxv2f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 2 x half> %1
}
define <vscale x 2 x half> @test_vlseg4ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg4e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg4ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 2 x half> %1
}
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg5ff.nxv2f16(half* , i64)
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg5ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)
define <vscale x 2 x half> @test_vlseg5ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg5ff.nxv2f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 2 x half> %1
}
define <vscale x 2 x half> @test_vlseg5ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg5ff_mask_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg5e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg5ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 5
store i64 %2, i64* %outvl
ret <vscale x 2 x half> %1
}
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg6ff.nxv2f16(half* , i64)
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg6ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)
define <vscale x 2 x half> @test_vlseg6ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg6ff.nxv2f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 2 x half> %1
}
define <vscale x 2 x half> @test_vlseg6ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg6ff_mask_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg6e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg6ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 6
store i64 %2, i64* %outvl
ret <vscale x 2 x half> %1
}
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg7ff.nxv2f16(half* , i64)
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg7ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)
define <vscale x 2 x half> @test_vlseg7ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg7ff.nxv2f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 2 x half> %1
}
define <vscale x 2 x half> @test_vlseg7ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg7ff_mask_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg7e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg7ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 7
store i64 %2, i64* %outvl
ret <vscale x 2 x half> %1
}
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg8ff.nxv2f16(half* , i64)
declare {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg8ff.mask.nxv2f16(<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, half*, <vscale x 2 x i1>, i64)
define <vscale x 2 x half> @test_vlseg8ff_nxv2f16(half* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg8ff.nxv2f16(half* %base, i64 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 2 x half> %1
}
define <vscale x 2 x half> @test_vlseg8ff_mask_nxv2f16(<vscale x 2 x half> %val, half* %base, i64 %vl, <vscale x 2 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg8ff_mask_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v7, v8
; CHECK-NEXT: vmv1r.v v9, v7
; CHECK-NEXT: vmv1r.v v10, v7
; CHECK-NEXT: vmv1r.v v11, v7
; CHECK-NEXT: vmv1r.v v12, v7
; CHECK-NEXT: vmv1r.v v13, v7
; CHECK-NEXT: vmv1r.v v14, v7
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,tu,mu
; CHECK-NEXT: vlseg8e16ff.v v7, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8 killed $v8 killed $v7_v8_v9_v10_v11_v12_v13_v14
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} @llvm.riscv.vlseg8ff.mask.nxv2f16(<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val,<vscale x 2 x half> %val, half* %base, <vscale x 2 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 1
%2 = extractvalue {<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>,<vscale x 2 x half>, i64} %0, 8
store i64 %2, i64* %outvl
ret <vscale x 2 x half> %1
}
declare {<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg2ff.nxv4f32(float* , i64)
declare {<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64)
define <vscale x 4 x float> @test_vlseg2ff_nxv4f32(float* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vlseg2e32ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg2ff.nxv4f32(float* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 4 x float> %1
}
define <vscale x 4 x float> @test_vlseg2ff_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg2ff_mask_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vlseg2e32ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg2ff.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 2
store i64 %2, i64* %outvl
ret <vscale x 4 x float> %1
}
declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg3ff.nxv4f32(float* , i64)
declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg3ff.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64)
define <vscale x 4 x float> @test_vlseg3ff_nxv4f32(float* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vlseg3e32ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg3ff.nxv4f32(float* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 4 x float> %1
}
define <vscale x 4 x float> @test_vlseg3ff_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg3ff_mask_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vlseg3e32ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg3ff.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 3
store i64 %2, i64* %outvl
ret <vscale x 4 x float> %1
}
declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg4ff.nxv4f32(float* , i64)
declare {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg4ff.mask.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, float*, <vscale x 4 x i1>, i64)
define <vscale x 4 x float> @test_vlseg4ff_nxv4f32(float* %base, i64 %vl, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vlseg4e32ff.v v6, (a0)
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg4ff.nxv4f32(float* %base, i64 %vl)
%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 4 x float> %1
}
define <vscale x 4 x float> @test_vlseg4ff_mask_nxv4f32(<vscale x 4 x float> %val, float* %base, i64 %vl, <vscale x 4 x i1> %mask, i64* %outvl) {
; CHECK-LABEL: test_vlseg4ff_mask_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv2r.v v6, v8
; CHECK-NEXT: vmv2r.v v10, v6
; CHECK-NEXT: vmv2r.v v12, v6
; CHECK-NEXT: vsetvli a1, a1, e32,m2,tu,mu
; CHECK-NEXT: vlseg4e32ff.v v6, (a0), v0.t
; CHECK-NEXT: csrr a0, vl
; CHECK-NEXT: sd a0, 0(a2)
; CHECK-NEXT: # kill: def $v8m2 killed $v8m2 killed $v6m2_v8m2_v10m2_v12m2
; CHECK-NEXT: ret
entry:
%0 = tail call {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} @llvm.riscv.vlseg4ff.mask.nxv4f32(<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val,<vscale x 4 x float> %val, float* %base, <vscale x 4 x i1> %mask, i64 %vl)
%1 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 1
%2 = extractvalue {<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>, i64} %0, 4
store i64 %2, i64* %outvl
ret <vscale x 4 x float> %1
}
llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll