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Differential D95134

[RISCV] Use v8-v23 as argument registers to conform to the proposal.
ClosedPublic

Authored by HsiangKai on Jan 21 2021, 7:11 AM.

Details

Reviewers
craig.topper
rogfer01
frasercrmck
jrtc27
evandro
asb
luismarques
Commits
rG6e360460f14b: [RISCV] Use v8-v23 as argument registers to conform to the proposal.
Summary

The maximum LMUL is 8. We need 16 vector registers for two LMUL-8 arguments. The modification follows the proposal of psABI in https://github.com/riscv/riscv-elf-psabi-doc/pull/171

There are lots of test files need to be updated. It is too large to contain all of these test files in one commit to upload. I only add vadd test files to demonstrate the modification. If this patch is accepted, I will update all of these test files and commit them to the repository.

Diff Detail

Event Timeline

HsiangKai created this revision.Jan 21 2021, 7:11 AM
Herald added subscribers: NickHung, apazos, sameer.abuasal and 20 others. · View Herald TranscriptJan 21 2021, 7:11 AM
HsiangKai requested review of this revision.Jan 21 2021, 7:11 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 21 2021, 7:11 AM
Herald added a subscriber: MaskRay. · View Herald Transcript
kito-cheng added a comment.Jan 21 2021, 7:33 AM

Add a dedicated test file to demonstrate and verify the ABI would be better.

Harbormaster completed remote builds in B86087: Diff 318190.Jan 21 2021, 8:22 AM
craig.topper accepted this revision.Jan 21 2021, 1:54 PM

LGTM

This revision is now accepted and ready to land.Jan 21 2021, 1:54 PM
HsiangKai added a comment.Jan 21 2021, 3:36 PM
In D95134#2512496, @kito-cheng wrote:

Add a dedicated test file to demonstrate and verify the ABI would be better.

I would add test cases for ABI in D94465. In D94465, we could demonstrate how to pass vector arguments between caller and callee. In addition, we could show how to pass vector arguments through memory by reference.

This revision was landed with ongoing or failed builds.Jan 21 2021, 3:59 PM
Closed by commit rG6e360460f14b: [RISCV] Use v8-v23 as argument registers to conform to the proposal. (authored by HsiangKai). · Explain Why
This revision was automatically updated to reflect the committed changes.
HsiangKai added a commit: rG6e360460f14b: [RISCV] Use v8-v23 as argument registers to conform to the proposal..

Large Diff

This large diff affects 461 files. Files without inline comments have been collapsed. Expand All Files

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Diff 318342

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll

llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll

llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll

llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll

llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll

llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vaadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vaaddu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vadc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamoadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamoadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamoand-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamoand-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamomax-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamomax-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamomaxu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamomin-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamomin-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamominu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vamominu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vamoor-rv32.ll

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llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfnmacc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfnmadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfnmsac-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfnmsub-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfrdiv-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfrsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfrsub-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfsgnj-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfsgnjn-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfsgnjx-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfslide1down-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfsqrt-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfsub-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vid-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vid-rv64.ll

llvm/test/CodeGen/RISCV/rvv/viota-rv32.ll

llvm/test/CodeGen/RISCV/rvv/viota-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vle-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vle-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vlse-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vlse-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmacc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmadc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll

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