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[RISCV] Share VTYPE encoding code between the assembler and the CustomInserter for adding VSETVLI before vector instructions
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Authored by craig.topper on Dec 7 2020, 9:02 PM.

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Summary

This merges the SEW and LMUL enums that each used into singles enums in RISCVBaseInfo.h. The patch also adds a new encoding helper to take SEW, LMUL, tail agnostic, mask agnostic and turn it into a vtype immediate.

I also stopped storing the Encoding in the VTYPE operand in the assembler. It is easy to calculate when adding the operand which should only happen once per instruction.

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craig.topper created this revision.Dec 7 2020, 9:02 PM
craig.topper requested review of this revision.Dec 7 2020, 9:02 PM
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I had actually prototyped something very similar so I'm all for this.

llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
363

I think that it would help to be explicit (in a comment) that this operand encoding is the same as the vtype binary encoding and is assumed to be so in the MC layers.

craig.topper edited the summary of this revision. (Show Details)

Add comments to the new functions

This revision was not accepted when it landed; it landed in state Needs Review.Dec 8 2020, 4:19 PM
This revision was automatically updated to reflect the committed changes.