[RISCV] Basic jump table lowering

[nand]

Summary

This patch enables jump table lowering in the RISC-V backend.

In addition to the test case included, the new lowering was
tested by compiling the OCaml runtime and running it under qemu.

[lenary]

llvm/test/CodeGen/RISCV/jumptable.ll

1–9

I *think* these tests need to be expanded to cover both the low code model (currently covered), and the medium code model (which uses auipc). I've added some RUN lines for you, if you take the suggestion, you'll need to re-run update_llc_test_checks.py

[nand]

Expanded test to cover 32-bit/64-bit variants with small and medium code models

[lenary]

llvm/test/CodeGen/RISCV/jumptable.ll

12

update_llc_test_checks.py doesn't remove unused prefixes, so you can delete the RV32I-* lines :)

[jrtc27]

llvm/test/CodeGen/RISCV/jumptable.ll

3

codemodel-lowering.ll uses -SMALL and -MEDIUM; please be consistent with that.

12

This whole set of check lines needs to go (and not sure how the formatting got messed up...).

[jrtc27]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

126

Why is it that expandAuipcInstPair needs to handle this specially but there's no corresponding logic for medlow's plain LUI/ADDI?

[nand]

consistent run lines

[nand]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

126

Based on my understanding, addDisp seems to be a generic method that produces an operand with an arbitrary offset from some reference, however it doesn't seem like offsets into jump tables are supported. Since the offset is always 0, the jump table index is handled separately. I might be wrong though.

[lenary]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

265

Let's make sure this doesn't have a major code size impact. I'm not sure the threshold GCC uses, something like 3 IIRC?

The problem for code size is that the sequence to hold the jump table and the calculate the jump index is longer than a chain of ifs, if there aren't too many entries.

[jrtc27]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

126

Right, then surely the correct fix is to add an MO_JumpTableIndex case to addDisp that calls addJumpTableIndex?

[lenary]

@nand thank you for this patch, it's been something missing from the RISC-V backend for a while, which is why you're getting so much feedback so quickly.

[nand]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

126

addDisp is common to all architectures, so I am reluctant to change it. Furthermore, addDisp takes an offset operand and the only sensible value for jump tables is 0. I think handling jump tables separately is nicer than asserting in addDisp that off is 0.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

265

I am using this backend to compile OCaml in a weird way. I could try to build a bunch of OCaml binaries with various thresholds, report the results and maybe we can make a decision for a reasonable default?

[nand]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

265

I now realised that I cannot change this threshold in my code generator, so I cannot provide any measurements.

Based on my understanding of the code, unless the target explicitly overwrites it, the -min-jump-table-entries
argument is used, which defaults to 4. If that is reasonable, maybe there is no point in hardcoding a default value?

[jrtc27]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

126

I disagree. It's a generic method meant to take any operand one would reasonably want to use. We already use it for the very-similar constant pool index. You also don't need to assert off is 0; that's not done for CPIs, and if you pass in non-zero then you get what you asked for, ie Symbol.getIndex() + off. The only reason it's not currently supported in addDisp is that nobody has yet needed it, as other backends tend to just duplicate lowering for the different hooks. Just mirror the CPI code for what is basically a special case of it.

[jrtc27]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

126

Note that this has been done in the past for RISC-V too; see https://reviews.llvm.org/D60136 (needed for https://reviews.llvm.org/D54143).

[jrtc27]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

126

I see, CreateJTI doesn't have an Offset. Well, IMO it should for completeness, but yes you probably want to assert the offset is 0 in addDisp then.

[nand]

moved logic into addDisp

[nand]

update

[jrtc27]

You still appear to have the old patch that doesn't change addDisp.

[nand]

applied the changes on the correct checkout of the llvm repository this time...

[jrtc27]

This seems fine to me now other than the outstanding discussion about code size.

[nand]

Is there anything I could do to test the impact on code size? As I mentioned previously, in my setting I cannot easily turn the use of jump tables off. Are there any binaries that are relatively easy to cross compile and are of interest?

[lenary]

There was a previous patch which had some feedback about thresholds: https://reviews.llvm.org/D48430

[nand]

updated the minimum number of jump table entries

[nand]

fixed test and added below/above threshold cases

[lenary]

Cool. I think we can tweak the threshold later, but this should start us in a reasonable place. Thanks for your patience, I'm happy for this to land.

The previous discussion pointed out that GCC's default threshold on RISC-V was 5 (thanks @kito-cheng for the link). We match that here, so that should avoid the worst of the performance regressions.

[nand]

ping

[jrtc27]

I agree with @lenary, I think this is fine to land (with the whitespace fix :)) and if it turns out the threshold is too low then we'll soon find out and can adjust accordingly (but I imagine not, 5 feels like a sensible default). Or if it's too high!

llvm/test/CodeGen/RISCV/jumptable.ll

190

Nit: unwanted extra blank line

[nand]

removed newline

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

bool RISCVExpandPseudo::expandAuipcInstPair(
   MachineBasicBlock *NewMBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
 
   // Tell AsmPrinter that we unconditionally want the symbol of this label to be
   // emitted.
   NewMBB->setLabelMustBeEmitted();
 
   MF->insert(++MBB.getIterator(), NewMBB);
 
+  if (Symbol.isJTI()) {
+    BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg)
+        .addJumpTableIndex(Symbol.getIndex(), FlagsHi);
+  } else {
     BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg)
         .addDisp(Symbol, 0, FlagsHi);
+  }
   BuildMI(NewMBB, DL, TII->get(SecondOpcode), DestReg)
       .addReg(DestReg)
       .addMBB(NewMBB, RISCVII::MO_PCREL_LO);
 
   // Move all the rest of the instructions to NewMBB.
   NewMBB->splice(NewMBB->end(), &MBB, std::next(MBBI), MBB.end());
   // Update machine-CFG edges.
   NewMBB->transferSuccessorsAndUpdatePHIs(&MBB);

llvm/lib/Target/RISCV/RISCVISelLowering.h

private:
 
   SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
                            bool UseGOT) const;
   SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG) const;
 
   SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
   SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

if (Subtarget.is64Bit()) {
     setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
     setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
     setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
   }
 
   setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
   setOperationAction(ISD::BlockAddress, XLenVT, Custom);
   setOperationAction(ISD::ConstantPool, XLenVT, Custom);
+  setOperationAction(ISD::JumpTable, XLenVT, Custom);
 
   setOperationAction(ISD::GlobalTLSAddress, XLenVT, Custom);
 
   // TODO: On M-mode only targets, the cycle[h] CSR may not be present.
   // Unfortunately this can't be determined just from the ISA naming string.
   setOperationAction(ISD::READCYCLECOUNTER, MVT::i64,
                      Subtarget.is64Bit() ? Legal : Custom);
 
RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   setBooleanContents(ZeroOrOneBooleanContent);
 
   // Function alignments.
   const Align FunctionAlignment(Subtarget.hasStdExtC() ? 2 : 4);
   setMinFunctionAlignment(FunctionAlignment);
   setPrefFunctionAlignment(FunctionAlignment);
 
-  // Effectively disable jump table generation.
-  setMinimumJumpTableEntries(INT_MAX);
-
   // Jumps are expensive, compared to logic
   setJumpIsExpensive();
 
   // We can use any register for comparisons
   setHasMultipleConditionRegisters();
 
   if (Subtarget.hasStdExtZbp()) {
     setTargetDAGCombine(ISD::OR);
SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   default:
     report_fatal_error("unimplemented operand");
   case ISD::GlobalAddress:
     return lowerGlobalAddress(Op, DAG);
   case ISD::BlockAddress:
     return lowerBlockAddress(Op, DAG);
   case ISD::ConstantPool:
     return lowerConstantPool(Op, DAG);
+  case ISD::JumpTable:
+    return lowerJumpTable(Op, DAG);
   case ISD::GlobalTLSAddress:
     return lowerGlobalTLSAddress(Op, DAG);
   case ISD::SELECT:
     return lowerSELECT(Op, DAG);
   case ISD::VASTART:
     return lowerVASTART(Op, DAG);
   case ISD::FRAMEADDR:
     return lowerFRAMEADDR(Op, DAG);

 }
 
 static SDValue getTargetNode(ConstantPoolSDNode *N, SDLoc DL, EVT Ty,
                              SelectionDAG &DAG, unsigned Flags) {
   return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlign(),
                                    N->getOffset(), Flags);
 }
 
+static SDValue getTargetNode(JumpTableSDNode *N, SDLoc DL, EVT Ty,
+                             SelectionDAG &DAG, unsigned Flags) {
+  return DAG.getTargetJumpTable(N->getIndex(), Ty, Flags);
+}
+
 template <class NodeTy>
 SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
                                      bool IsLocal) const {
   SDLoc DL(N);
   EVT Ty = getPointerTy(DAG.getDataLayout());
 
   if (isPositionIndependent()) {
     SDValue Addr = getTargetNode(N, DL, Ty, DAG, 0);

 
 SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op,
                                                SelectionDAG &DAG) const {
   ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
 
   return getAddr(N, DAG);
 }
 
+SDValue RISCVTargetLowering::lowerJumpTable(SDValue Op,
+                                            SelectionDAG &DAG) const {
+  JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
+
+  return getAddr(N, DAG);
+}
+
 SDValue RISCVTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N,
                                               SelectionDAG &DAG,
                                               bool UseGOT) const {
   SDLoc DL(N);
   EVT Ty = getPointerTy(DAG.getDataLayout());
   const GlobalValue *GV = N->getGlobal();
   MVT XLenVT = Subtarget.getXLenVT();
 

llvm/lib/Target/RISCV/RISCVMCInstLower.cpp

case MachineOperand::MO_BlockAddress:
     break;
   case MachineOperand::MO_ExternalSymbol:
     MCOp = lowerSymbolOperand(
         MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP);
     break;
   case MachineOperand::MO_ConstantPoolIndex:
     MCOp = lowerSymbolOperand(MO, AP.GetCPISymbol(MO.getIndex()), AP);
     break;
+  case MachineOperand::MO_JumpTableIndex:
+    MCOp = lowerSymbolOperand(MO, AP.GetJTISymbol(MO.getIndex()), AP);
+    break;
   }
   return true;
 }
 
 void llvm::LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
                                           const AsmPrinter &AP) {
   OutMI.setOpcode(MI->getOpcode());
 
   for (const MachineOperand &MO : MI->operands()) {
     MCOperand MCOp;
     if (LowerRISCVMachineOperandToMCOperand(MO, MCOp, AP))
       OutMI.addOperand(MCOp);
   }
 }

llvm/test/CodeGen/RISCV/jumptable.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32I-SMALL
+; RUN: llc -mtriple=riscv32 -code-model=medium -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32I-MED
+; RUN: llc -mtriple=riscv64 -code-model=small -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64I-SMALL
+; RUN: llc -mtriple=riscv64 -code-model=medium -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64I-MED
 
 define void @jt(i32 %in, i32* %out) nounwind {
 ; RV32I-LABEL: jt:
 ; RV32I:       # %bb.0: # %entry
-; RV32I-NEXT:    addi a2, zero, 2
-; RV32I-NEXT:    blt a2, a0, .LBB0_4
-; RV32I-NEXT:  # %bb.1: # %entry
-; RV32I-NEXT:    addi a2, zero, 1
-; RV32I-NEXT:    beq a0, a2, .LBB0_7
-; RV32I-NEXT:  # %bb.2: # %entry
-; RV32I-NEXT:    addi a2, zero, 2
-; RV32I-NEXT:    bne a0, a2, .LBB0_10
-; RV32I-NEXT:  # %bb.3: # %bb2
-; RV32I-NEXT:    addi a0, zero, 3
-; RV32I-NEXT:    j .LBB0_9
-; RV32I-NEXT:  .LBB0_4: # %entry
-; RV32I-NEXT:    addi a2, zero, 3
-; RV32I-NEXT:    beq a0, a2, .LBB0_8
-; RV32I-NEXT:  # %bb.5: # %entry
-; RV32I-NEXT:    addi a2, zero, 4
-; RV32I-NEXT:    bne a0, a2, .LBB0_10
-; RV32I-NEXT:  # %bb.6: # %bb4
-; RV32I-NEXT:    addi a0, zero, 1
-; RV32I-NEXT:    j .LBB0_9
-; RV32I-NEXT:  .LBB0_7: # %bb1
-; RV32I-NEXT:    addi a0, zero, 4
-; RV32I-NEXT:    j .LBB0_9
-; RV32I-NEXT:  .LBB0_8: # %bb3
-; RV32I-NEXT:    addi a0, zero, 2
-; RV32I-NEXT:  .LBB0_9: # %exit
-; RV32I-NEXT:    sw a0, 0(a1)
-; RV32I-NEXT:  .LBB0_10: # %exit
-; RV32I-NEXT:    ret
+; RV32I-NEXT:   addi  a0, a0, -1
+; RV32I-NEXT:   addi  a2, zero, 3
+; RV32I-NEXT:   bltu  a2, a0, .LBB0_7
+; RV32I-NEXT: # %bb.1:                                # %entry
+; RV32I-NEXT:   slli  a0, a0, 2
+; RV32I-NEXT:   lui a2, %hi(.LJTI0_0)
+; RV32I-NEXT:   addi  a2, a2, %lo(.LJTI0_0)
+; RV32I-NEXT:   add a0, a0, a2
+; RV32I-NEXT:   lw  a0, 0(a0)
+; RV32I-NEXT:   jr  a0
+; RV32I-NEXT: .LBB0_2:                                # %bb1
+; RV32I-NEXT:   addi  a0, zero, 4
+; RV32I-NEXT:   j .LBB0_6
+; RV32I-NEXT: .LBB0_3:                                # %bb2
+; RV32I-NEXT:   addi  a0, zero, 3
+; RV32I-NEXT:   j .LBB0_6
+; RV32I-NEXT: .LBB0_4:                                # %bb3
+; RV32I-NEXT:   addi  a0, zero, 2
+; RV32I-NEXT:   j .LBB0_6
+; RV32I-NEXT: .LBB0_5:                                # %bb4
+; RV32I-NEXT:   addi  a0, zero, 1
+; RV32I-NEXT: .LBB0_6:                                # %exit
+; RV32I-NEXT:   sw  a0, 0(a1)
+; RV32I-NEXT: .LBB0_7:                                # %exit
+; RV32I-NEXT:   ret
+; RV32I-NEXT: .Lfunc_end0:
+; RV32I-NEXT:   .size jt, .Lfunc_end0-jt
+; RV32I-NEXT:   .section  .rodata,"a",@progbits
+; RV32I-NEXT:   .p2align  2
+; RV32I-NEXT: .LJTI0_0:
+; RV32I-NEXT:   .word .LBB0_2
+; RV32I-NEXT:   .word .LBB0_3
+; RV32I-NEXT:   .word .LBB0_4
+; RV32I-NEXT:   .word .LBB0_5
+; RV32I-SMALL-LABEL: jt:
+; RV32I-SMALL:       # %bb.0: # %entry
+; RV32I-SMALL-NEXT:    addi a0, a0, -1
+; RV32I-SMALL-NEXT:    addi a2, zero, 3
+; RV32I-SMALL-NEXT:    bltu a2, a0, .LBB0_7
+; RV32I-SMALL-NEXT:  # %bb.1: # %entry
+; RV32I-SMALL-NEXT:    slli a0, a0, 2
+; RV32I-SMALL-NEXT:    lui a2, %hi(.LJTI0_0)
+; RV32I-SMALL-NEXT:    addi a2, a2, %lo(.LJTI0_0)
+; RV32I-SMALL-NEXT:    add a0, a0, a2
+; RV32I-SMALL-NEXT:    lw a0, 0(a0)
+; RV32I-SMALL-NEXT:    jr a0
+; RV32I-SMALL-NEXT:  .LBB0_2: # %bb1
+; RV32I-SMALL-NEXT:    addi a0, zero, 4
+; RV32I-SMALL-NEXT:    j .LBB0_6
+; RV32I-SMALL-NEXT:  .LBB0_3: # %bb2
+; RV32I-SMALL-NEXT:    addi a0, zero, 3
+; RV32I-SMALL-NEXT:    j .LBB0_6
+; RV32I-SMALL-NEXT:  .LBB0_4: # %bb3
+; RV32I-SMALL-NEXT:    addi a0, zero, 2
+; RV32I-SMALL-NEXT:    j .LBB0_6
+; RV32I-SMALL-NEXT:  .LBB0_5: # %bb4
+; RV32I-SMALL-NEXT:    addi a0, zero, 1
+; RV32I-SMALL-NEXT:  .LBB0_6: # %exit
+; RV32I-SMALL-NEXT:    sw a0, 0(a1)
+; RV32I-SMALL-NEXT:  .LBB0_7: # %exit
+; RV32I-SMALL-NEXT:    ret
+;
+; RV32I-MED-LABEL: jt:
+; RV32I-MED:       # %bb.0: # %entry
+; RV32I-MED-NEXT:    addi a0, a0, -1
+; RV32I-MED-NEXT:    addi a2, zero, 3
+; RV32I-MED-NEXT:    bltu a2, a0, .LBB0_7
+; RV32I-MED-NEXT:  # %bb.1: # %entry
+; RV32I-MED-NEXT:    slli a0, a0, 2
+; RV32I-MED-NEXT:  .LBB0_8: # %entry
+; RV32I-MED-NEXT:    # Label of block must be emitted
+; RV32I-MED-NEXT:    auipc a2, %pcrel_hi(.LJTI0_0)
+; RV32I-MED-NEXT:    addi a2, a2, %pcrel_lo(.LBB0_8)
+; RV32I-MED-NEXT:    add a0, a0, a2
+; RV32I-MED-NEXT:    lw a0, 0(a0)
+; RV32I-MED-NEXT:    jr a0
+; RV32I-MED-NEXT:  .LBB0_2: # %bb1
+; RV32I-MED-NEXT:    addi a0, zero, 4
+; RV32I-MED-NEXT:    j .LBB0_6
+; RV32I-MED-NEXT:  .LBB0_3: # %bb2
+; RV32I-MED-NEXT:    addi a0, zero, 3
+; RV32I-MED-NEXT:    j .LBB0_6
+; RV32I-MED-NEXT:  .LBB0_4: # %bb3
+; RV32I-MED-NEXT:    addi a0, zero, 2
+; RV32I-MED-NEXT:    j .LBB0_6
+; RV32I-MED-NEXT:  .LBB0_5: # %bb4
+; RV32I-MED-NEXT:    addi a0, zero, 1
+; RV32I-MED-NEXT:  .LBB0_6: # %exit
+; RV32I-MED-NEXT:    sw a0, 0(a1)
+; RV32I-MED-NEXT:  .LBB0_7: # %exit
+; RV32I-MED-NEXT:    ret
+;
+; RV64I-SMALL-LABEL: jt:
+; RV64I-SMALL:       # %bb.0: # %entry
+; RV64I-SMALL-NEXT:    slli a0, a0, 32
+; RV64I-SMALL-NEXT:    srli a0, a0, 32
+; RV64I-SMALL-NEXT:    addi a0, a0, -1
+; RV64I-SMALL-NEXT:    addi a2, zero, 3
+; RV64I-SMALL-NEXT:    bltu a2, a0, .LBB0_7
+; RV64I-SMALL-NEXT:  # %bb.1: # %entry
+; RV64I-SMALL-NEXT:    slli a0, a0, 3
+; RV64I-SMALL-NEXT:    lui a2, %hi(.LJTI0_0)
+; RV64I-SMALL-NEXT:    addi a2, a2, %lo(.LJTI0_0)
+; RV64I-SMALL-NEXT:    add a0, a0, a2
+; RV64I-SMALL-NEXT:    ld a0, 0(a0)
+; RV64I-SMALL-NEXT:    jr a0
+; RV64I-SMALL-NEXT:  .LBB0_2: # %bb1
+; RV64I-SMALL-NEXT:    addi a0, zero, 4
+; RV64I-SMALL-NEXT:    j .LBB0_6
+; RV64I-SMALL-NEXT:  .LBB0_3: # %bb2
+; RV64I-SMALL-NEXT:    addi a0, zero, 3
+; RV64I-SMALL-NEXT:    j .LBB0_6
+; RV64I-SMALL-NEXT:  .LBB0_4: # %bb3
+; RV64I-SMALL-NEXT:    addi a0, zero, 2
+; RV64I-SMALL-NEXT:    j .LBB0_6
+; RV64I-SMALL-NEXT:  .LBB0_5: # %bb4
+; RV64I-SMALL-NEXT:    addi a0, zero, 1
+; RV64I-SMALL-NEXT:  .LBB0_6: # %exit
+; RV64I-SMALL-NEXT:    sw a0, 0(a1)
+; RV64I-SMALL-NEXT:  .LBB0_7: # %exit
+; RV64I-SMALL-NEXT:    ret
+;
+; RV64I-MED-LABEL: jt:
+; RV64I-MED:       # %bb.0: # %entry
+; RV64I-MED-NEXT:    slli a0, a0, 32
+; RV64I-MED-NEXT:    srli a0, a0, 32
+; RV64I-MED-NEXT:    addi a0, a0, -1
+; RV64I-MED-NEXT:    addi a2, zero, 3
+; RV64I-MED-NEXT:    bltu a2, a0, .LBB0_7
+; RV64I-MED-NEXT:  # %bb.1: # %entry
+; RV64I-MED-NEXT:    slli a0, a0, 3
+; RV64I-MED-NEXT:  .LBB0_8: # %entry
+; RV64I-MED-NEXT:    # Label of block must be emitted
+; RV64I-MED-NEXT:    auipc a2, %pcrel_hi(.LJTI0_0)
+; RV64I-MED-NEXT:    addi a2, a2, %pcrel_lo(.LBB0_8)
+; RV64I-MED-NEXT:    add a0, a0, a2
+; RV64I-MED-NEXT:    ld a0, 0(a0)
+; RV64I-MED-NEXT:    jr a0
+; RV64I-MED-NEXT:  .LBB0_2: # %bb1
+; RV64I-MED-NEXT:    addi a0, zero, 4
+; RV64I-MED-NEXT:    j .LBB0_6
+; RV64I-MED-NEXT:  .LBB0_3: # %bb2
+; RV64I-MED-NEXT:    addi a0, zero, 3
+; RV64I-MED-NEXT:    j .LBB0_6
+; RV64I-MED-NEXT:  .LBB0_4: # %bb3
+; RV64I-MED-NEXT:    addi a0, zero, 2
+; RV64I-MED-NEXT:    j .LBB0_6
+; RV64I-MED-NEXT:  .LBB0_5: # %bb4
+; RV64I-MED-NEXT:    addi a0, zero, 1
+; RV64I-MED-NEXT:  .LBB0_6: # %exit
+; RV64I-MED-NEXT:    sw a0, 0(a1)
+; RV64I-MED-NEXT:  .LBB0_7: # %exit
+; RV64I-MED-NEXT:    ret
 entry:
   switch i32 %in, label %exit [
     i32 1, label %bb1
     i32 2, label %bb2
     i32 3, label %bb3
     i32 4, label %bb4
   ]
 bb1:
   store i32 4, i32* %out
   br label %exit
 bb2:
   store i32 3, i32* %out
   br label %exit
 bb3:
   store i32 2, i32* %out
   br label %exit
 bb4:
   store i32 1, i32* %out
   br label %exit
 exit:
   ret void
 }