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Show First 20 Lines • Show All 997 Lines • ▼ Show 20 Lines	case ISD::UREM:
if (N->getOperand(0).getOpcode() == ISD::Constant \|\|		if (N->getOperand(0).getOpcode() == ISD::Constant \|\|
N->getOperand(1).getOpcode() == ISD::Constant)		N->getOperand(1).getOpcode() == ISD::Constant)
return;		return;
Results.push_back(customLegalizeToWOp(N, DAG));		Results.push_back(customLegalizeToWOp(N, DAG));
break;		break;
case ISD::BITCAST: {		case ISD::BITCAST: {
assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&		assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
Subtarget.hasStdExtF() && "Unexpected custom legalisation");		Subtarget.hasStdExtF() && "Unexpected custom legalisation");
SDLoc DL(N);
SDValue Op0 = N->getOperand(0);		SDValue Op0 = N->getOperand(0);
if (Op0.getValueType() != MVT::f32)		if (Op0.getValueType() != MVT::f32)
return;		return;
SDValue FPConv =		SDValue FPConv =
DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Op0);		DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Op0);
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, FPConv));		Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, FPConv));
break;		break;
}		}
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[RISCV] eliminate the repetition declare of SDLoc DLClosedPublic