[ARM] Add enhanced counter virtualization system registers

[stuij]

Summary

This patch upstreams support for the ARMv8.6A Enhanced Counter Virtualization
(ECV) extension, which adds 6 new system registers.

See ARMv8.6-ECV in the Arm Architecture Reference Manual Armv8 for more
information.

[SjoerdMeijer]

LGTM (perhaps the same nit as in the other review)

[stuij]

don't just test with x0

llvm/lib/Target/AArch64/AArch64.td

def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
     "that allows a memory tag in the upper address bits">;
 
 def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16",
     "true", "Enable BFloat16 Extension" >;
 
 def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
     "true", "Enable fine grained virtualization traps extension">;
 
+def FeatureEnhancedCounterVirtualization :
+      SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization",
+      "true", "Enable enhanced counter virtualization extension">;
+
 
 //===----------------------------------------------------------------------===//
 // Architectures.
 //
 
 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
   "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM,
   FeaturePAN, FeatureLOR, FeatureVH]>;
def HasV8_5aOps : SubtargetFeature<
   "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
   [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
    FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
    FeatureBranchTargetId]>;
 
 def HasV8_6aOps : SubtargetFeature<
   "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",
 
-  [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps]>;
+  [HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
+   FeatureEnhancedCounterVirtualization]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "AArch64RegisterInfo.td"
 include "AArch64RegisterBanks.td"
 include "AArch64CallingConvention.td"

llvm/lib/Target/AArch64/AArch64Subtarget.h

protected:
   bool HasRandGen = false;
   bool HasMTE = false;
   bool HasTME = false;
 
   // Armv8.6-A Extensions
   bool HasBF16 = false;
   bool HasAMVS = false;
   bool HasFineGrainedTraps = false;
+  bool HasEnhancedCounterVirtualization = false;
 
   // Arm SVE2 extensions
   bool HasSVE2AES = false;
   bool HasSVE2SM4 = false;
   bool HasSVE2SHA3 = false;
   bool HasSVE2BitPerm = false;
 
   // Future architecture extensions.
public:
   bool hasSVE2AES() const { return HasSVE2AES; }
   bool hasSVE2SM4() const { return HasSVE2SM4; }
   bool hasSVE2SHA3() const { return HasSVE2SHA3; }
   bool hasSVE2BitPerm() const { return HasSVE2BitPerm; }
 
   // Armv8.6-A Extensions
   bool hasBF16() const { return HasBF16; }
   bool hasFineGrainedTraps() const { return HasFineGrainedTraps; }
+  bool hasEnhancedCounterVirtualization() const {
+    return HasEnhancedCounterVirtualization;
+  }
 
   bool isLittleEndian() const { return IsLittle; }
 
   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
   bool isTargetIOS() const { return TargetTriple.isiOS(); }
   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
   bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 let Requires = [{ {AArch64::FeatureFineGrainedTraps} }] in {
 def : RWSysReg<"HFGRTR_EL2",       0b11, 0b100, 0b0001, 0b0001, 0b100>;
 def : RWSysReg<"HFGWTR_EL2",       0b11, 0b100, 0b0001, 0b0001, 0b101>;
 def : RWSysReg<"HFGITR_EL2",       0b11, 0b100, 0b0001, 0b0001, 0b110>;
 def : RWSysReg<"HDFGRTR_EL2",      0b11, 0b100, 0b0011, 0b0001, 0b100>;
 def : RWSysReg<"HDFGWTR_EL2",      0b11, 0b100, 0b0011, 0b0001, 0b101>;
 }
 
+// v8.6a Enhanced Counter Virtualization
+//                                 Op0   Op1    CRn     CRm     Op2
+let Requires = [{ {AArch64::FeatureEnhancedCounterVirtualization} }] in {
+def : RWSysReg<"CNTSCALE_EL2",     0b11, 0b100, 0b1110, 0b0000, 0b100>;
+def : RWSysReg<"CNTISCALE_EL2",    0b11, 0b100, 0b1110, 0b0000, 0b101>;
+def : RWSysReg<"CNTPOFF_EL2",      0b11, 0b100, 0b1110, 0b0000, 0b110>;
+def : RWSysReg<"CNTVFRQ_EL2",      0b11, 0b100, 0b1110, 0b0000, 0b111>;
+def : RWSysReg<"CNTPCTSS_EL0",     0b11, 0b011, 0b1110, 0b0000, 0b101>;
+def : RWSysReg<"CNTVCTSS_EL0",     0b11, 0b011, 0b1110, 0b0000, 0b110>;
+}
+
 // Cyclone specific system registers
 //                                 Op0    Op1     CRn     CRm    Op2
 let Requires = [{ {AArch64::ProcAppleA7} }] in
 def : RWSysReg<"CPM_IOACC_CTL_EL3", 0b11, 0b111, 0b1111, 0b0010, 0b000>;

llvm/test/MC/AArch64/armv8.6a-ecv.s

+// RUN:     llvm-mc -triple aarch64 -show-encoding -mattr=+ecv   < %s | FileCheck %s
+// RUN:     llvm-mc -triple aarch64 -show-encoding -mattr=+v8.6a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding  < %s 2>&1         | FileCheck %s --check-prefix=NOECV
+
+msr CNTSCALE_EL2, x1
+msr CNTISCALE_EL2, x11
+msr CNTPOFF_EL2, x22
+msr CNTVFRQ_EL2, x3
+msr CNTPCTSS_EL0, x13
+msr CNTVCTSS_EL0, x23
+// CHECK: msr     CNTSCALE_EL2, x1        // encoding: [0x81,0xe0,0x1c,0xd5]
+// CHECK: msr     CNTISCALE_EL2, x11      // encoding: [0xab,0xe0,0x1c,0xd5]
+// CHECK: msr     CNTPOFF_EL2, x22        // encoding: [0xd6,0xe0,0x1c,0xd5]
+// CHECK: msr     CNTVFRQ_EL2, x3         // encoding: [0xe3,0xe0,0x1c,0xd5]
+// CHECK: msr     CNTPCTSS_EL0, x13       // encoding: [0xad,0xe0,0x1b,0xd5]
+// CHECK: msr     CNTVCTSS_EL0, x23       // encoding: [0xd7,0xe0,0x1b,0xd5]
+// NOECV :error: expected writable system register or pstate
+// NOECV: error: expected writable system register or pstate
+// NOECV: error: expected writable system register or pstate
+// NOECV: error: expected writable system register or pstate
+// NOECV: error: expected writable system register or pstate
+// NOECV: error: expected writable system register or pstate
+
+mrs x0, CNTSCALE_EL2
+mrs x5, CNTISCALE_EL2
+mrs x10, CNTPOFF_EL2
+mrs x15, CNTVFRQ_EL2
+mrs x20, CNTPCTSS_EL0
+mrs x30, CNTVCTSS_EL0
+// CHECK: mrs     x0, CNTSCALE_EL2        // encoding: [0x80,0xe0,0x3c,0xd5]
+// CHECK: mrs     x5, CNTISCALE_EL2       // encoding: [0xa5,0xe0,0x3c,0xd5]
+// CHECK: mrs     x10, CNTPOFF_EL2        // encoding: [0xca,0xe0,0x3c,0xd5]
+// CHECK: mrs     x15, CNTVFRQ_EL2        // encoding: [0xef,0xe0,0x3c,0xd5]
+// CHECK: mrs     x20, CNTPCTSS_EL0       // encoding: [0xb4,0xe0,0x3b,0xd5]
+// CHECK: mrs     x30, CNTVCTSS_EL0       // encoding: [0xde,0xe0,0x3b,0xd5]
+// NOECV: error: expected readable system register
+// NOECV: error: expected readable system register
+// NOECV: error: expected readable system register
+// NOECV: error: expected readable system register
+// NOECV: error: expected readable system register
+// NOECV: error: expected readable system register

llvm/test/MC/Disassembler/AArch64/armv8.6a-ecv.txt

+# RUN: llvm-mc -triple=aarch64  -mattr=+ecv -disassemble < %s      | FileCheck %s
+# RUN: llvm-mc -triple=aarch64              -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOFGT
+
+[0x81,0xe0,0x1c,0xd5]
+[0xab,0xe0,0x1c,0xd5]
+[0xd6,0xe0,0x1c,0xd5]
+[0xe3,0xe0,0x1c,0xd5]
+[0xad,0xe0,0x1b,0xd5]
+[0xd7,0xe0,0x1b,0xd5]
+# CHECK: msr CNTSCALE_EL2, x1
+# CHECK: msr CNTISCALE_EL2, x11
+# CHECK: msr CNTPOFF_EL2, x22
+# CHECK: msr CNTVFRQ_EL2, x3
+# CHECK: msr CNTPCTSS_EL0, x13
+# CHECK: msr CNTVCTSS_EL0, x23
+# NOFGT: msr S3_4_C14_C0_4, x1
+# NOFGT: msr S3_4_C14_C0_5, x11
+# NOFGT: msr S3_4_C14_C0_6, x22
+# NOFGT: msr S3_4_C14_C0_7, x3
+# NOFGT: msr S3_3_C14_C0_5, x13
+# NOFGT: msr S3_3_C14_C0_6, x23
+
+[0x80,0xe0,0x3c,0xd5]
+[0xa5,0xe0,0x3c,0xd5]
+[0xca,0xe0,0x3c,0xd5]
+[0xef,0xe0,0x3c,0xd5]
+[0xb4,0xe0,0x3b,0xd5]
+[0xde,0xe0,0x3b,0xd5]
+# CHECK: mrs x0, CNTSCALE_EL2
+# CHECK: mrs x5, CNTISCALE_EL2
+# CHECK: mrs x10, CNTPOFF_EL2
+# CHECK: mrs x15, CNTVFRQ_EL2
+# CHECK: mrs x20, CNTPCTSS_EL0
+# CHECK: mrs x30, CNTVCTSS_EL0
+# NOFGT: mrs x0, S3_4_C14_C0_4
+# NOFGT: mrs x5, S3_4_C14_C0_5
+# NOFGT: mrs x10, S3_4_C14_C0_6
+# NOFGT: mrs x15, S3_4_C14_C0_7
+# NOFGT: mrs x20, S3_3_C14_C0_5
+# NOFGT: mrs x30, S3_3_C14_C0_6