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Differential D76998

[ARM] add ARMv8.6-A Activity monitors virtualization extension
ClosedPublic

Authored by stuij on Mar 28 2020, 3:52 PM.

Details

Reviewers
t.p.northover
rengolin
SjoerdMeijer
ab
john.brawn
ostannard
Commits
rG59d10dc70335: [ARM] add ARMv8.6-A Activity monitors virtualization extension
Summary

This patch upstreams v8.6A activity monitors virtualization
assembler support, which consists of 32 new system
registers (two groups, each with 16 numbered registers).

See ARMv8.6-AMU in the Arm Architecture Reference Manual Armv8 for more
information.

Diff Detail

Event Timeline

stuij created this revision.Mar 28 2020, 3:52 PM
Herald added a project: Restricted Project. · View Herald TranscriptMar 28 2020, 3:52 PM
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls. · View Herald Transcript
stuij added a child revision: D76991: [ARM] Add ARMv8.6 Fine Grain Traps system registers.Mar 28 2020, 3:56 PM
Harbormaster failed remote builds in B50837: Diff 253383!Mar 28 2020, 5:12 PM
stuij added reviewers: t.p.northover, rengolin, SjoerdMeijer, ab, john.brawn.Mar 30 2020, 3:32 AM
SjoerdMeijer added inline comments.Mar 30 2020, 3:52 AM
llvm/test/MC/AArch64/armv8.6a-amvs-error.s
1 ↗(On Diff #253383)

I am unfamiliar with this: %p/armv8.6a-amvs.s , what is this doing?

ostannard added a subscriber: ostannard.Mar 30 2020, 5:27 AM
ostannard added inline comments.
llvm/test/MC/AArch64/armv8.6a-amvs-error.s
1 ↗(On Diff #253383)

%p expands to the test source directory, so this test is using the code from an adjacent file, with the filecheck lines from this file. I think it would be better (more obvious, idiomatic) to merge the two files together using different check prefixes for the positive and negative cases.

SjoerdMeijer added inline comments.Mar 30 2020, 6:00 AM
llvm/test/MC/AArch64/armv8.6a-amvs-error.s
1 ↗(On Diff #253383)

cheers, and +1 to that

stuij added a subscriber: dnsampaio.Mar 30 2020, 6:45 AM
stuij added a subscriber: LukeGeeson.Mar 30 2020, 2:56 PM
stuij updated this revision to Diff 253731.Mar 30 2020, 3:58 PM

As per review suggestion, merging tests from armv8.6a-amvs-error.s with armv8.6a-amvs.s.

Harbormaster completed remote builds in B51049: Diff 253731.Mar 30 2020, 4:57 PM
ostannard added inline comments.Mar 31 2020, 2:00 AM
llvm/test/MC/AArch64/armv8.6a-amvs.s
67

Run lines should all be grouped at the top of the file.

stuij updated this revision to Diff 253894.Mar 31 2020, 8:22 AM

rearranging lit test run lines as commented on by reviewer

stuij added a reviewer: ostannard.Mar 31 2020, 8:23 AM
ostannard accepted this revision.Mar 31 2020, 9:06 AM

LGTM

This revision is now accepted and ready to land.Mar 31 2020, 9:06 AM
Harbormaster completed remote builds in B51137: Diff 253894.Mar 31 2020, 9:22 AM
Closed by commit rG59d10dc70335: [ARM] add ARMv8.6-A Activity monitors virtualization extension (authored by Diogo Sampaio <diogo.sampaio@arm.com>, committed by stuij). · Explain WhyApr 5 2020, 5:51 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
7 lines
2 lines
14 lines
test/
MC/
AArch64/
327 lines
Disassembler/
AArch64/
197 lines

Diff 255145

llvm/lib/Target/AArch64/AArch64.td

Show First 20 Lines • Show All 275 Lines • ▼ Show 20 Lines
def FeatureTRACEV8_4 : SubtargetFeature< def FeatureTRACEV8_4 : SubtargetFeature<
"tracev8.4", "HasTRACEV8_4", "true", "tracev8.4", "HasTRACEV8_4", "true",
"Enable v8.4-A Trace extension">; "Enable v8.4-A Trace extension">;
def FeatureAM : SubtargetFeature< def FeatureAM : SubtargetFeature<
"am", "HasAM", "true", "am", "HasAM", "true",
"Enable v8.4-A Activity Monitors extension">; "Enable v8.4-A Activity Monitors extension">;
def FeatureAMVS : SubtargetFeature<
"amvs", "HasAMVS", "true",
"Enable v8.6-A Activity Monitors Virtualization support",
[FeatureAM]>;
def FeatureSEL2 : SubtargetFeature< def FeatureSEL2 : SubtargetFeature<
"sel2", "HasSEL2", "true", "sel2", "HasSEL2", "true",
"Enable v8.4-A Secure Exception Level 2 extension">; "Enable v8.4-A Secure Exception Level 2 extension">;
def FeaturePMU : SubtargetFeature< def FeaturePMU : SubtargetFeature<
"pmu", "HasPMU", "true", "pmu", "HasPMU", "true",
"Enable v8.4-A PMU extension">; "Enable v8.4-A PMU extension">;
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
def HasV8_5aOps : SubtargetFeature< def HasV8_5aOps : SubtargetFeature<
"v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
[HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict, [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist, FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
FeatureBranchTargetId]>; FeatureBranchTargetId]>;
def HasV8_6aOps : SubtargetFeature< def HasV8_6aOps : SubtargetFeature<
"v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions", "v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",
[HasV8_5aOps, FeatureBF16]>; [HasV8_5aOps, FeatureAMVS, FeatureBF16]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Register File Description // Register File Description
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
include "AArch64RegisterInfo.td" include "AArch64RegisterInfo.td"
include "AArch64RegisterBanks.td" include "AArch64RegisterBanks.td"
include "AArch64CallingConvention.td" include "AArch64CallingConvention.td"
▲ Show 20 Lines • Show All 570 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64Subtarget.h

Show First 20 Lines • Show All 141 Lines • ▼ Show 20 Linesprotected:
bool HasCCDP = false; bool HasCCDP = false;
bool HasBTI = false; bool HasBTI = false;
bool HasRandGen = false; bool HasRandGen = false;
bool HasMTE = false; bool HasMTE = false;
bool HasTME = false; bool HasTME = false;
// Armv8.6-A Extensions // Armv8.6-A Extensions
bool HasBF16 = false; bool HasBF16 = false;
bool HasAMVS = false;
// Arm SVE2 extensions // Arm SVE2 extensions
bool HasSVE2AES = false; bool HasSVE2AES = false;
bool HasSVE2SM4 = false; bool HasSVE2SM4 = false;
bool HasSVE2SHA3 = false; bool HasSVE2SHA3 = false;
bool HasSVE2BitPerm = false; bool HasSVE2BitPerm = false;
// Future architecture extensions. // Future architecture extensions.
▲ Show 20 Lines • Show All 288 Lines • ▼ Show 20 Linespublic:
bool hasComplxNum() const { return HasComplxNum; } bool hasComplxNum() const { return HasComplxNum; }
bool hasNV() const { return HasNV; } bool hasNV() const { return HasNV; }
bool hasRASv8_4() const { return HasRASv8_4; } bool hasRASv8_4() const { return HasRASv8_4; }
bool hasMPAM() const { return HasMPAM; } bool hasMPAM() const { return HasMPAM; }
bool hasDIT() const { return HasDIT; } bool hasDIT() const { return HasDIT; }
bool hasTRACEV8_4() const { return HasTRACEV8_4; } bool hasTRACEV8_4() const { return HasTRACEV8_4; }
bool hasAM() const { return HasAM; } bool hasAM() const { return HasAM; }
bool hasAMVS() const { return HasAMVS; }
bool hasSEL2() const { return HasSEL2; } bool hasSEL2() const { return HasSEL2; }
bool hasPMU() const { return HasPMU; } bool hasPMU() const { return HasPMU; }
bool hasTLB_RMI() const { return HasTLB_RMI; } bool hasTLB_RMI() const { return HasTLB_RMI; }
bool hasFMI() const { return HasFMI; } bool hasFMI() const { return HasFMI; }
bool hasRCPC_IMMO() const { return HasRCPC_IMMO; } bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
bool addrSinkUsingGEPs() const override { bool addrSinkUsingGEPs() const override {
// Keeping GEPs inbounds is important for exploiting AArch64 // Keeping GEPs inbounds is important for exploiting AArch64
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64SystemOperands.td

Show First 20 Lines • Show All 1,482 Lines • ▼ Show 20 Lines
def : RWSysReg<"TRBPTR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b001>; def : RWSysReg<"TRBPTR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b001>;
def : RWSysReg<"TRBBASER_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b010>; def : RWSysReg<"TRBBASER_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b010>;
def : RWSysReg<"TRBSR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b011>; def : RWSysReg<"TRBSR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b011>;
def : RWSysReg<"TRBMAR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b100>; def : RWSysReg<"TRBMAR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b100>;
def : RWSysReg<"TRBTRG_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b110>; def : RWSysReg<"TRBTRG_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b110>;
def : ROSysReg<"TRBIDR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b111>; def : ROSysReg<"TRBIDR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b111>;
} // FeatureTRBE } // FeatureTRBE
// v8.6a Activity Monitors Virtualization Support
let Requires = [{ {AArch64::FeatureAMVS} }] in {
foreach n = 0-15 in {
foreach x = 0-1 in {
def : RWSysReg<"AMEVCNTVOFF"#x#n#"_EL2",
0b11, 0b100, 0b1101, 0b1000, 0b000>{
let Encoding{4} = x;
let Encoding{3-0} = n;
}
}
}
}
// Cyclone specific system registers // Cyclone specific system registers
// Op0 Op1 CRn CRm Op2 // Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::ProcAppleA7} }] in let Requires = [{ {AArch64::ProcAppleA7} }] in
def : RWSysReg<"CPM_IOACC_CTL_EL3", 0b11, 0b111, 0b1111, 0b0010, 0b000>; def : RWSysReg<"CPM_IOACC_CTL_EL3", 0b11, 0b111, 0b1111, 0b0010, 0b000>;

llvm/test/MC/AArch64/armv8.6a-amvs.s

  • This file was added.
// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+amvs -o - %s | FileCheck %s
// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.6a -o - %s | FileCheck %s
// RUN: not llvm-mc -triple aarch64 -show-encoding -o - %p/armv8.6a-amvs.s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
msr AMEVCNTVOFF00_EL2, x0
msr AMEVCNTVOFF01_EL2, x0
msr AMEVCNTVOFF02_EL2, x0
msr AMEVCNTVOFF03_EL2, x0
msr AMEVCNTVOFF04_EL2, x0
msr AMEVCNTVOFF05_EL2, x0
msr AMEVCNTVOFF06_EL2, x0
msr AMEVCNTVOFF07_EL2, x0
msr AMEVCNTVOFF08_EL2, x0
msr AMEVCNTVOFF09_EL2, x0
msr AMEVCNTVOFF010_EL2, x0
msr AMEVCNTVOFF011_EL2, x0
msr AMEVCNTVOFF012_EL2, x0
msr AMEVCNTVOFF013_EL2, x0
msr AMEVCNTVOFF014_EL2, x0
msr AMEVCNTVOFF015_EL2, x0
mrs x0, AMEVCNTVOFF00_EL2
mrs x0, AMEVCNTVOFF01_EL2
mrs x0, AMEVCNTVOFF02_EL2
mrs x0, AMEVCNTVOFF03_EL2
mrs x0, AMEVCNTVOFF04_EL2
mrs x0, AMEVCNTVOFF05_EL2
mrs x0, AMEVCNTVOFF06_EL2
mrs x0, AMEVCNTVOFF07_EL2
mrs x0, AMEVCNTVOFF08_EL2
mrs x0, AMEVCNTVOFF09_EL2
mrs x0, AMEVCNTVOFF010_EL2
mrs x0, AMEVCNTVOFF011_EL2
mrs x0, AMEVCNTVOFF012_EL2
mrs x0, AMEVCNTVOFF013_EL2
mrs x0, AMEVCNTVOFF014_EL2
mrs x0, AMEVCNTVOFF015_EL2
msr AMEVCNTVOFF10_EL2, x0
msr AMEVCNTVOFF11_EL2, x0
msr AMEVCNTVOFF12_EL2, x0
msr AMEVCNTVOFF13_EL2, x0
msr AMEVCNTVOFF14_EL2, x0
msr AMEVCNTVOFF15_EL2, x0
msr AMEVCNTVOFF16_EL2, x0
msr AMEVCNTVOFF17_EL2, x0
msr AMEVCNTVOFF18_EL2, x0
msr AMEVCNTVOFF19_EL2, x0
msr AMEVCNTVOFF110_EL2, x0
msr AMEVCNTVOFF111_EL2, x0
msr AMEVCNTVOFF112_EL2, x0
msr AMEVCNTVOFF113_EL2, x0
msr AMEVCNTVOFF114_EL2, x0
msr AMEVCNTVOFF115_EL2, x0
mrs x0, AMEVCNTVOFF10_EL2
mrs x0, AMEVCNTVOFF11_EL2
mrs x0, AMEVCNTVOFF12_EL2
mrs x0, AMEVCNTVOFF13_EL2
mrs x0, AMEVCNTVOFF14_EL2
mrs x0, AMEVCNTVOFF15_EL2
mrs x0, AMEVCNTVOFF16_EL2
mrs x0, AMEVCNTVOFF17_EL2
mrs x0, AMEVCNTVOFF18_EL2
mrs x0, AMEVCNTVOFF19_EL2
mrs x0, AMEVCNTVOFF110_EL2
mrs x0, AMEVCNTVOFF111_EL2
mrs x0, AMEVCNTVOFF112_EL2
mrs x0, AMEVCNTVOFF113_EL2
mrs x0, AMEVCNTVOFF114_EL2
mrs x0, AMEVCNTVOFF115_EL2
ostannardUnsubmitted
Not Done
ReplyInline Actions

Run lines should all be grouped at the top of the file.

ostannard: Run lines should all be grouped at the top of the file.
// CHECK: .text
// CHECK-NEXT: msr AMEVCNTVOFF00_EL2, x0 // encoding: [0x00,0xd8,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF01_EL2, x0 // encoding: [0x20,0xd8,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF02_EL2, x0 // encoding: [0x40,0xd8,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF03_EL2, x0 // encoding: [0x60,0xd8,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF04_EL2, x0 // encoding: [0x80,0xd8,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF05_EL2, x0 // encoding: [0xa0,0xd8,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF06_EL2, x0 // encoding: [0xc0,0xd8,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF07_EL2, x0 // encoding: [0xe0,0xd8,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF08_EL2, x0 // encoding: [0x00,0xd9,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF09_EL2, x0 // encoding: [0x20,0xd9,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF010_EL2, x0 // encoding: [0x40,0xd9,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF011_EL2, x0 // encoding: [0x60,0xd9,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF012_EL2, x0 // encoding: [0x80,0xd9,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF013_EL2, x0 // encoding: [0xa0,0xd9,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF014_EL2, x0 // encoding: [0xc0,0xd9,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF015_EL2, x0 // encoding: [0xe0,0xd9,0x1c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF00_EL2 // encoding: [0x00,0xd8,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF01_EL2 // encoding: [0x20,0xd8,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF02_EL2 // encoding: [0x40,0xd8,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF03_EL2 // encoding: [0x60,0xd8,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF04_EL2 // encoding: [0x80,0xd8,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF05_EL2 // encoding: [0xa0,0xd8,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF06_EL2 // encoding: [0xc0,0xd8,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF07_EL2 // encoding: [0xe0,0xd8,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF08_EL2 // encoding: [0x00,0xd9,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF09_EL2 // encoding: [0x20,0xd9,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF010_EL2 // encoding: [0x40,0xd9,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF011_EL2 // encoding: [0x60,0xd9,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF012_EL2 // encoding: [0x80,0xd9,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF013_EL2 // encoding: [0xa0,0xd9,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF014_EL2 // encoding: [0xc0,0xd9,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF015_EL2 // encoding: [0xe0,0xd9,0x3c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF10_EL2, x0 // encoding: [0x00,0xda,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF11_EL2, x0 // encoding: [0x20,0xda,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF12_EL2, x0 // encoding: [0x40,0xda,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF13_EL2, x0 // encoding: [0x60,0xda,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF14_EL2, x0 // encoding: [0x80,0xda,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF15_EL2, x0 // encoding: [0xa0,0xda,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF16_EL2, x0 // encoding: [0xc0,0xda,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF17_EL2, x0 // encoding: [0xe0,0xda,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF18_EL2, x0 // encoding: [0x00,0xdb,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF19_EL2, x0 // encoding: [0x20,0xdb,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF110_EL2, x0 // encoding: [0x40,0xdb,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF111_EL2, x0 // encoding: [0x60,0xdb,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF112_EL2, x0 // encoding: [0x80,0xdb,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF113_EL2, x0 // encoding: [0xa0,0xdb,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF114_EL2, x0 // encoding: [0xc0,0xdb,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF115_EL2, x0 // encoding: [0xe0,0xdb,0x1c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF10_EL2 // encoding: [0x00,0xda,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF11_EL2 // encoding: [0x20,0xda,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF12_EL2 // encoding: [0x40,0xda,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF13_EL2 // encoding: [0x60,0xda,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF14_EL2 // encoding: [0x80,0xda,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF15_EL2 // encoding: [0xa0,0xda,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF16_EL2 // encoding: [0xc0,0xda,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF17_EL2 // encoding: [0xe0,0xda,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF18_EL2 // encoding: [0x00,0xdb,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF19_EL2 // encoding: [0x20,0xdb,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF110_EL2 // encoding: [0x40,0xdb,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF111_EL2 // encoding: [0x60,0xdb,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF112_EL2 // encoding: [0x80,0xdb,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF113_EL2 // encoding: [0xa0,0xdb,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF114_EL2 // encoding: [0xc0,0xdb,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF115_EL2 // encoding: [0xe0,0xdb,0x3c,0xd5]
// CHECK-ERROR: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF00_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF01_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF02_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF03_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF04_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF05_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF06_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF07_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF08_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF09_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF010_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF011_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF012_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF013_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF014_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF015_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF00_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF01_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF02_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF03_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF04_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF05_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF06_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF07_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF08_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF09_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF010_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF011_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF012_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF013_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF014_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF015_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF10_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF11_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF12_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF13_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF14_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF15_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF16_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF17_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF18_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF19_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF110_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF111_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF112_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF113_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF114_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr AMEVCNTVOFF115_EL2, x0
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF10_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF11_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF12_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF13_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF14_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF15_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF16_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF17_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF18_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF19_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF110_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF111_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF112_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF113_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF114_EL2
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected readable system register
// CHECK-ERROR-NEXT: mrs x0, AMEVCNTVOFF115_EL2
// CHECK-ERROR-NEXT: ^

llvm/test/MC/Disassembler/AArch64/armv8.6a-amvs.s

  • This file was added.
// RUN: llvm-mc -triple aarch64 -show-encoding -disassemble -mattr=+amvs %s | FileCheck %s
// RUN: llvm-mc -triple aarch64 -show-encoding -disassemble -mattr=+v8.6a -o - %s | FileCheck %s
// RUN: llvm-mc -triple aarch64 -show-encoding -disassemble -o - %s | FileCheck --check-prefix=NOAMVS %s
[0x00,0xd8,0x1c,0xd5]
[0x20,0xd8,0x1c,0xd5]
[0x40,0xd8,0x1c,0xd5]
[0x60,0xd8,0x1c,0xd5]
[0x80,0xd8,0x1c,0xd5]
[0xa0,0xd8,0x1c,0xd5]
[0xc0,0xd8,0x1c,0xd5]
[0xe0,0xd8,0x1c,0xd5]
[0x00,0xd9,0x1c,0xd5]
[0x20,0xd9,0x1c,0xd5]
[0x40,0xd9,0x1c,0xd5]
[0x60,0xd9,0x1c,0xd5]
[0x80,0xd9,0x1c,0xd5]
[0xa0,0xd9,0x1c,0xd5]
[0xc0,0xd9,0x1c,0xd5]
[0xe0,0xd9,0x1c,0xd5]
[0x00,0xd8,0x3c,0xd5]
[0x20,0xd8,0x3c,0xd5]
[0x40,0xd8,0x3c,0xd5]
[0x60,0xd8,0x3c,0xd5]
[0x80,0xd8,0x3c,0xd5]
[0xa0,0xd8,0x3c,0xd5]
[0xc0,0xd8,0x3c,0xd5]
[0xe0,0xd8,0x3c,0xd5]
[0x00,0xd9,0x3c,0xd5]
[0x20,0xd9,0x3c,0xd5]
[0x40,0xd9,0x3c,0xd5]
[0x60,0xd9,0x3c,0xd5]
[0x80,0xd9,0x3c,0xd5]
[0xa0,0xd9,0x3c,0xd5]
[0xc0,0xd9,0x3c,0xd5]
[0xe0,0xd9,0x3c,0xd5]
[0x00,0xda,0x1c,0xd5]
[0x20,0xda,0x1c,0xd5]
[0x40,0xda,0x1c,0xd5]
[0x60,0xda,0x1c,0xd5]
[0x80,0xda,0x1c,0xd5]
[0xa0,0xda,0x1c,0xd5]
[0xc0,0xda,0x1c,0xd5]
[0xe0,0xda,0x1c,0xd5]
[0x00,0xdb,0x1c,0xd5]
[0x20,0xdb,0x1c,0xd5]
[0x40,0xdb,0x1c,0xd5]
[0x60,0xdb,0x1c,0xd5]
[0x80,0xdb,0x1c,0xd5]
[0xa0,0xdb,0x1c,0xd5]
[0xc0,0xdb,0x1c,0xd5]
[0xe0,0xdb,0x1c,0xd5]
[0x00,0xda,0x3c,0xd5]
[0x20,0xda,0x3c,0xd5]
[0x40,0xda,0x3c,0xd5]
[0x60,0xda,0x3c,0xd5]
[0x80,0xda,0x3c,0xd5]
[0xa0,0xda,0x3c,0xd5]
[0xc0,0xda,0x3c,0xd5]
[0xe0,0xda,0x3c,0xd5]
[0x00,0xdb,0x3c,0xd5]
[0x20,0xdb,0x3c,0xd5]
[0x40,0xdb,0x3c,0xd5]
[0x60,0xdb,0x3c,0xd5]
[0x80,0xdb,0x3c,0xd5]
[0xa0,0xdb,0x3c,0xd5]
[0xc0,0xdb,0x3c,0xd5]
[0xe0,0xdb,0x3c,0xd5]
// CHECK: .text
// CHECK-NEXT: msr AMEVCNTVOFF00_EL2, x0 // encoding: [0x00,0xd8,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF01_EL2, x0 // encoding: [0x20,0xd8,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF02_EL2, x0 // encoding: [0x40,0xd8,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF03_EL2, x0 // encoding: [0x60,0xd8,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF04_EL2, x0 // encoding: [0x80,0xd8,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF05_EL2, x0 // encoding: [0xa0,0xd8,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF06_EL2, x0 // encoding: [0xc0,0xd8,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF07_EL2, x0 // encoding: [0xe0,0xd8,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF08_EL2, x0 // encoding: [0x00,0xd9,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF09_EL2, x0 // encoding: [0x20,0xd9,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF010_EL2, x0 // encoding: [0x40,0xd9,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF011_EL2, x0 // encoding: [0x60,0xd9,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF012_EL2, x0 // encoding: [0x80,0xd9,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF013_EL2, x0 // encoding: [0xa0,0xd9,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF014_EL2, x0 // encoding: [0xc0,0xd9,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF015_EL2, x0 // encoding: [0xe0,0xd9,0x1c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF00_EL2 // encoding: [0x00,0xd8,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF01_EL2 // encoding: [0x20,0xd8,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF02_EL2 // encoding: [0x40,0xd8,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF03_EL2 // encoding: [0x60,0xd8,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF04_EL2 // encoding: [0x80,0xd8,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF05_EL2 // encoding: [0xa0,0xd8,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF06_EL2 // encoding: [0xc0,0xd8,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF07_EL2 // encoding: [0xe0,0xd8,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF08_EL2 // encoding: [0x00,0xd9,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF09_EL2 // encoding: [0x20,0xd9,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF010_EL2 // encoding: [0x40,0xd9,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF011_EL2 // encoding: [0x60,0xd9,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF012_EL2 // encoding: [0x80,0xd9,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF013_EL2 // encoding: [0xa0,0xd9,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF014_EL2 // encoding: [0xc0,0xd9,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF015_EL2 // encoding: [0xe0,0xd9,0x3c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF10_EL2, x0 // encoding: [0x00,0xda,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF11_EL2, x0 // encoding: [0x20,0xda,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF12_EL2, x0 // encoding: [0x40,0xda,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF13_EL2, x0 // encoding: [0x60,0xda,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF14_EL2, x0 // encoding: [0x80,0xda,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF15_EL2, x0 // encoding: [0xa0,0xda,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF16_EL2, x0 // encoding: [0xc0,0xda,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF17_EL2, x0 // encoding: [0xe0,0xda,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF18_EL2, x0 // encoding: [0x00,0xdb,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF19_EL2, x0 // encoding: [0x20,0xdb,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF110_EL2, x0 // encoding: [0x40,0xdb,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF111_EL2, x0 // encoding: [0x60,0xdb,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF112_EL2, x0 // encoding: [0x80,0xdb,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF113_EL2, x0 // encoding: [0xa0,0xdb,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF114_EL2, x0 // encoding: [0xc0,0xdb,0x1c,0xd5]
// CHECK-NEXT: msr AMEVCNTVOFF115_EL2, x0 // encoding: [0xe0,0xdb,0x1c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF10_EL2 // encoding: [0x00,0xda,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF11_EL2 // encoding: [0x20,0xda,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF12_EL2 // encoding: [0x40,0xda,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF13_EL2 // encoding: [0x60,0xda,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF14_EL2 // encoding: [0x80,0xda,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF15_EL2 // encoding: [0xa0,0xda,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF16_EL2 // encoding: [0xc0,0xda,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF17_EL2 // encoding: [0xe0,0xda,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF18_EL2 // encoding: [0x00,0xdb,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF19_EL2 // encoding: [0x20,0xdb,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF110_EL2 // encoding: [0x40,0xdb,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF111_EL2 // encoding: [0x60,0xdb,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF112_EL2 // encoding: [0x80,0xdb,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF113_EL2 // encoding: [0xa0,0xdb,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF114_EL2 // encoding: [0xc0,0xdb,0x3c,0xd5]
// CHECK-NEXT: mrs x0, AMEVCNTVOFF115_EL2 // encoding: [0xe0,0xdb,0x3c,0xd5]
// NOAMVS: .text
// NOAMVS-NEXT: msr S3_4_C13_C8_0, x0 // encoding: [0x00,0xd8,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C8_1, x0 // encoding: [0x20,0xd8,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C8_2, x0 // encoding: [0x40,0xd8,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C8_3, x0 // encoding: [0x60,0xd8,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C8_4, x0 // encoding: [0x80,0xd8,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C8_5, x0 // encoding: [0xa0,0xd8,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C8_6, x0 // encoding: [0xc0,0xd8,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C8_7, x0 // encoding: [0xe0,0xd8,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C9_0, x0 // encoding: [0x00,0xd9,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C9_1, x0 // encoding: [0x20,0xd9,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C9_2, x0 // encoding: [0x40,0xd9,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C9_3, x0 // encoding: [0x60,0xd9,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C9_4, x0 // encoding: [0x80,0xd9,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C9_5, x0 // encoding: [0xa0,0xd9,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C9_6, x0 // encoding: [0xc0,0xd9,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C9_7, x0 // encoding: [0xe0,0xd9,0x1c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C8_0 // encoding: [0x00,0xd8,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C8_1 // encoding: [0x20,0xd8,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C8_2 // encoding: [0x40,0xd8,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C8_3 // encoding: [0x60,0xd8,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C8_4 // encoding: [0x80,0xd8,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C8_5 // encoding: [0xa0,0xd8,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C8_6 // encoding: [0xc0,0xd8,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C8_7 // encoding: [0xe0,0xd8,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C9_0 // encoding: [0x00,0xd9,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C9_1 // encoding: [0x20,0xd9,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C9_2 // encoding: [0x40,0xd9,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C9_3 // encoding: [0x60,0xd9,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C9_4 // encoding: [0x80,0xd9,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C9_5 // encoding: [0xa0,0xd9,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C9_6 // encoding: [0xc0,0xd9,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C9_7 // encoding: [0xe0,0xd9,0x3c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C10_0, x0 // encoding: [0x00,0xda,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C10_1, x0 // encoding: [0x20,0xda,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C10_2, x0 // encoding: [0x40,0xda,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C10_3, x0 // encoding: [0x60,0xda,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C10_4, x0 // encoding: [0x80,0xda,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C10_5, x0 // encoding: [0xa0,0xda,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C10_6, x0 // encoding: [0xc0,0xda,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C10_7, x0 // encoding: [0xe0,0xda,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C11_0, x0 // encoding: [0x00,0xdb,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C11_1, x0 // encoding: [0x20,0xdb,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C11_2, x0 // encoding: [0x40,0xdb,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C11_3, x0 // encoding: [0x60,0xdb,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C11_4, x0 // encoding: [0x80,0xdb,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C11_5, x0 // encoding: [0xa0,0xdb,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C11_6, x0 // encoding: [0xc0,0xdb,0x1c,0xd5]
// NOAMVS-NEXT: msr S3_4_C13_C11_7, x0 // encoding: [0xe0,0xdb,0x1c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C10_0 // encoding: [0x00,0xda,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C10_1 // encoding: [0x20,0xda,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C10_2 // encoding: [0x40,0xda,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C10_3 // encoding: [0x60,0xda,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C10_4 // encoding: [0x80,0xda,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C10_5 // encoding: [0xa0,0xda,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C10_6 // encoding: [0xc0,0xda,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C10_7 // encoding: [0xe0,0xda,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C11_0 // encoding: [0x00,0xdb,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C11_1 // encoding: [0x20,0xdb,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C11_2 // encoding: [0x40,0xdb,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C11_3 // encoding: [0x60,0xdb,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C11_4 // encoding: [0x80,0xdb,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C11_5 // encoding: [0xa0,0xdb,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C11_6 // encoding: [0xc0,0xdb,0x3c,0xd5]
// NOAMVS-NEXT: mrs x0, S3_4_C13_C11_7 // encoding: [0xe0,0xdb,0x3c,0xd5]