olista01 (Oliver Stannard)
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User Since
Feb 5 2014, 1:36 AM (228 w, 1 d)

Recent Activity

Today

olista01 added a comment to D48437: [ARM] Cortex-M0 strict align target feature.

This restriction is in the Armv6M architecture, so I think this should be done in ARMv6m, so it also applies to cortex-m1 and sc000, and I think this also applies to ARMv8mBaseline.

Thu, Jun 21, 8:37 AM

Tue, Jun 5

olista01 added a comment to D47711: [AArch64][SVE] Asm: Add parsing/printing support for exact FP immediates..

It looks like we currently have two ways in which floating-point operands can get parsed, and this patch adds a third, which accepts values which overlap with both of the existing ones. Instead, this seems like a good time to tidy this up, always parsing to the same AArch64Operand, and using predicate functions to check if the value is valid for each operand type, as we do for integer operands with different ranges.

Tue, Jun 5, 7:36 AM

Apr 27 2018

olista01 committed rL331039: [ARM,AArch64] Add intrinsics for dot product instructions.
[ARM,AArch64] Add intrinsics for dot product instructions
Apr 27 2018, 7:09 AM
olista01 committed rC331039: [ARM,AArch64] Add intrinsics for dot product instructions.
[ARM,AArch64] Add intrinsics for dot product instructions
Apr 27 2018, 7:09 AM
olista01 closed D46109: [ARM,AArch64] Add intrinsics for dot product instructions.
Apr 27 2018, 7:09 AM
olista01 added inline comments to D46109: [ARM,AArch64] Add intrinsics for dot product instructions.
Apr 27 2018, 7:05 AM
olista01 committed rL331038: [ARM] Add __ARM_FEATURE_DOTPROD pre-defined macro.
[ARM] Add __ARM_FEATURE_DOTPROD pre-defined macro
Apr 27 2018, 6:59 AM
olista01 committed rC331038: [ARM] Add __ARM_FEATURE_DOTPROD pre-defined macro.
[ARM] Add __ARM_FEATURE_DOTPROD pre-defined macro
Apr 27 2018, 6:59 AM
olista01 closed D46108: [ARM] Add __ARM_FEATURE_DOTPROD pre-defined macro.
Apr 27 2018, 6:59 AM
olista01 committed rL331036: [AArch64] Codegen for v8.2A dot product intrinsics.
[AArch64] Codegen for v8.2A dot product intrinsics
Apr 27 2018, 6:49 AM
olista01 committed rL331032: [ARM] Codegen for v8.2A dot product intrinsics.
[ARM] Codegen for v8.2A dot product intrinsics
Apr 27 2018, 5:54 AM
olista01 closed D46106: [ARM] Codegen for v8.2A dot product intrinsics.
Apr 27 2018, 5:54 AM

Apr 26 2018

olista01 created D46109: [ARM,AArch64] Add intrinsics for dot product instructions.
Apr 26 2018, 2:30 AM
olista01 created D46108: [ARM] Add __ARM_FEATURE_DOTPROD pre-defined macro.
Apr 26 2018, 2:27 AM
olista01 created D46107: [AArch64] Codegen for v8.2A dot product intrinsics.
Apr 26 2018, 2:25 AM
olista01 created D46106: [ARM] Codegen for v8.2A dot product intrinsics.
Apr 26 2018, 2:24 AM

Apr 25 2018

olista01 accepted D45879: [AsmMatcher] Extend PredicateMethod with optional DiagnosticPredicate.

LGTM

Apr 25 2018, 7:58 AM

Apr 11 2018

olista01 accepted D45205: [ARM] FP16 VSEL codegen follow up.

LGTM, thanks.

Apr 11 2018, 2:16 AM

Apr 5 2018

olista01 added inline comments to D45205: [ARM] FP16 VSEL codegen follow up.
Apr 5 2018, 10:08 AM

Apr 3 2018

olista01 added a comment to D45205: [ARM] FP16 VSEL codegen follow up.

This patch now changes 4 DAG nodes, but doesn't touch any tests for most of them. Are these changes NFC, and properly tested elsewhere? If not, this needs more tests.

Apr 3 2018, 10:32 AM
olista01 added inline comments to D45205: [ARM] FP16 VSEL codegen follow up.
Apr 3 2018, 5:59 AM

Mar 6 2018

olista01 committed rL326810: [Asm] Fix another layering violation in assmebly macro dumping.
[Asm] Fix another layering violation in assmebly macro dumping
Mar 6 2018, 8:55 AM
olista01 committed rL326804: [ARM][Asm] Fix layering violation introduced by r326795.
[ARM][Asm] Fix layering violation introduced by r326795
Mar 6 2018, 7:35 AM
olista01 committed rL326795: [Asm] Add debug printing for assembler macros.
[Asm] Add debug printing for assembler macros
Mar 6 2018, 6:10 AM
olista01 closed D43937: [Asm] Add debug printing for assembler macros.
Mar 6 2018, 6:10 AM
olista01 committed rL326794: [Asm] Refactor debug printing of AsmToken.
[Asm] Refactor debug printing of AsmToken
Mar 6 2018, 6:05 AM
olista01 closed D43936: [Asm] Refactor debug printing of AsmToken.
Mar 6 2018, 6:05 AM
olista01 added inline comments to D43936: [Asm] Refactor debug printing of AsmToken.
Mar 6 2018, 5:48 AM

Mar 5 2018

olista01 committed rL326696: [ARM][Asm] VMOVSRR and VMOVRRS need sequential S registers.
[ARM][Asm] VMOVSRR and VMOVRRS need sequential S registers
Mar 5 2018, 5:30 AM
olista01 closed D44084: [ARM][Asm] VMOVSRR and VMOVRRS need sequential S registers.
Mar 5 2018, 5:29 AM
olista01 created D44084: [ARM][Asm] VMOVSRR and VMOVRRS need sequential S registers.
Mar 5 2018, 3:01 AM

Mar 1 2018

olista01 added a dependency for D43937: [Asm] Add debug printing for assembler macros: D43936: [Asm] Refactor debug printing of AsmToken.
Mar 1 2018, 3:47 AM
olista01 added a dependent revision for D43936: [Asm] Refactor debug printing of AsmToken: D43937: [Asm] Add debug printing for assembler macros.
Mar 1 2018, 3:47 AM
olista01 created D43937: [Asm] Add debug printing for assembler macros.
Mar 1 2018, 3:47 AM
olista01 created D43936: [Asm] Refactor debug printing of AsmToken.
Mar 1 2018, 3:45 AM

Feb 27 2018

olista01 accepted D43807: ARM: Don't rewrite add reg, $sp, 0 -> mov reg, $sp if the add defines CPSR..

LGTM, thanks.

Feb 27 2018, 4:14 AM
olista01 accepted D43777: [ARM] Another f16 litpool fix.

LGTM.

Feb 27 2018, 3:05 AM

Feb 21 2018

olista01 accepted D43580: [ARM] FP16 constant pool fix.

LGTM, but please wait a day to let other time-zones comment.

Feb 21 2018, 9:44 AM

Feb 16 2018

olista01 added a comment to D43374: [ARM]Decoding MSR with unpredictable destination register causes an assert.

Hi Simi,

Feb 16 2018, 2:01 AM

Feb 14 2018

olista01 accepted D43018: Move llvm::computeLoopSafetyInfo from LICM.cpp to LoopUtils.cpp. NFC.

LGTM

Feb 14 2018, 9:21 AM
olista01 added inline comments to D43291: [ARM] f16 vcmp fixes.
Feb 14 2018, 8:53 AM
olista01 accepted D43280: [ARM] f16 stack spill/reloads.

LGTM, thanks

Feb 14 2018, 7:07 AM
olista01 added a comment to D43280: [ARM] f16 stack spill/reloads.

The test case doesn't have to be exactly the -O0 output from clang, you should reduce it to clear IR which triggers the bug. To start with, are all of those allocas and memcpy calls required?

Feb 14 2018, 6:32 AM
olista01 added inline comments to D43280: [ARM] f16 stack spill/reloads.
Feb 14 2018, 6:21 AM

Feb 13 2018

olista01 accepted D42784: [ARM] Allow Half types in ConstantPool.

LGTM, thanks

Feb 13 2018, 7:30 AM
olista01 accepted D43179: [Thumb] Handle addressing mode AddrMode5FP16.

LGTM, thanks

Feb 13 2018, 1:56 AM

Feb 12 2018

olista01 added inline comments to D42784: [ARM] Allow Half types in ConstantPool.
Feb 12 2018, 9:58 AM
olista01 added inline comments to D43179: [Thumb] Handle addressing mode AddrMode5FP16.
Feb 12 2018, 9:53 AM
olista01 committed rL324908: [AArch64] Improve v8.1-A code-gen for atomic load-and.
[AArch64] Improve v8.1-A code-gen for atomic load-and
Feb 12 2018, 9:06 AM
olista01 closed D42478: [AArch64] Improve v8.1-A code-gen for atomic load-and.
Feb 12 2018, 9:05 AM
olista01 committed rL324892: [AArch64] Improve v8.1-A code-gen for atomic load-subtract.
[AArch64] Improve v8.1-A code-gen for atomic load-subtract
Feb 12 2018, 6:24 AM
olista01 closed D42477: [AArch64] Improve v8.1-A code-gen for atomic load-subtract.
Feb 12 2018, 6:23 AM
olista01 added a comment to D43125: [ARM] Don't print "Requires NEON" error message for M-profile.

To have a better handling than this, we'd have to error out earlier saying M-class doesn't have NEON, which probably needs more knowledge than that piece of code has...

Feb 12 2018, 5:13 AM
olista01 added a comment to D42477: [AArch64] Improve v8.1-A code-gen for atomic load-subtract.

Geoff Berry suggested to do this in DAG Combine

Feb 12 2018, 5:08 AM
olista01 added a comment to D42477: [AArch64] Improve v8.1-A code-gen for atomic load-subtract.

Ping (also for the related D42478).

Feb 12 2018, 2:05 AM
olista01 added inline comments to D42784: [ARM] Allow Half types in ConstantPool.
Feb 12 2018, 1:55 AM

Feb 9 2018

olista01 added inline comments to D42784: [ARM] Allow Half types in ConstantPool.
Feb 9 2018, 7:08 AM
olista01 committed rL324731: [ELF] Print the .type assembly directive correctly for STT_NOTYPE.
[ELF] Print the .type assembly directive correctly for STT_NOTYPE
Feb 9 2018, 5:36 AM
olista01 closed D43116: [ELF] Print the .type assembly directive correctly for STT_NOTYPE.
Feb 9 2018, 5:36 AM
olista01 updated the diff for D43116: [ELF] Print the .type assembly directive correctly for STT_NOTYPE.

Add a triple to the test.

Feb 9 2018, 3:35 AM
olista01 created D43116: [ELF] Print the .type assembly directive correctly for STT_NOTYPE.
Feb 9 2018, 3:34 AM

Feb 8 2018

olista01 committed rL324606: [ARM] Re-commit r324600 with fixed LLVMBuild.txt.
[ARM] Re-commit r324600 with fixed LLVMBuild.txt
Feb 8 2018, 6:34 AM
olista01 committed rL324604: Revert r324600 as it breaks a buildbot.
Revert r324600 as it breaks a buildbot
Feb 8 2018, 6:24 AM
olista01 committed rL324600: [ARM] Fix disassembly of invalid banked register moves.
[ARM] Fix disassembly of invalid banked register moves
Feb 8 2018, 5:10 AM
olista01 closed D43066: [ARM] Fix disassembly of invalid banked register moves.
Feb 8 2018, 5:10 AM
olista01 added a comment to D43066: [ARM] Fix disassembly of invalid banked register moves.

Was only wondering about the Cortex-A8 -> A15 change in the test run line.

Feb 8 2018, 3:17 AM
olista01 created D43066: [ARM] Fix disassembly of invalid banked register moves.
Feb 8 2018, 2:19 AM

Feb 7 2018

olista01 accepted D43020: [AArch64] Don't materialize 0 with "fmov h0, .." when FullFP16 is not supported..

LGTM, but please wait a day to let other time zones comment.

Feb 7 2018, 7:22 AM
olista01 accepted D42965: [CodeGen] Add a -trap-unreachable option for debugging.

LGTM.

Feb 7 2018, 5:40 AM

Feb 6 2018

olista01 accepted D42954: [ARM] f16 conversions.

Thanks, LGTM.

Feb 6 2018, 8:23 AM
olista01 added inline comments to D42962: [ARM] Allow 64- and 128-bit types with 't' inline asm constraint.
Feb 6 2018, 8:01 AM
olista01 added a comment to D42965: [CodeGen] Add a -trap-unreachable option for debugging.

Would it be possible to enable this for all targets, not just ARM? Maybe this could be put into the constructor of LLVMTargetMachine?

Feb 6 2018, 7:22 AM
olista01 added inline comments to D42954: [ARM] f16 conversions.
Feb 6 2018, 5:23 AM
olista01 committed rL324325: [AArch64] Fix spelling of ICH_ELRSR_EL2 system register.
[AArch64] Fix spelling of ICH_ELRSR_EL2 system register
Feb 6 2018, 1:41 AM
olista01 committed rL324324: [ARM][AArch64] Add CSDB speculation barrier instruction.
[ARM][AArch64] Add CSDB speculation barrier instruction
Feb 6 2018, 1:27 AM

Feb 5 2018

olista01 accepted D42849: [ARM] Armv8.2-A FP16 code generation (part 3/3).

LGTM with a few nits (see inline comments), but please give 24 hours for other time zones to comment before committing.

Feb 5 2018, 2:59 AM

Feb 2 2018

olista01 added a comment to D42477: [AArch64] Improve v8.1-A code-gen for atomic load-subtract.

Ping.

Feb 2 2018, 1:46 AM

Feb 1 2018

olista01 accepted D42743: [ARM] FullFP16 LowerReturn Fix.

LGTM, thanks.

Feb 1 2018, 5:46 AM
olista01 added inline comments to D42743: [ARM] FullFP16 LowerReturn Fix.
Feb 1 2018, 2:21 AM

Jan 31 2018

olista01 accepted D42293: [TableGen][AsmMatcherEmitter] Fix tied-constraint checking for InstAliases.

LGTM.

Jan 31 2018, 8:50 AM
olista01 accepted D41905: [ARM] Add support for unpredictable MVN instructions..

LGTM, thanks!

Jan 31 2018, 4:58 AM
olista01 accepted D42580: [ARM] Armv8.2-A FP16 code generation (part 2/3).

Thanks for making these changes, LGTM.

Jan 31 2018, 2:03 AM

Jan 30 2018

olista01 added a comment to D42580: [ARM] Armv8.2-A FP16 code generation (part 2/3).

I'm still not convinced about the correctness of this transformation: you are turning code which contains truncates and extends into code that doesn't, without checking whether the top 16 bits could be relevant. This happens to be OK if the value is coming from/going to an fp16 arithmetic instruction, which ignores/clears the top 16 bits, but I don't think it's correct in all cases.

Jan 30 2018, 5:22 AM

Jan 29 2018

olista01 added a comment to D42580: [ARM] Armv8.2-A FP16 code generation (part 2/3).

Is your concern that I am changing the semantics of these nodes because I am omitting this convert?

Jan 29 2018, 8:48 AM
olista01 added a comment to D42580: [ARM] Armv8.2-A FP16 code generation (part 2/3).

It might be intended to only apply to function arguments and returns, but those patterns for f16_to_fp and fp_to_f16 could match anywhere.

Jan 29 2018, 7:38 AM
olista01 added a comment to D42580: [ARM] Armv8.2-A FP16 code generation (part 2/3).

Have you tried adding tablegen patterns for bitconvert nodes between i16 and f16? That's how it currently works for f32<->i32, see the VMOVRS and VMOVSR instructions in ARMInstrVFP.td.

Jan 29 2018, 3:05 AM
olista01 committed rL323634: [AArch64] Generate the CASP instruction for 128-bit cmpxchg.
[AArch64] Generate the CASP instruction for 128-bit cmpxchg
Jan 29 2018, 1:20 AM
olista01 closed D42104: [AArch64] Generate the CASP instruction for 128-bit cmpxchg.
Jan 29 2018, 1:20 AM

Jan 25 2018

olista01 added a comment to D38315: [ARM] Armv8.2-A FP16 code generation (part 1/3).

Ok, I agree with the idea of committing this as a starting point and developing it gradually. Just a few nits left.

Jan 25 2018, 3:57 AM

Jan 24 2018

olista01 added inline comments to D38315: [ARM] Armv8.2-A FP16 code generation (part 1/3).
Jan 24 2018, 7:27 AM
olista01 added a dependency for D42478: [AArch64] Improve v8.1-A code-gen for atomic load-and: D42477: [AArch64] Improve v8.1-A code-gen for atomic load-subtract.
Jan 24 2018, 6:59 AM
olista01 added a dependent revision for D42477: [AArch64] Improve v8.1-A code-gen for atomic load-subtract: D42478: [AArch64] Improve v8.1-A code-gen for atomic load-and.
Jan 24 2018, 6:59 AM
olista01 created D42478: [AArch64] Improve v8.1-A code-gen for atomic load-and.
Jan 24 2018, 6:58 AM
olista01 created D42477: [AArch64] Improve v8.1-A code-gen for atomic load-subtract.
Jan 24 2018, 6:58 AM

Jan 23 2018

olista01 added a comment to D42104: [AArch64] Generate the CASP instruction for 128-bit cmpxchg.

Ping

Jan 23 2018, 6:13 AM

Jan 19 2018

olista01 added a comment to D42293: [TableGen][AsmMatcherEmitter] Fix tied-constraint checking for InstAliases.

Well, this patch doesn't change the actual conversion to MCInst, it just encodes more information into the conversion-function by using an indirection through the 'TiedAsmOperandTable'. It will still create the MCInst in the same way as it did before.

Jan 19 2018, 9:10 AM
olista01 added a comment to D42293: [TableGen][AsmMatcherEmitter] Fix tied-constraint checking for InstAliases.

I was looking at your original version of this the other day to work out if it could be used to do 3-operand aliases of 2-operand Thumb1 instructions, and this (adding support for aliases) looks like it's what we would need for that.

Jan 19 2018, 7:44 AM

Jan 17 2018

olista01 accepted D41863: [AArch64] Fix incorrect LD1 of 16-bit FP vectors in big endian.

I've spotted a missed optimisation in the tests, but that should be done as a separate patch.

Jan 17 2018, 5:02 AM
olista01 added inline comments to D41905: [ARM] Add support for unpredictable MVN instructions..
Jan 17 2018, 4:41 AM

Jan 16 2018

olista01 added a comment to D38315: [ARM] Armv8.2-A FP16 code generation (part 1/3).

This looks like a lot of additional complexity to deal with the case where we only have the conversion instructions, but you have made f16 a legal type.

Jan 16 2018, 8:23 AM