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olista01 (Oliver Stannard)
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User Since
Feb 5 2014, 1:36 AM (263 w, 3 d)

Recent Activity

Thu, Feb 21

olista01 accepted D58059: [AArch64] Print instruction before atomic semantic annotations.

LGTM

Thu, Feb 21, 1:53 AM · Restricted Project

Mon, Feb 18

olista01 committed rGe3c8ce8b7547: [ARM] Add pre-defined macros for ROPI and RWPI (authored by olista01).
[ARM] Add pre-defined macros for ROPI and RWPI
Mon, Feb 18, 4:40 AM
olista01 committed rC354265: [ARM] Add pre-defined macros for ROPI and RWPI.
[ARM] Add pre-defined macros for ROPI and RWPI
Mon, Feb 18, 4:39 AM
olista01 committed rL354265: [ARM] Add pre-defined macros for ROPI and RWPI.
[ARM] Add pre-defined macros for ROPI and RWPI
Mon, Feb 18, 4:39 AM
olista01 closed D23610: [ARM] Add pre-defined macros for ROPI and RWPI.
Mon, Feb 18, 4:39 AM · Restricted Project
olista01 added a comment to D23610: [ARM] Add pre-defined macros for ROPI and RWPI.

Yes, the back-end work was all done years ago, I just also forgot about these while waiting for the ACLE to be published.

Mon, Feb 18, 4:38 AM · Restricted Project
Herald added a project to D54791: [AArch64] Fix disassembly of SXTL and UXTL aliases: Restricted Project.

Ping

Mon, Feb 18, 3:12 AM · Restricted Project
olista01 added a comment to D23610: [ARM] Add pre-defined macros for ROPI and RWPI.

These macros have been in the published ACLE for a while now: https://developer.arm.com/products/software-development-tools/compilers/arm-compiler-5/docs/101028/latest/5-feature-test-macros#position-independent-code

Mon, Feb 18, 3:08 AM · Restricted Project

Wed, Feb 13

olista01 requested changes to D58059: [AArch64] Print instruction before atomic semantic annotations.

I think it would be neater to move this annotation printing code to after the regular printAliasInstr/printInstruction calls at the end of the function (line 300). As it is, this patch will drop any other annotations on the instruction, because it doesn't call printAnnotation(O, Annot).

Wed, Feb 13, 5:55 AM · Restricted Project

Wed, Feb 6

olista01 requested changes to D57765: [ARM] Add Cortex-M35P Support.
Wed, Feb 6, 5:24 AM · Restricted Project
olista01 requested changes to D57763: [ARM] Add Cortex-M35P.
Wed, Feb 6, 5:22 AM · Restricted Project
olista01 accepted D57764: [AArch64] Add Cortex-A76 and Cortex-A76AE Support.

LGTM, but please remember to upload with more context.

Wed, Feb 6, 5:15 AM · Restricted Project
olista01 accepted D57762: [AArch64] Add support for Cortex-A76 and Cortex-A76AE.

LGTM with one minor nit.

Wed, Feb 6, 5:11 AM · Restricted Project

Tue, Feb 5

olista01 committed rG78dc38ec9422: [AArch64][Outliner] Don't outline BTI instructions (authored by olista01).
[AArch64][Outliner] Don't outline BTI instructions
Tue, Feb 5, 9:22 AM
olista01 committed rL353190: [AArch64][Outliner] Don't outline BTI instructions.
[AArch64][Outliner] Don't outline BTI instructions
Tue, Feb 5, 9:22 AM
olista01 closed D57753: [AArch64][Outliner] Don't outline BTI instructions.
Tue, Feb 5, 9:21 AM · Restricted Project
olista01 created D57753: [AArch64][Outliner] Don't outline BTI instructions.
Tue, Feb 5, 7:29 AM · Restricted Project

Fri, Feb 1

olista01 committed rL352844: [CodeGen] Don't scavenge non-saved regs in exception throwing functions.
[CodeGen] Don't scavenge non-saved regs in exception throwing functions
Fri, Feb 1, 1:23 AM
olista01 closed D57381: [CodeGen] Don't scavenge non-saved regs in exception throwing functions.
Fri, Feb 1, 1:23 AM · Restricted Project

Thu, Jan 31

olista01 updated the diff for D57381: [CodeGen] Don't scavenge non-saved regs in exception throwing functions.
Thu, Jan 31, 1:27 AM · Restricted Project

Wed, Jan 30

olista01 updated the diff for D57381: [CodeGen] Don't scavenge non-saved regs in exception throwing functions.
Wed, Jan 30, 2:23 AM · Restricted Project

Tue, Jan 29

olista01 updated the diff for D57381: [CodeGen] Don't scavenge non-saved regs in exception throwing functions.
Tue, Jan 29, 6:45 AM · Restricted Project
olista01 added a comment to D57335: [IR] Don't assume all functions are 4 byte aligned.

Why do you think this would be better as a target hook, rather than in the datalayout? The datalayout already includes information about alignments of different types, and most of the target hooks are concerned with what IR will be efficient for the target, not things which might affect correctness.

Tue, Jan 29, 6:31 AM
olista01 created D57381: [CodeGen] Don't scavenge non-saved regs in exception throwing functions.
Tue, Jan 29, 6:17 AM · Restricted Project

Jan 22 2019

olista01 accepted D56717: [SLH] AArch64: correctly pick temporary register to mask SP.

LGTM with one nit.

Jan 22 2019, 6:26 AM

Jan 15 2019

olista01 requested changes to D56717: [SLH] AArch64: correctly pick temporary register to mask SP.
Jan 15 2019, 7:27 AM

Jan 9 2019

olista01 accepted D55929: Initial AArch64 SLH implementation..

LGTM, thanks.

Jan 9 2019, 3:24 AM

Jan 8 2019

olista01 added inline comments to D55929: Initial AArch64 SLH implementation..
Jan 8 2019, 7:46 AM

Jan 2 2019

olista01 added a comment to D54685: [AArch64] Allow -mattr=use_el[1|2|3] and -mattr=use_sp_for_tp.

What is the use-case for wanting to use SP_ELx for the thread pointer, instead of TPIDR_ELx?

Jan 2 2019, 3:51 AM

Dec 21 2018

olista01 added inline comments to D55990: [ARM] Add command-line option for SB.
Dec 21 2018, 2:49 AM
olista01 added inline comments to D55921: [AArch64] Add command-line option for SB.
Dec 21 2018, 2:47 AM

Dec 20 2018

olista01 accepted D51798: [Dwarf/AArch64] Return address signing B key dwarf support.

LGTM, thanks!

Dec 20 2018, 8:08 AM

Dec 18 2018

olista01 accepted D55774: [AArch64] - Return address signing dwarf support.

LGTM with one nit.

Dec 18 2018, 2:35 AM

Dec 17 2018

olista01 accepted D54896: Introduce control flow speculation tracking pass for AArch64..

LGTM.

Dec 17 2018, 8:47 AM
olista01 accepted D55704: [AArch64][libunwind] Unwinding support for return address signing with B Key.

LGTM with one nit.

Dec 17 2018, 3:33 AM

Dec 14 2018

olista01 accepted D55700: [AArch64][libunwind] Unwinding support for return address signing.

LGTM with one nit.

Dec 14 2018, 3:25 AM

Dec 11 2018

olista01 added a comment to rL348114: [ARM][MC] Move information about variadic register defs into tablegen.

In the ARM backend, we only use variable_ops for the LDM and STM instructions, where the variadic operands are either all uses or all defs. I'm less familiar with the other backends, but all of the other cases where variable_ops is used look similar.

Dec 11 2018, 1:31 AM

Dec 3 2018

olista01 added inline comments to D54633: [NFC][AArch64] Split out backend features.
Dec 3 2018, 2:42 AM
olista01 committed rL348114: [ARM][MC] Move information about variadic register defs into tablegen.
[ARM][MC] Move information about variadic register defs into tablegen
Dec 3 2018, 2:36 AM
olista01 closed D54853: [ARM][MC] Move information about variadic register defs into tablegen.
Dec 3 2018, 2:36 AM
olista01 committed rL348113: [ARM][Asm] Debug trace for the processInstruction loop.
[ARM][Asm] Debug trace for the processInstruction loop
Dec 3 2018, 2:24 AM
olista01 closed D54852: [ARM][Asm] Debug trace for the processInstruction loop.
Dec 3 2018, 2:24 AM
olista01 added a comment to D54853: [ARM][MC] Move information about variadic register defs into tablegen.

I can't think of any general way to test this, because these properties of MCInsts are not used much. The Thumb instructions which this applies to are tested by test/MC/ARM/implicit-it-generation.s, which has a big list of PC-writing instructions which cannot be used in the middle of an IT block, this patch is NFC for them.

Dec 3 2018, 1:59 AM
olista01 accepted D54633: [NFC][AArch64] Split out backend features.

A few nits, but otherwise LGTM, no need to re-review after fixing them.

Dec 3 2018, 1:54 AM

Nov 30 2018

olista01 added inline comments to D55059: [ARM] FP16: constant initialised v4f16 and v8f16 vectors.
Nov 30 2018, 1:05 AM

Nov 28 2018

olista01 added a comment to D54891: [RFC] Checking inline assembly for validity.

I can provide a full log of the 4831 warnings marked -Winline-asm during a Firefox for ARM Android build, if you're interested.

Nov 28 2018, 3:43 AM
olista01 updated the diff for D54891: [RFC] Checking inline assembly for validity.
  • Make the "cc" inline assembly clobber affect all status registers
  • Handle tied operands correctly in the AsmMatcher (fixes post-increment ldr/str instructions)
  • Fix outputs of t2AsmPseudo records (fixes Thumb2 mov with shifted right-hand operand)
  • Call transferInlineAsmOps in cases where we parse more than one operand at once
Nov 28 2018, 3:42 AM
olista01 added a comment to D54891: [RFC] Checking inline assembly for validity.

mpi_arm.c:

  • For the warnings which are emitted, some register MCOperands are being matched against the wrong parsed operand.
  • For post-increment instructions, the assembly matcher is not setting the writeback register in the MCInst (leaving it as noreg), because it is tied to one part of a complex operand, which it doesn't support. The fix for this might be to make a similar change to rL209425 in the ARM backend, which would give other advantages (better diagnostics for memory operands).
Nov 28 2018, 3:34 AM

Nov 27 2018

olista01 added a comment to D54891: [RFC] Checking inline assembly for validity.

For the first example, it looks like we're missing the case where a memory instruction with writeback modifies the address register. I'll have a look and see if there's a way to fix that.

Nov 27 2018, 3:46 AM
olista01 added a child revision for D54853: [ARM][MC] Move information about variadic register defs into tablegen: D54891: [RFC] Checking inline assembly for validity.
Nov 27 2018, 3:35 AM
olista01 added a parent revision for D54891: [RFC] Checking inline assembly for validity: D54853: [ARM][MC] Move information about variadic register defs into tablegen.
Nov 27 2018, 3:35 AM
olista01 added a comment to D54633: [NFC][AArch64] Split out backend features.

However, the ID_AA64MMFR2_EL1 register was added in v8.2. So I believe we should check as to warn the user if he might get undefined behavior by accessing it when not present.

Nov 27 2018, 3:05 AM
olista01 added a comment to D54896: Introduce control flow speculation tracking pass for AArch64..

There currently isn't even a user interface to reserve X16.

Nov 27 2018, 2:22 AM

Nov 26 2018

olista01 updated the diff for D54853: [ARM][MC] Move information about variadic register defs into tablegen.

Remove special case in MCInstrDesc::mayAffectControlFlow, which is no longer needed.

Nov 26 2018, 3:52 AM
olista01 created D54891: [RFC] Checking inline assembly for validity.
Nov 26 2018, 2:50 AM

Nov 23 2018

olista01 committed rL347494: [ARM][AsmParser] Improve debug printing of parsed asm operands.
[ARM][AsmParser] Improve debug printing of parsed asm operands
Nov 23 2018, 6:30 AM
olista01 closed D54850: [ARM][AsmParser] Improve debug printing of parsed asm operands.
Nov 23 2018, 6:30 AM
olista01 added a comment to D54850: [ARM][AsmParser] Improve debug printing of parsed asm operands.

This is only used for the -debug output (i.e. things inside the LLVM_DEBUG macro) and from within a debugger, I don't think we tend to test that.

Nov 23 2018, 6:27 AM
olista01 created D54853: [ARM][MC] Move information about variadic register defs into tablegen.
Nov 23 2018, 3:38 AM
olista01 created D54852: [ARM][Asm] Debug trace for the processInstruction loop.
Nov 23 2018, 3:36 AM
olista01 created D54850: [ARM][AsmParser] Improve debug printing of parsed asm operands.
Nov 23 2018, 3:35 AM
olista01 added a comment to D54633: [NFC][AArch64] Split out backend features.

Have you discussed these feature names with the GCC devs? I know we can change the user-facing names used by clang in in TargetParser, but it's easier for us if they match.

Nov 23 2018, 2:26 AM

Nov 21 2018

olista01 created D54791: [AArch64] Fix disassembly of SXTL and UXTL aliases.
Nov 21 2018, 5:32 AM · Restricted Project

Nov 7 2018

olista01 accepted D54148: [NFC][Clang][Aarch64] Add missing test file.

LGTM

Nov 7 2018, 3:35 AM

Oct 25 2018

olista01 accepted D51429: [AArch64] Return Address Signing B Key Support.

LGTM, thanks!

Oct 25 2018, 1:40 AM

Oct 17 2018

olista01 added a comment to D51427: [AArch64] Return address signing B key support.

Hi Luke,

Oct 17 2018, 1:23 PM
olista01 added inline comments to D51429: [AArch64] Return Address Signing B Key Support.
Oct 17 2018, 1:21 PM

Oct 11 2018

olista01 accepted D53132: [AARCH64][FIX] Emit data symbol for constant pool data.

LGTM

Oct 11 2018, 6:58 AM
olista01 requested changes to D53132: [AARCH64][FIX] Emit data symbol for constant pool data.

Actually, the test uses cortex-a76, but I don't think that's been committed yet. This isn't CPU-dependent, so you should be able to just remove the option.

Oct 11 2018, 6:15 AM
olista01 accepted D53132: [AARCH64][FIX] Emit data symbol for constant pool data.

LGTM, thanks!

Oct 11 2018, 6:13 AM

Oct 9 2018

olista01 added inline comments to D51798: [Dwarf/AArch64] Return address signing B key dwarf support.
Oct 9 2018, 5:53 AM
olista01 added inline comments to D51429: [AArch64] Return Address Signing B Key Support.
Oct 9 2018, 5:10 AM

Oct 8 2018

olista01 committed rL343969: [AArch64][v8.5A] Don't create BR instructions in outliner when BTI enabled.
[AArch64][v8.5A] Don't create BR instructions in outliner when BTI enabled
Oct 8 2018, 7:14 AM
olista01 closed D52869: [AArch64][v8.5A] Don't create BR instructions in outliner when BTI enabled.
Oct 8 2018, 7:14 AM
olista01 committed rL343968: [AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI.
[AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI
Oct 8 2018, 7:11 AM
olista01 closed D52868: [AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI.
Oct 8 2018, 7:11 AM
olista01 committed rL343967: [AArch64][v8.5A] Branch Target Identification code-generation pass.
[AArch64][v8.5A] Branch Target Identification code-generation pass
Oct 8 2018, 7:07 AM
olista01 closed D52867: [AArch64][v8.5A] Branch Target Identification code-generation pass.
Oct 8 2018, 7:06 AM
olista01 updated the diff for D52868: [AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI.

Remove unnecessary Requires on pseudo-instructions.

Oct 8 2018, 6:56 AM
olista01 committed rL343959: [AArch64] Fix verifier error when outlining indirect calls.
[AArch64] Fix verifier error when outlining indirect calls
Oct 8 2018, 2:20 AM
olista01 closed D52829: [AArch64] Fix verifier error when outlining indirect calls.
Oct 8 2018, 2:20 AM

Oct 4 2018

olista01 added a comment to D52829: [AArch64] Fix verifier error when outlining indirect calls.

I don't think adding a special case to the verifier makes sense, when it's easy enough to generate code which is valid by the normal rules.

Oct 4 2018, 2:22 AM
olista01 edited reviewers for D52829: [AArch64] Fix verifier error when outlining indirect calls, added: paquette; removed: jpaquette.
Oct 4 2018, 1:48 AM
olista01 edited reviewers for D52869: [AArch64][v8.5A] Don't create BR instructions in outliner when BTI enabled, added: paquette; removed: jpaquette.
Oct 4 2018, 1:48 AM
olista01 created D52869: [AArch64][v8.5A] Don't create BR instructions in outliner when BTI enabled.
Oct 4 2018, 1:36 AM
olista01 created D52868: [AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI.
Oct 4 2018, 1:36 AM
olista01 added reviewers for D52829: [AArch64] Fix verifier error when outlining indirect calls: t.p.northover, rengolin, LukeCheeseman.
Oct 4 2018, 1:36 AM
olista01 created D52867: [AArch64][v8.5A] Branch Target Identification code-generation pass.
Oct 4 2018, 1:32 AM

Oct 3 2018

olista01 created D52829: [AArch64] Fix verifier error when outlining indirect calls.
Oct 3 2018, 5:31 AM

Oct 2 2018

olista01 accepted D52737: [ARM] Emmit data symbol for constant pool data.

LGTM with one nit.

Oct 2 2018, 7:46 AM
olista01 added inline comments to D52737: [ARM] Emmit data symbol for constant pool data.
Oct 2 2018, 3:12 AM
olista01 committed rL343572: [AArch64][v8.5A] Add Memory Tagging instructions.
[AArch64][v8.5A] Add Memory Tagging instructions
Oct 2 2018, 3:07 AM
olista01 closed D52490: [AArch64][v8.5A] Add Memory Tagging instructions.
Oct 2 2018, 3:06 AM
olista01 committed rL343571: [AArch64][v8.5A] Add Memory Tagging system registers.
[AArch64][v8.5A] Add Memory Tagging system registers
Oct 2 2018, 2:56 AM
olista01 closed D52488: [AArch64][v8.5A] Add Memory Tagging system registers.
Oct 2 2018, 2:56 AM
olista01 committed rL343570: [AArch64][v8.5A] Add MTE system instructions.
[AArch64][v8.5A] Add MTE system instructions
Oct 2 2018, 2:50 AM
olista01 closed D52487: [AArch64][v8.5A] Add MTE system instructions.
Oct 2 2018, 2:50 AM
olista01 committed rC343566: [AArch64][v8.5A] Test clang option for the Memory Tagging Extension.
[AArch64][v8.5A] Test clang option for the Memory Tagging Extension
Oct 2 2018, 2:41 AM
olista01 committed rL343566: [AArch64][v8.5A] Test clang option for the Memory Tagging Extension.
[AArch64][v8.5A] Test clang option for the Memory Tagging Extension
Oct 2 2018, 2:41 AM
olista01 closed D52493: [AArch64][v8.5A] Test clang option for the Memory Tagging Extension.
Oct 2 2018, 2:41 AM