- User Since
- Feb 5 2014, 1:36 AM (253 w, 18 h)
In the ARM backend, we only use variable_ops for the LDM and STM instructions, where the variadic operands are either all uses or all defs. I'm less familiar with the other backends, but all of the other cases where variable_ops is used look similar.
Mon, Dec 3
I can't think of any general way to test this, because these properties of MCInsts are not used much. The Thumb instructions which this applies to are tested by test/MC/ARM/implicit-it-generation.s, which has a big list of PC-writing instructions which cannot be used in the middle of an IT block, this patch is NFC for them.
A few nits, but otherwise LGTM, no need to re-review after fixing them.
Fri, Nov 30
Wed, Nov 28
I can provide a full log of the 4831 warnings marked -Winline-asm during a Firefox for ARM Android build, if you're interested.
- Make the "cc" inline assembly clobber affect all status registers
- Handle tied operands correctly in the AsmMatcher (fixes post-increment ldr/str instructions)
- Fix outputs of t2AsmPseudo records (fixes Thumb2 mov with shifted right-hand operand)
- Call transferInlineAsmOps in cases where we parse more than one operand at once
- For the warnings which are emitted, some register MCOperands are being matched against the wrong parsed operand.
- For post-increment instructions, the assembly matcher is not setting the writeback register in the MCInst (leaving it as noreg), because it is tied to one part of a complex operand, which it doesn't support. The fix for this might be to make a similar change to rL209425 in the ARM backend, which would give other advantages (better diagnostics for memory operands).
Tue, Nov 27
For the first example, it looks like we're missing the case where a memory instruction with writeback modifies the address register. I'll have a look and see if there's a way to fix that.
However, the ID_AA64MMFR2_EL1 register was added in v8.2. So I believe we should check as to warn the user if he might get undefined behavior by accessing it when not present.
There currently isn't even a user interface to reserve X16.
Mon, Nov 26
Remove special case in MCInstrDesc::mayAffectControlFlow, which is no longer needed.
Fri, Nov 23
This is only used for the -debug output (i.e. things inside the LLVM_DEBUG macro) and from within a debugger, I don't think we tend to test that.
Have you discussed these feature names with the GCC devs? I know we can change the user-facing names used by clang in in TargetParser, but it's easier for us if they match.
Wed, Nov 21
Nov 7 2018
Oct 25 2018
Oct 17 2018
Oct 11 2018
Actually, the test uses cortex-a76, but I don't think that's been committed yet. This isn't CPU-dependent, so you should be able to just remove the option.
Oct 9 2018
Oct 8 2018
Remove unnecessary Requires on pseudo-instructions.
Oct 4 2018
I don't think adding a special case to the verifier makes sense, when it's easy enough to generate code which is valid by the normal rules.
Oct 3 2018
Oct 2 2018
LGTM with one nit.
Ping. This is the last patch for Armv8.5A (dis)assembler support which needs review, all of the ones adding the memory tagging instructions and registers are approved but depend on this one, and all of the other features are now committed.
Sep 28 2018
Sep 27 2018
Rename feature to FeatureFRInt3264.