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olista01 (Oliver Stannard)
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User Since
Feb 5 2014, 1:36 AM (253 w, 18 h)

Recent Activity

Yesterday

olista01 added a comment to rL348114: [ARM][MC] Move information about variadic register defs into tablegen.

In the ARM backend, we only use variable_ops for the LDM and STM instructions, where the variadic operands are either all uses or all defs. I'm less familiar with the other backends, but all of the other cases where variable_ops is used look similar.

Tue, Dec 11, 1:31 AM

Mon, Dec 3

olista01 added inline comments to D54633: [NFC][AArch64] Split out backend features.
Mon, Dec 3, 2:42 AM
olista01 committed rL348114: [ARM][MC] Move information about variadic register defs into tablegen.
[ARM][MC] Move information about variadic register defs into tablegen
Mon, Dec 3, 2:36 AM
olista01 closed D54853: [ARM][MC] Move information about variadic register defs into tablegen.
Mon, Dec 3, 2:36 AM
olista01 committed rL348113: [ARM][Asm] Debug trace for the processInstruction loop.
[ARM][Asm] Debug trace for the processInstruction loop
Mon, Dec 3, 2:24 AM
olista01 closed D54852: [ARM][Asm] Debug trace for the processInstruction loop.
Mon, Dec 3, 2:24 AM
olista01 added a comment to D54853: [ARM][MC] Move information about variadic register defs into tablegen.

I can't think of any general way to test this, because these properties of MCInsts are not used much. The Thumb instructions which this applies to are tested by test/MC/ARM/implicit-it-generation.s, which has a big list of PC-writing instructions which cannot be used in the middle of an IT block, this patch is NFC for them.

Mon, Dec 3, 1:59 AM
olista01 accepted D54633: [NFC][AArch64] Split out backend features.

A few nits, but otherwise LGTM, no need to re-review after fixing them.

Mon, Dec 3, 1:54 AM

Fri, Nov 30

olista01 added inline comments to D55059: [ARM] FP16: constant initialised v4f16 and v8f16 vectors.
Fri, Nov 30, 1:05 AM

Wed, Nov 28

olista01 added a comment to D54891: [RFC] Checking inline assembly for validity.

I can provide a full log of the 4831 warnings marked -Winline-asm during a Firefox for ARM Android build, if you're interested.

Wed, Nov 28, 3:43 AM
olista01 updated the diff for D54891: [RFC] Checking inline assembly for validity.
  • Make the "cc" inline assembly clobber affect all status registers
  • Handle tied operands correctly in the AsmMatcher (fixes post-increment ldr/str instructions)
  • Fix outputs of t2AsmPseudo records (fixes Thumb2 mov with shifted right-hand operand)
  • Call transferInlineAsmOps in cases where we parse more than one operand at once
Wed, Nov 28, 3:42 AM
olista01 added a comment to D54891: [RFC] Checking inline assembly for validity.

mpi_arm.c:

  • For the warnings which are emitted, some register MCOperands are being matched against the wrong parsed operand.
  • For post-increment instructions, the assembly matcher is not setting the writeback register in the MCInst (leaving it as noreg), because it is tied to one part of a complex operand, which it doesn't support. The fix for this might be to make a similar change to rL209425 in the ARM backend, which would give other advantages (better diagnostics for memory operands).
Wed, Nov 28, 3:34 AM

Tue, Nov 27

olista01 added a comment to D54891: [RFC] Checking inline assembly for validity.

For the first example, it looks like we're missing the case where a memory instruction with writeback modifies the address register. I'll have a look and see if there's a way to fix that.

Tue, Nov 27, 3:46 AM
olista01 added a child revision for D54853: [ARM][MC] Move information about variadic register defs into tablegen: D54891: [RFC] Checking inline assembly for validity.
Tue, Nov 27, 3:35 AM
olista01 added a parent revision for D54891: [RFC] Checking inline assembly for validity: D54853: [ARM][MC] Move information about variadic register defs into tablegen.
Tue, Nov 27, 3:35 AM
olista01 added a comment to D54633: [NFC][AArch64] Split out backend features.

However, the ID_AA64MMFR2_EL1 register was added in v8.2. So I believe we should check as to warn the user if he might get undefined behavior by accessing it when not present.

Tue, Nov 27, 3:05 AM
olista01 added a comment to D54896: Introduce control flow speculation tracking pass for AArch64..

There currently isn't even a user interface to reserve X16.

Tue, Nov 27, 2:22 AM

Mon, Nov 26

olista01 updated the diff for D54853: [ARM][MC] Move information about variadic register defs into tablegen.

Remove special case in MCInstrDesc::mayAffectControlFlow, which is no longer needed.

Mon, Nov 26, 3:52 AM
olista01 created D54891: [RFC] Checking inline assembly for validity.
Mon, Nov 26, 2:50 AM

Fri, Nov 23

olista01 committed rL347494: [ARM][AsmParser] Improve debug printing of parsed asm operands.
[ARM][AsmParser] Improve debug printing of parsed asm operands
Fri, Nov 23, 6:30 AM
olista01 closed D54850: [ARM][AsmParser] Improve debug printing of parsed asm operands.
Fri, Nov 23, 6:30 AM
olista01 added a comment to D54850: [ARM][AsmParser] Improve debug printing of parsed asm operands.

This is only used for the -debug output (i.e. things inside the LLVM_DEBUG macro) and from within a debugger, I don't think we tend to test that.

Fri, Nov 23, 6:27 AM
olista01 created D54853: [ARM][MC] Move information about variadic register defs into tablegen.
Fri, Nov 23, 3:38 AM
olista01 created D54852: [ARM][Asm] Debug trace for the processInstruction loop.
Fri, Nov 23, 3:36 AM
olista01 created D54850: [ARM][AsmParser] Improve debug printing of parsed asm operands.
Fri, Nov 23, 3:35 AM
olista01 added a comment to D54633: [NFC][AArch64] Split out backend features.

Have you discussed these feature names with the GCC devs? I know we can change the user-facing names used by clang in in TargetParser, but it's easier for us if they match.

Fri, Nov 23, 2:26 AM

Wed, Nov 21

olista01 created D54791: [AArch64] Fix disassembly of SXTL and UXTL aliases.
Wed, Nov 21, 5:32 AM

Nov 7 2018

olista01 accepted D54148: [NFC][Clang][Aarch64] Add missing test file.

LGTM

Nov 7 2018, 3:35 AM

Oct 25 2018

olista01 accepted D51429: [AArch64] Return Address Signing B Key Support.

LGTM, thanks!

Oct 25 2018, 1:40 AM

Oct 17 2018

olista01 added a comment to D51427: [AArch64] Return address signing B key support.

Hi Luke,

Oct 17 2018, 1:23 PM
olista01 added inline comments to D51429: [AArch64] Return Address Signing B Key Support.
Oct 17 2018, 1:21 PM

Oct 11 2018

olista01 accepted D53132: [AARCH64][FIX] Emit data symbol for constant pool data.

LGTM

Oct 11 2018, 6:58 AM
olista01 requested changes to D53132: [AARCH64][FIX] Emit data symbol for constant pool data.

Actually, the test uses cortex-a76, but I don't think that's been committed yet. This isn't CPU-dependent, so you should be able to just remove the option.

Oct 11 2018, 6:15 AM
olista01 accepted D53132: [AARCH64][FIX] Emit data symbol for constant pool data.

LGTM, thanks!

Oct 11 2018, 6:13 AM

Oct 9 2018

olista01 added inline comments to D51798: [Dwarf/AArch64] Return address signing B key dwarf support.
Oct 9 2018, 5:53 AM
olista01 added inline comments to D51429: [AArch64] Return Address Signing B Key Support.
Oct 9 2018, 5:10 AM

Oct 8 2018

olista01 committed rL343969: [AArch64][v8.5A] Don't create BR instructions in outliner when BTI enabled.
[AArch64][v8.5A] Don't create BR instructions in outliner when BTI enabled
Oct 8 2018, 7:14 AM
olista01 closed D52869: [AArch64][v8.5A] Don't create BR instructions in outliner when BTI enabled.
Oct 8 2018, 7:14 AM
olista01 committed rL343968: [AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI.
[AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI
Oct 8 2018, 7:11 AM
olista01 closed D52868: [AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI.
Oct 8 2018, 7:11 AM
olista01 committed rL343967: [AArch64][v8.5A] Branch Target Identification code-generation pass.
[AArch64][v8.5A] Branch Target Identification code-generation pass
Oct 8 2018, 7:07 AM
olista01 closed D52867: [AArch64][v8.5A] Branch Target Identification code-generation pass.
Oct 8 2018, 7:06 AM
olista01 updated the diff for D52868: [AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI.

Remove unnecessary Requires on pseudo-instructions.

Oct 8 2018, 6:56 AM
olista01 committed rL343959: [AArch64] Fix verifier error when outlining indirect calls.
[AArch64] Fix verifier error when outlining indirect calls
Oct 8 2018, 2:20 AM
olista01 closed D52829: [AArch64] Fix verifier error when outlining indirect calls.
Oct 8 2018, 2:20 AM

Oct 4 2018

olista01 added a comment to D52829: [AArch64] Fix verifier error when outlining indirect calls.

I don't think adding a special case to the verifier makes sense, when it's easy enough to generate code which is valid by the normal rules.

Oct 4 2018, 2:22 AM
olista01 edited reviewers for D52829: [AArch64] Fix verifier error when outlining indirect calls, added: paquette; removed: jpaquette.
Oct 4 2018, 1:48 AM
olista01 edited reviewers for D52869: [AArch64][v8.5A] Don't create BR instructions in outliner when BTI enabled, added: paquette; removed: jpaquette.
Oct 4 2018, 1:48 AM
olista01 created D52869: [AArch64][v8.5A] Don't create BR instructions in outliner when BTI enabled.
Oct 4 2018, 1:36 AM
olista01 created D52868: [AArch64][v8.5A] Restrict indirect tail calls to use x16/17 only when using BTI.
Oct 4 2018, 1:36 AM
olista01 added reviewers for D52829: [AArch64] Fix verifier error when outlining indirect calls: t.p.northover, rengolin, LukeCheeseman.
Oct 4 2018, 1:36 AM
olista01 created D52867: [AArch64][v8.5A] Branch Target Identification code-generation pass.
Oct 4 2018, 1:32 AM

Oct 3 2018

olista01 created D52829: [AArch64] Fix verifier error when outlining indirect calls.
Oct 3 2018, 5:31 AM

Oct 2 2018

olista01 accepted D52737: [ARM] Emmit data symbol for constant pool data.

LGTM with one nit.

Oct 2 2018, 7:46 AM
olista01 added inline comments to D52737: [ARM] Emmit data symbol for constant pool data.
Oct 2 2018, 3:12 AM
olista01 committed rL343572: [AArch64][v8.5A] Add Memory Tagging instructions.
[AArch64][v8.5A] Add Memory Tagging instructions
Oct 2 2018, 3:07 AM
olista01 closed D52490: [AArch64][v8.5A] Add Memory Tagging instructions.
Oct 2 2018, 3:06 AM
olista01 committed rL343571: [AArch64][v8.5A] Add Memory Tagging system registers.
[AArch64][v8.5A] Add Memory Tagging system registers
Oct 2 2018, 2:56 AM
olista01 closed D52488: [AArch64][v8.5A] Add Memory Tagging system registers.
Oct 2 2018, 2:56 AM
olista01 committed rL343570: [AArch64][v8.5A] Add MTE system instructions.
[AArch64][v8.5A] Add MTE system instructions
Oct 2 2018, 2:50 AM
olista01 closed D52487: [AArch64][v8.5A] Add MTE system instructions.
Oct 2 2018, 2:50 AM
olista01 committed rC343566: [AArch64][v8.5A] Test clang option for the Memory Tagging Extension.
[AArch64][v8.5A] Test clang option for the Memory Tagging Extension
Oct 2 2018, 2:41 AM
olista01 committed rL343566: [AArch64][v8.5A] Test clang option for the Memory Tagging Extension.
[AArch64][v8.5A] Test clang option for the Memory Tagging Extension
Oct 2 2018, 2:41 AM
olista01 closed D52493: [AArch64][v8.5A] Test clang option for the Memory Tagging Extension.
Oct 2 2018, 2:41 AM
olista01 committed rL343563: [AArch64][v8.5A] Add MTE as an optional AArch64 extension.
[AArch64][v8.5A] Add MTE as an optional AArch64 extension
Oct 2 2018, 2:40 AM
olista01 closed D52486: [AArch64][v8.5A] Add MTE as an optional AArch64 extension.
Oct 2 2018, 2:40 AM
olista01 added inline comments to D52737: [ARM] Emmit data symbol for constant pool data.
Oct 2 2018, 1:44 AM
olista01 added a comment to D52486: [AArch64][v8.5A] Add MTE as an optional AArch64 extension.

Ping. This is the last patch for Armv8.5A (dis)assembler support which needs review, all of the ones adding the memory tagging instructions and registers are approved but depend on this one, and all of the other features are now committed.

Oct 2 2018, 12:48 AM

Sep 28 2018

olista01 committed rL343300: [ARM][v8.5A] Add speculation barriers SSBB and PSSBB.
[ARM][v8.5A] Add speculation barriers SSBB and PSSBB
Sep 28 2018, 1:31 AM
olista01 closed D52484: [ARM][v8.5A] Add speculation barriers SSBB and PSSBB.
Sep 28 2018, 1:31 AM

Sep 27 2018

olista01 committed rL343231: [AArch64] Refactor immediate details out of add/sub tblgen class (NFCI).
[AArch64] Refactor immediate details out of add/sub tblgen class (NFCI)
Sep 27 2018, 9:20 AM
olista01 closed D52489: [AArch64] Refactor immediate details out of add/sub tblgen class (NFCI).
Sep 27 2018, 9:20 AM
olista01 committed rL343229: [AArch64][v8.5A] Add speculation barriers SSBB and PSSBB.
[AArch64][v8.5A] Add speculation barriers SSBB and PSSBB
Sep 27 2018, 9:11 AM
olista01 closed D52483: [AArch64][v8.5A] Add speculation barriers SSBB and PSSBB.
Sep 27 2018, 9:11 AM
olista01 committed rL343225: [AArch64][v8.5A] Add Branch Target Identification instructions.
[AArch64][v8.5A] Add Branch Target Identification instructions
Sep 27 2018, 7:56 AM
olista01 closed D52485: [AArch64][v8.5A] Add Branch Target Identification instructions.
Sep 27 2018, 7:56 AM
olista01 added inline comments to D52483: [AArch64][v8.5A] Add speculation barriers SSBB and PSSBB.
Sep 27 2018, 7:41 AM
olista01 committed rL343220: [AArch64][v8.5A] Test optional Armv8.5-A random number extension.
[AArch64][v8.5A] Test optional Armv8.5-A random number extension
Sep 27 2018, 7:22 AM
olista01 committed rC343220: [AArch64][v8.5A] Test optional Armv8.5-A random number extension.
[AArch64][v8.5A] Test optional Armv8.5-A random number extension
Sep 27 2018, 7:22 AM
olista01 closed D52492: [AArch64][v8.5A] Test optional Armv8.5-A random number extension.
Sep 27 2018, 7:22 AM
olista01 committed rL343218: [AArch64][v8.5A] Add speculation restriction system registers.
[AArch64][v8.5A] Add speculation restriction system registers
Sep 27 2018, 7:09 AM
olista01 closed D52482: [AArch64][v8.5A] Add speculation restriction system registers.
Sep 27 2018, 7:09 AM
olista01 committed rL343217: [AArch64][v8.5A] Add Armv8.5-A random number instructions.
[AArch64][v8.5A] Add Armv8.5-A random number instructions
Sep 27 2018, 7:03 AM
olista01 closed D52481: [AArch64][v8.5A] Add Armv8.5-A random number instructions.
Sep 27 2018, 7:03 AM
olista01 committed rL343216: [AArch64][v8.5A] Add Armv8.5-A "DC CVADP" instruction.
[AArch64][v8.5A] Add Armv8.5-A "DC CVADP" instruction
Sep 27 2018, 6:56 AM
olista01 closed D52480: [AArch64][v8.5A] Add Armv8.5-A "DC CVADP" instruction.
Sep 27 2018, 6:56 AM
olista01 committed rL343214: [AArch64][v8.5A] Add prediction invalidation instructions to AArch64.
[AArch64][v8.5A] Add prediction invalidation instructions to AArch64
Sep 27 2018, 6:49 AM
olista01 closed D52479: [AArch64][v8.5A] Add prediction invalidation instructions to AArch64.
Sep 27 2018, 6:49 AM
olista01 committed rL343213: [ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction sets.
[ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction sets
Sep 27 2018, 6:43 AM
olista01 closed D52477: [ARM][v8.5A] Add speculation barrier to ARM & Thumb instruction sets.
Sep 27 2018, 6:43 AM
olista01 committed rL343211: [AArch64][v8.5A] Add speculation barrier to AArch64 instruction set.
[AArch64][v8.5A] Add speculation barrier to AArch64 instruction set
Sep 27 2018, 6:43 AM
olista01 closed D52476: [AArch64][v8.5A] Add speculation barrier to AArch64 instruction set.
Sep 27 2018, 6:43 AM
olista01 committed rL343209: [AArch64][v8.5A] Add FRINT[32,64][Z,X] instructions.
[AArch64][v8.5A] Add FRINT[32,64][Z,X] instructions
Sep 27 2018, 6:36 AM
olista01 closed D52475: [AArch64][v8.5A] Add FRINT[32,64][Z,X] instructions.
Sep 27 2018, 6:36 AM
olista01 updated the diff for D52475: [AArch64][v8.5A] Add FRINT[32,64][Z,X] instructions.

Rename feature to FeatureFRInt3264.

Sep 27 2018, 2:50 AM
olista01 added inline comments to D52475: [AArch64][v8.5A] Add FRINT[32,64][Z,X] instructions.
Sep 27 2018, 2:28 AM
olista01 committed rL343187: [AArch64][v8.5A] Add PSTATE manipulation instructions XAFlag and AXFlag.
[AArch64][v8.5A] Add PSTATE manipulation instructions XAFlag and AXFlag
Sep 27 2018, 2:13 AM
olista01 closed D52473: [AArch64][v8.5A] Add PSTATE manipulation instructions XAFlag and AXFlag.
Sep 27 2018, 2:13 AM

Sep 26 2018

olista01 committed rL343120: [AArch64] Extend single-operand FP insns to match Arm ARM (NFCI).
[AArch64] Extend single-operand FP insns to match Arm ARM (NFCI)
Sep 26 2018, 8:46 AM
olista01 closed D52474: [AArch64] Extend single-operand FP insns to match Arm ARM (NFCI).
Sep 26 2018, 8:46 AM