[RISCV] Generate PIC address sequence for medany -fno-pic

[jrtc27]

I am still of the view that we should support rewriting the instruction stream in the linker when necessary like BFD does. We need to do this to be able to link in GCC-compiled code, including libraries. It is a very simple thing to do with a patch available that provides consistency between the GNU world and the LLVM world.

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

680

This is confusing and differs from when you invoke the assembler manually, even via the Clang driver with the right code model specified. Any las there will be assembled as AUIPC/ADDI. I am of the view it was a mistake to make la's behaviour conditional on PICness and it should have always used the GOT, but this is what we have.

llvm/lib/Target/TargetMachine.cpp

192

Are we sure we want to do this and take the performance hit over GCC due to the extra level of indirection on every single extern global access? If this is the solution to take for extern weak, I think we should limit it to just that and have a separate discussion about non-extern-weak.

[MaskRay]

In D72056#1800524, @jrtc27 wrote:

I am still of the view that we should support rewriting the instruction stream in the linker when necessary like BFD does. We need to do this to be able to link in GCC-compiled code, including libraries. It is a very simple thing to do with a patch available that provides consistency between the GNU world and the LLVM world.

https://github.com/riscv/riscv-elf-psabi-doc/issues/126#issuecomment-570076329

[MaskRay]

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

680

I am of the view it was a mistake to make la's behaviour conditional on PICness and it should have always used the GOT, but this is what we have.

I agree with you. la's behavior should not be conditional on PIC. RISC-V probably should have a GOT relaxation mechanism. See my comment at https://github.com/riscv/riscv-elf-psabi-doc/issues/126

llvm/lib/Target/TargetMachine.cpp

192

I'd like to know more about -mcmodel=medany -fno-pic's use cases. I guess @bsdjhb's FreeBSD kernel use case can probably be met by -mcmodel=medany -fpie.

I think there is no precedent which differs extern-strong and extern-weak. If GOT relaxation works, we can make this unconditional.

// RISC-V prefer avoiding copy relocations.
if (TT.isRISCV()
  return false;

[jrtc27]

llvm/lib/Target/TargetMachine.cpp

192

It can, but that implies GOT accesses for anything extern, which will hurt kernel performance.

clang/lib/CodeGen/CodeGenModule.cpp

if (RM == llvm::Reloc::PIC_ && GV->hasExternalWeakLinkage())
     return false;
 
   // PPC has no copy relocations and cannot use a plt entry as a symbol address.
   llvm::Triple::ArchType Arch = TT.getArch();
   if (Arch == llvm::Triple::ppc || Arch == llvm::Triple::ppc64 ||
       Arch == llvm::Triple::ppc64le)
     return false;
 
+  // RISC-V non-small code models prefer avoiding copy relocations.
+  if (TT.isRISCV() && CGOpts.CodeModel != "small")
+    return false;
+
   // If we can use copy relocations we can assume it is local.
   if (auto *Var = dyn_cast<llvm::GlobalVariable>(GV))
     if (!Var->isThreadLocal() &&
         (RM == llvm::Reloc::Static || CGOpts.PIECopyRelocations))
       return true;
 
   // If we can use a plt entry as the symbol address we can assume it
   // is local.

llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

 
 bool RISCVExpandPseudo::expandLoadAddress(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
     MachineBasicBlock::iterator &NextMBBI) {
   MachineFunction *MF = MBB.getParent();
 
   unsigned SecondOpcode;
   unsigned FlagsHi;
-  if (MF->getTarget().isPositionIndependent()) {
+  if (MF->getTarget().isPositionIndependent() ||
+      MF->getTarget().getCodeModel() != CodeModel::Small) {
     const auto &STI = MF->getSubtarget<RISCVSubtarget>();
     SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
     FlagsHi = RISCVII::MO_GOT_HI;
   } else {
     SecondOpcode = RISCV::ADDI;
     FlagsHi = RISCVII::MO_PCREL_HI;
   }
   return expandAuipcInstPair(MBB, MBBI, NextMBBI, FlagsHi, SecondOpcode);

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

return DAG.getTargetConstantPool(N->getConstVal(), Ty, N->getAlignment(),
                                    N->getOffset(), Flags);
 }
 
 template <class NodeTy>
 SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
                                      bool IsLocal) const {
   SDLoc DL(N);
   EVT Ty = getPointerTy(DAG.getDataLayout());
+  CodeModel::Model M = getTargetMachine().getCodeModel();
+  if (M != CodeModel::Small && M != CodeModel::Medium)
+    report_fatal_error("Unsupported code model for lowering");
+
+  if (!isPositionIndependent() && M == CodeModel::Small) {
+    // Generate a sequence for accessing addresses within the first 2 GiB of
+    // address space. This generates the pattern (addi (lui %hi(sym)) %lo(sym)).
+    SDValue AddrHi = getTargetNode(N, DL, Ty, DAG, RISCVII::MO_HI);
+    SDValue AddrLo = getTargetNode(N, DL, Ty, DAG, RISCVII::MO_LO);
+    SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, AddrHi), 0);
+    return SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, AddrLo), 0);
+  }
 
-  if (isPositionIndependent()) {
-    SDValue Addr = getTargetNode(N, DL, Ty, DAG, 0);
-    if (IsLocal)
-      // Use PC-relative addressing to access the symbol. This generates the
-      // pattern (PseudoLLA sym), which expands to (addi (auipc %pcrel_hi(sym))
-      // %pcrel_lo(auipc)).
-      return SDValue(DAG.getMachineNode(RISCV::PseudoLLA, DL, Ty, Addr), 0);
 
-    // Use PC-relative addressing to access the GOT for this symbol, then load
-    // the address from the GOT. This generates the pattern (PseudoLA sym),
-    // which expands to (ld (addi (auipc %got_pcrel_hi(sym)) %pcrel_lo(auipc))).
-    return SDValue(DAG.getMachineNode(RISCV::PseudoLA, DL, Ty, Addr), 0);
-  }
 
-  switch (getTargetMachine().getCodeModel()) {
-  default:
-    report_fatal_error("Unsupported code model for lowering");
-  case CodeModel::Small: {
-    // Generate a sequence for accessing addresses within the first 2 GiB of
-    // address space. This generates the pattern (addi (lui %hi(sym)) %lo(sym)).
-    SDValue AddrHi = getTargetNode(N, DL, Ty, DAG, RISCVII::MO_HI);
-    SDValue AddrLo = getTargetNode(N, DL, Ty, DAG, RISCVII::MO_LO);
-    SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, AddrHi), 0);
-    return SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, AddrLo), 0);
-  }
-  case CodeModel::Medium: {
-    // Generate a sequence for accessing addresses within any 2GiB range within
-    // the address space. This generates the pattern (PseudoLLA sym), which
-    // expands to (addi (auipc %pcrel_hi(sym)) %pcrel_lo(auipc)).
-    SDValue Addr = getTargetNode(N, DL, Ty, DAG, 0);
-    return SDValue(DAG.getMachineNode(RISCV::PseudoLLA, DL, Ty, Addr), 0);
-  }
-  }
-}
-
 SDValue RISCVTargetLowering::lowerGlobalAddress(SDValue Op,
                                                 SelectionDAG &DAG) const {
   SDLoc DL(Op);
   EVT Ty = Op.getValueType();
   GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
   int64_t Offset = N->getOffset();
   MVT XLenVT = Subtarget.getXLenVT();
 

llvm/lib/Target/TargetMachine.cpp

if (IsExecutable) {
     const Function *F = dyn_cast_or_null<Function>(GV);
     if (F && F->hasFnAttribute(Attribute::NonLazyBind))
       return false;
     Triple::ArchType Arch = TT.getArch();
 
     // PowerPC prefers avoiding copy relocations.
     if (Arch == Triple::ppc || TT.isPPC64())
       return false;
+    // RISC-V non-small code models prefer avoiding copy relocations.
+    if (TT.isRISCV() && getCodeModel() != CodeModel::Small)
+      return false;
 
     // Check if we can use copy relocations.
     if (!(GV && GV->isThreadLocal()) && RM == Reloc::Static)
       return true;
   }
 
   // ELF & wasm support preemption of other symbols.
   return false;

llvm/test/CodeGen/RISCV/pic-models.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -relocation-model=static < %s \
 ; RUN:     | FileCheck -check-prefix=RV32-STATIC %s
 ; RUN: llc -mtriple=riscv32 -relocation-model=pic < %s \
 ; RUN:     | FileCheck -check-prefix=RV32-PIC %s
 ; RUN: llc -mtriple=riscv64 -relocation-model=static < %s \
 ; RUN:     | FileCheck -check-prefix=RV64-STATIC %s
 ; RUN: llc -mtriple=riscv64 -relocation-model=pic < %s \
 ; RUN:     | FileCheck -check-prefix=RV64-PIC %s
 
+;; Use PIC address sequence for medium code model, even if position dependent.
+; RUN: llc -mtriple=riscv64 -relocation-model=static -code-model=medium < %s \
+; RUN:     | FileCheck -check-prefix=RV64-PIC %s
+
 ; Check basic lowering of PIC addressing.
 ; TODO: Check other relocation models?
 
 @external_var = external global i32
 @internal_var = internal global i32 42
 
 
 ; external address