[Xtensa 1/10] Recognize Xtensa in triple parsing code.

[andreisfr]

Summary

I'm sharing initial set of patches that adds LLVM backend for Xtensa architecture. It is based on this LLVM fork https://github.com/espressif/llvm-xtensa. I prepared patches by similar way like it was already successfully done for RISCV, i.e. incrementally add an initial MC layer for Xtensa by small chunks which could be reviewable.

[aykevl]

Is there a reason why this hasn't been committed yet?

@andreisfr if you don't have commit access, you can indicate that here so that someone else can commit it for you.
For details: https://llvm.org/docs/Contributing.html#how-to-submit-a-patch

(I'm just very excited about having Xtensa support in LLVM).

[andreisfr]

@aykevl, I'm not sure whether we currently could upload patch 1/10, because there are some questions in patch 4/10 about ISA(we currently have just opensource projects and unofficial documents with Xtensa ISA description). You could participate in this discussion to move the Xtensa backend forward.

[arsenm]

I think the standard for what is committed for the triple is quite low. We already have out of tree targets included in the upstream triple, so it doesn't really matter what happens with the follow up patches. This should be fine to commit without waiting for the rest of the backend review

[andreisfr]

Patch is updated according to latest upstream version.

[andreisfr]

Patch is updated according to LLVM upstream version and latest Xtensa backend version.. Also updated CODE_OWNERS.txt.

[andreisfr]

Patch is updated according to LLVM upstream version

[andreisfr]

Patch is updated according to LLVM upstream version

[saugustine]

One minor nit, but otherwise this looks good.

llvm/include/llvm/ADT/Triple.h

88 ↗

(On Diff #425062)

Add a colon between Tensilica and Xtensa.

[andreisfr]

Minor changes: corrected comment.

[andreisfr]

llvm/include/llvm/ADT/Triple.h

88 ↗

(On Diff #425062)

Corrected

[andreisfr]

Updated according to latest changes in upstream source code

[sstefan1]

Hi everyone. Since this has been accepted for some time now, we're planning to commit this on Monday (December 16th). Please let us know if there is anything else we should address.

[MaskRay]

LGTM.

@sstefan1 consider test buildability of 3 build modes

• default
• -DBUILD_SHARED_LIBS=on
• -DLLVM_LINK_LLVM_DYLIB=on

(For all-but-one mode, just build, no need to test. Consider LIT_OPTS='--filter=nomatch --allow-empty-runs' ninja check-{llvm,clang,clang-tools,lldb})

For large patches which change a lot of the build system. I've seen many patches reverted and relanded because of some dependency issues.

If you want to test asan, use -DLLVM_USE_SANITIZER=Address -DLLVM_ENABLE_RUNTIMES=

[andreisfr]

Updated according to latest changes in upstream source code

[andreisfr]

Updated according to latest changes in upstream source code

llvm/CODE_OWNERS.TXT

 N: Paul Robinson
 E: [e-mail]
 D: Sony PlayStation®4 support
 
 N: Chad Rosier
 E: [e-mail]
 D: Fast-Isel
 
+N: Andrei Safronov
+E: [e-mail]
+D: Xtensa backend (lib/Target/Xtensa/*)
+
 N: Duncan Sands
 E: [e-mail]
 D: DragonEgg
 
 N: Mark Schimmel
 E: [e-mail]
 D: ARC backend (lib/Target/ARC/*)
 

llvm/include/llvm/TargetParser/Triple.h

enum ArchType {
     systemz,        // SystemZ: s390x
     tce,            // TCE (http://tce.cs.tut.fi/): tce
     tcele,          // TCE little endian (http://tce.cs.tut.fi/): tcele
     thumb,          // Thumb (little endian): thumb, thumbv.*
     thumbeb,        // Thumb (big endian): thumbeb
     x86,            // X86: i[3-9]86
     x86_64,         // X86-64: amd64, x86_64
     xcore,          // XCore: xcore
+    xtensa,         // Tensilica: Xtensa
     nvptx,          // NVPTX: 32-bit
     nvptx64,        // NVPTX: 64-bit
     le32,           // le32: generic little-endian 32-bit CPU (PNaCl)
     le64,           // le64: generic little-endian 64-bit CPU (PNaCl)
     amdil,          // AMDIL
     amdil64,        // AMDIL with 64-bit pointers
     hsail,          // AMD HSAIL
     hsail64,        // AMD HSAIL with 64-bit pointers

llvm/lib/TargetParser/Triple.cpp

StringRef Triple::getArchTypeName(ArchType Kind) {
   case thumb:          return "thumb";
   case thumbeb:        return "thumbeb";
   case ve:             return "ve";
   case wasm32:         return "wasm32";
   case wasm64:         return "wasm64";
   case x86:            return "i386";
   case x86_64:         return "x86_64";
   case xcore:          return "xcore";
+  case xtensa:         return "xtensa";
   }
 
   llvm_unreachable("Invalid ArchType!");
 }
 
 StringRef Triple::getArchTypePrefix(ArchType Kind) {
   switch (Kind) {
   default:
StringRef Triple::getArchTypePrefix(ArchType Kind) {
 
   case ve:          return "ve";
   case csky:        return "csky";
 
   case loongarch32:
   case loongarch64: return "loongarch";
 
   case dxil:        return "dx";
+
+  case xtensa:      return "xtensa";
   }
 }
 
 StringRef Triple::getVendorTypeName(VendorType Kind) {
   switch (Kind) {
   case UnknownVendor: return "unknown";
 
   case AMD: return "amd";
return StringSwitch<Triple::ArchType>(Name)
     .Case("wasm64", wasm64)
     .Case("renderscript32", renderscript32)
     .Case("renderscript64", renderscript64)
     .Case("ve", ve)
     .Case("csky", csky)
     .Case("loongarch32", loongarch32)
     .Case("loongarch64", loongarch64)
     .Case("dxil", dxil)
+    .Case("xtensa", xtensa)
     .Default(UnknownArch);
 }
 
 static Triple::ArchType parseARMArch(StringRef ArchName) {
   ARM::ISAKind ISA = ARM::parseArchISA(ArchName);
   ARM::EndianKind ENDIAN = ARM::parseArchEndian(ArchName);
 
   Triple::ArchType arch = Triple::UnknownArch;
auto AT = StringSwitch<Triple::ArchType>(ArchName)
     .Case("shave", Triple::shave)
     .Case("ve", Triple::ve)
     .Case("wasm32", Triple::wasm32)
     .Case("wasm64", Triple::wasm64)
     .Case("csky", Triple::csky)
     .Case("loongarch32", Triple::loongarch32)
     .Case("loongarch64", Triple::loongarch64)
     .Case("dxil", Triple::dxil)
+    .Case("xtensa", Triple::xtensa)
     .Default(Triple::UnknownArch);
 
   // Some architectures require special parsing logic just to compute the
   // ArchType result.
   if (AT == Triple::UnknownArch) {
     if (ArchName.startswith("arm") || ArchName.startswith("thumb") ||
         ArchName.startswith("aarch64"))
       return parseARMArch(ArchName);
static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
   case Triple::sparcv9:
   case Triple::spir64:
   case Triple::spir:
   case Triple::tce:
   case Triple::tcele:
   case Triple::thumbeb:
   case Triple::ve:
   case Triple::xcore:
+  case Triple::xtensa:
     return Triple::ELF;
 
   case Triple::ppc64:
   case Triple::ppc:
     if (T.isOSAIX())
       return Triple::XCOFF;
     return Triple::ELF;
 
static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
   case llvm::Triple::spirv32:
   case llvm::Triple::tce:
   case llvm::Triple::tcele:
   case llvm::Triple::thumb:
   case llvm::Triple::thumbeb:
   case llvm::Triple::wasm32:
   case llvm::Triple::x86:
   case llvm::Triple::xcore:
+  case llvm::Triple::xtensa:
     return 32;
 
   case llvm::Triple::aarch64:
   case llvm::Triple::aarch64_be:
   case llvm::Triple::amdgcn:
   case llvm::Triple::amdil64:
   case llvm::Triple::bpfeb:
   case llvm::Triple::bpfel:
Triple Triple::get32BitArchVariant() const {
   case Triple::spirv32:
   case Triple::tce:
   case Triple::tcele:
   case Triple::thumb:
   case Triple::thumbeb:
   case Triple::wasm32:
   case Triple::x86:
   case Triple::xcore:
+  case Triple::xtensa:
     // Already 32-bit.
     break;
 
   case Triple::aarch64:        T.setArch(Triple::arm);     break;
   case Triple::aarch64_be:     T.setArch(Triple::armeb);   break;
   case Triple::amdil64:        T.setArch(Triple::amdil);   break;
   case Triple::hsail64:        T.setArch(Triple::hsail);   break;
   case Triple::le64:           T.setArch(Triple::le32);    break;
Triple Triple::get64BitArchVariant() const {
   case Triple::m68k:
   case Triple::msp430:
   case Triple::r600:
   case Triple::shave:
   case Triple::sparcel:
   case Triple::tce:
   case Triple::tcele:
   case Triple::xcore:
+  case Triple::xtensa:
     T.setArch(UnknownArch);
     break;
 
   case Triple::aarch64:
   case Triple::aarch64_be:
   case Triple::amdgcn:
   case Triple::amdil64:
   case Triple::bpfeb:
Triple Triple::getBigEndianArchVariant() const {
   case Triple::spirv64:
   case Triple::wasm32:
   case Triple::wasm64:
   case Triple::x86:
   case Triple::x86_64:
   case Triple::xcore:
   case Triple::ve:
   case Triple::csky:
+  case Triple::xtensa:
 
   // ARM is intentionally unsupported here, changing the architecture would
   // drop any arch suffixes.
   case Triple::arm:
   case Triple::thumb:
     T.setArch(UnknownArch);
     break;
 
bool Triple::isLittleEndian() const {
   case Triple::tcele:
   case Triple::thumb:
   case Triple::ve:
   case Triple::wasm32:
   case Triple::wasm64:
   case Triple::x86:
   case Triple::x86_64:
   case Triple::xcore:
+  case Triple::xtensa:
     return true;
   default:
     return false;
   }
 }
 
 bool Triple::isCompatibleWith(const Triple &Other) const {
   // ARM and Thumb triples are compatible, if subarch, vendor and OS match.

llvm/unittests/TargetParser/TripleTest.cpp

TEST(TripleTest, ParsedIDs) {
 
   T = Triple("dxil-unknown-shadermodel-amplification");
   EXPECT_EQ(Triple::dxil, T.getArch());
   EXPECT_EQ(Triple::UnknownVendor, T.getVendor());
   EXPECT_EQ(Triple::ShaderModel, T.getOS());
   EXPECT_EQ(Triple::Amplification, T.getEnvironment());
   EXPECT_FALSE(T.supportsCOMDAT());
 
+  T = Triple("xtensa");
+  EXPECT_EQ(Triple::xtensa, T.getArch());
+  EXPECT_EQ(Triple::UnknownVendor, T.getVendor());
+  EXPECT_EQ(Triple::UnknownOS, T.getOS());
+  EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
+
+  T = Triple("xtensa-unknown-unknown");
+  EXPECT_EQ(Triple::xtensa, T.getArch());
+  EXPECT_EQ(Triple::UnknownVendor, T.getVendor());
+  EXPECT_EQ(Triple::UnknownOS, T.getOS());
+  EXPECT_EQ(Triple::UnknownEnvironment, T.getEnvironment());
+
   T = Triple("huh");
   EXPECT_EQ(Triple::UnknownArch, T.getArch());
 }
 
 static std::string Join(StringRef A, StringRef B, StringRef C) {
   std::string Str = std::string(A);
   Str += '-';
   Str += B;
TEST(TripleTest, BitWidthPredicates) {
   EXPECT_TRUE(T.isArch64Bit());
   EXPECT_TRUE(T.isLoongArch());
 
   T.setArch(Triple::dxil);
   EXPECT_FALSE(T.isArch16Bit());
   EXPECT_TRUE(T.isArch32Bit());
   EXPECT_FALSE(T.isArch64Bit());
   EXPECT_TRUE(T.isDXIL());
+
+  T.setArch(Triple::xtensa);
+  EXPECT_FALSE(T.isArch16Bit());
+  EXPECT_TRUE(T.isArch32Bit());
+  EXPECT_FALSE(T.isArch64Bit());
 }
 
 TEST(TripleTest, BitWidthArchVariants) {
   Triple T;
   EXPECT_EQ(Triple::UnknownArch, T.get32BitArchVariant().getArch());
   EXPECT_EQ(Triple::UnknownArch, T.get64BitArchVariant().getArch());
 
   T.setArch(Triple::UnknownArch);
TEST(TripleTest, BitWidthArchVariants) {
 
   T.setArch(Triple::xcore);
   EXPECT_EQ(Triple::xcore, T.get32BitArchVariant().getArch());
   EXPECT_EQ(Triple::UnknownArch, T.get64BitArchVariant().getArch());
 
   T.setArch(Triple::dxil);
   EXPECT_EQ(Triple::dxil, T.get32BitArchVariant().getArch());
   EXPECT_EQ(Triple::UnknownArch, T.get64BitArchVariant().getArch());
+
+  T.setArch(Triple::xtensa);
+  EXPECT_EQ(Triple::xtensa, T.get32BitArchVariant().getArch());
+  EXPECT_EQ(Triple::UnknownArch, T.get64BitArchVariant().getArch());
 }
 
 TEST(TripleTest, EndianArchVariants) {
   Triple T;
   EXPECT_EQ(Triple::UnknownArch, T.getBigEndianArchVariant().getArch());
   EXPECT_EQ(Triple::UnknownArch, T.getLittleEndianArchVariant().getArch());
 
   T.setArch(Triple::UnknownArch);