[ARM] Add remaining miscellaneous MVE instructions.

[simon_tatham]

Summary

This final batch includes the tail-predicated versions of the
low-overhead loop instructions (LETP); the VPSEL instruction to select
between two vector registers based on the predicate mask without
having to open a VPT block; and VPNOT which complements the predicate
mask in place.

[simon_tatham]

Remastered patch to apply cleanly against current trunk.

[simon_tatham]

Updated instruction spellings in line with intended consistent MVE practice, and also reworked the WLSTP/DLSTP and LETP/LCTP definitions to remove pointless !if from the base classes. (In particular, the instructions that don't have a label field in the encoding now don't have one in their Tablegen defs either.)

[ostannard]

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

7748

It would be better to do these as checks on the operands, rather than the whole instruction.

llvm/test/MC/ARM/mve-misc.s

2

If nothing is expected to vary between the FP and no-FP cases, the check lines can be merged, and the errors checked for both cases.

17

Are these instructions expected to work with label operands now (in which case that should be tested), or is that coming in a later patch?

[simon_tatham]

llvm/test/MC/ARM/mve-misc.s

17

Yes, they are; tests added.

[simon_tatham]

Addressed all review comments.

[ostannard]

LGTM

llvm/lib/Target/ARM/ARMInstrMVE.td

def MVE_VPST : MVE_MI<(outs ), (ins vpt_mask:$Mk), NoItinerary,
   let Inst{15-13} = Mk{2-0};
   let Inst{12-0} = 0b0111101001101;
   let Unpredictable{12} = 0b1;
   let Unpredictable{7} = 0b1;
   let Unpredictable{5} = 0b1;
 
   let Defs = [P0];
 }
+
+def MVE_VPSEL : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), NoItinerary,
+                      "vpsel", "", "$Qd, $Qn, $Qm", vpred_n, "", []> {
+  bits<4> Qn;
+  bits<4> Qd;
+  bits<4> Qm;
+
+  let Inst{28} = 0b1;
+  let Inst{25-23} = 0b100;
+  let Inst{22} = Qd{3};
+  let Inst{21-20} = 0b11;
+  let Inst{19-17} = Qn{2-0};
+  let Inst{16} = 0b1;
+  let Inst{15-13} = Qd{2-0};
+  let Inst{12-9} = 0b0111;
+  let Inst{8} = 0b1;
+  let Inst{7} = Qn{3};
+  let Inst{6} = 0b0;
+  let Inst{5} = Qm{3};
+  let Inst{4} = 0b0;
+  let Inst{3-1} = Qm{2-0};
+  let Inst{0} = 0b1;
+}
+
+foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32",
+                  "i8", "i16", "i32",       "f16", "f32"] in
+def : MVEInstAlias<"vpsel${vp}." # suffix # "\t$Qd, $Qn, $Qm",
+                   (MVE_VPSEL MQPR:$Qd, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
+
+def MVE_VPNOT : MVE_p<(outs), (ins), NoItinerary,
+                      "vpnot", "", "", vpred_n, "", []> {
+  let Inst{31-0} = 0b11111110001100010000111101001101;
+  let Unpredictable{19-17} = 0b111;
+  let Unpredictable{12} = 0b1;
+  let Unpredictable{7} = 0b1;
+  let Unpredictable{5} = 0b1;
+  let Defs = [P0];
+  let Uses = [P0];
+
+  let Constraints = "";
+}
+
+class MVE_loltp_start<dag iops, string asm, string ops, bits<2> size>
+  : t2LOL<(outs GPRlr:$LR), iops, asm, ops> {
+  bits<4> Rn;
+  let Predicates = [HasMVEInt];
+  let Inst{22} = 0b0;
+  let Inst{21-20} = size;
+  let Inst{19-16} = Rn{3-0};
+  let Inst{12} = 0b0;
+}
+
+class MVE_DLSTP<string asm, bits<2> size>
+  : MVE_loltp_start<(ins rGPR:$Rn), asm, "$LR, $Rn", size> {
+  let Inst{13} = 0b1;
+  let Inst{11-1} = 0b00000000000;
+  let Unpredictable{10-1} = 0b1111111111;
+}
+
+class MVE_WLSTP<string asm, bits<2> size>
+  : MVE_loltp_start<(ins rGPR:$Rn, wlslabel_u11:$label),
+                    asm, "$LR, $Rn, $label", size> {
+  bits<11> label;
+  let Inst{13} = 0b0;
+  let Inst{11} = label{0};
+  let Inst{10-1} = label{10-1};
+}
+
+def MVE_DLSTP_8  : MVE_DLSTP<"dlstp.8",  0b00>;
+def MVE_DLSTP_16 : MVE_DLSTP<"dlstp.16", 0b01>;
+def MVE_DLSTP_32 : MVE_DLSTP<"dlstp.32", 0b10>;
+def MVE_DLSTP_64 : MVE_DLSTP<"dlstp.64", 0b11>;
+
+def MVE_WLSTP_8  : MVE_WLSTP<"wlstp.8",  0b00>;
+def MVE_WLSTP_16 : MVE_WLSTP<"wlstp.16", 0b01>;
+def MVE_WLSTP_32 : MVE_WLSTP<"wlstp.32", 0b10>;
+def MVE_WLSTP_64 : MVE_WLSTP<"wlstp.64", 0b11>;
+
+class MVE_loltp_end<dag oops, dag iops, string asm, string ops>
+  : t2LOL<oops, iops, asm, ops> {
+  let Predicates = [HasMVEInt];
+  let Inst{22-21} = 0b00;
+  let Inst{19-16} = 0b1111;
+  let Inst{12} = 0b0;
+}
+
+def MVE_LETP : MVE_loltp_end<(outs GPRlr:$LRout),
+                             (ins GPRlr:$LRin, lelabel_u11:$label),
+                             "letp", "$LRin, $label"> {
+  bits<11> label;
+  let Inst{20} = 0b1;
+  let Inst{13} = 0b0;
+  let Inst{11} = label{0};
+  let Inst{10-1} = label{10-1};
+}
+
+def MVE_LCTP : MVE_loltp_end<(outs), (ins pred:$p), "lctp${p}", ""> {
+  let Inst{20} = 0b0;
+  let Inst{13} = 0b1;
+  let Inst{11-1} = 0b00000000000;
+  let Unpredictable{21-20} = 0b11;
+  let Unpredictable{11-1} = 0b11111111111;
+}

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
         (Mnemonic == "vmine" ||
          Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt" ||
          Mnemonic == "vrshle" || Mnemonic == "vrshlt" ||
          Mnemonic == "vmvne" || Mnemonic == "vorne" ||
          Mnemonic == "vnege" || Mnemonic == "vnegt" ||
          Mnemonic == "vmule" || Mnemonic == "vmult" ||
          Mnemonic == "vrintne" ||
          Mnemonic == "vcmult" || Mnemonic == "vcmule" ||
+         Mnemonic == "vpsele" || Mnemonic == "vpselt" ||
          Mnemonic.startswith("vq")))) {
     unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
     if (CC != ~0U) {
       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
       PredicationCode = CC;
     }
   }
 
StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
   }
 
   if (isMnemonicVPTPredicable(Mnemonic, ExtraToken) && Mnemonic != "vmovlt" &&
       Mnemonic != "vshllt" && Mnemonic != "vrshrnt" && Mnemonic != "vshrnt" &&
       Mnemonic != "vqrshrunt" && Mnemonic != "vqshrunt" &&
       Mnemonic != "vqrshrnt" && Mnemonic != "vqshrnt" && Mnemonic != "vmullt" &&
       Mnemonic != "vqmovnt" && Mnemonic != "vqmovunt" &&
       Mnemonic != "vqmovnt" && Mnemonic != "vmovnt" && Mnemonic != "vqdmullt" &&
-      Mnemonic != "vcvtt" && Mnemonic != "vcvt") {
+      Mnemonic != "vpnot" && Mnemonic != "vcvtt" && Mnemonic != "vcvt") {
     unsigned CC = ARMVectorCondCodeFromString(Mnemonic.substr(Mnemonic.size()-1));
     if (CC != ~0U) {
       Mnemonic = Mnemonic.slice(0, Mnemonic.size()-1);
       VPTPredicationCode = CC;
     }
     return Mnemonic;
   }
 
if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
       Mnemonic == "bfcsel" || Mnemonic == "wls" ||
       Mnemonic == "dls" || Mnemonic == "le" || Mnemonic == "csel" ||
       Mnemonic == "csinc" || Mnemonic == "csinv" || Mnemonic == "csneg" ||
       Mnemonic == "cinc" || Mnemonic == "cinv" || Mnemonic == "cneg" ||
       Mnemonic == "cset" || Mnemonic == "csetm" ||
       Mnemonic.startswith("vpt") || Mnemonic.startswith("vpst") ||
       (hasMVE() &&
        (Mnemonic.startswith("vst2") || Mnemonic.startswith("vld2") ||
-        Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4")))) {
+        Mnemonic.startswith("vst4") || Mnemonic.startswith("vld4") ||
+        Mnemonic.startswith("wlstp") || Mnemonic.startswith("dlstp") ||
+        Mnemonic.startswith("letp")))) {
     // These mnemonics are never predicable
     CanAcceptPredicationCode = false;
   } else if (!isThumb()) {
     // Some instructions are only predicable in Thumb mode
     CanAcceptPredicationCode =
         Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
         Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
         Mnemonic != "dmb" && Mnemonic != "dfb" && Mnemonic != "dsb" &&
bool ARMAsmParser::shouldOmitVectorPredicateOperand(StringRef Mnemonic,
                                                     OperandVector &Operands) {
   if (!hasMVE() || Operands.size() < 3)
     return true;
 
   if (Mnemonic.startswith("vld2") || Mnemonic.startswith("vld4") ||
       Mnemonic.startswith("vst2") || Mnemonic.startswith("vst4"))
     return true;
 
-  if (Mnemonic.startswith("vctp"))
+  if (Mnemonic.startswith("vctp") || Mnemonic.startswith("vpnot"))
     return false;
 
   if (Mnemonic.startswith("vmov") &&
       !(Mnemonic.startswith("vmovl") || Mnemonic.startswith("vmovn") ||
         Mnemonic.startswith("vmovx"))) {
     for (auto &Operand : Operands) {
       if (static_cast<ARMOperand &>(*Operand).isVectorIndex() ||
           ((*Operand).isReg() &&
if (Imm8 == 0x10 && Pred != ARMCC::AL && hasRAS())
                                                "predicable, but condition "
                                                "code specified");
     if (Imm8 == 0x14 && Pred != ARMCC::AL)
       return Error(Operands[1]->getStartLoc(), "instruction 'csdb' is not "
                                                "predicable, but condition "
                                                "code specified");
     break;
   }
-  case ARM::t2WLS: {
+  case ARM::t2WLS:
+  case ARM::MVE_WLSTP_8:
+  case ARM::MVE_WLSTP_16:
+  case ARM::MVE_WLSTP_32:
+  case ARM::MVE_WLSTP_64: {
     int idx = Opcode == ARM::t2WLS ? 3 : 4;
     if (!static_cast<ARMOperand &>(*Operands[idx]).isUnsignedOffset<11, 1>())
       return Error(Operands[idx]->getStartLoc(),
                    "loop end is out of range or not a positive multiple of 2");
     break;
   }
-  case ARM::t2LEUpdate: {
+  case ARM::t2LEUpdate:
+  case ARM::MVE_LETP: {
     if (Inst.getOperand(2).isImm() &&
         !(Inst.getOperand(2).getImm() < 0 &&
           Inst.getOperand(2).getImm() >= -4094 &&
           (Inst.getOperand(2).getImm() & 1) == 0))
       return Error(Operands[2]->getStartLoc(),
                    "loop start is out of range or not a negative multiple of 2");
     break;
   }

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
   Inst.addOperand(MCOperand::createImm(Val));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
                                  const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
+  if (Inst.getOpcode() == ARM::MVE_LCTP)
+    return S;
+
   unsigned Imm = fieldFromInstruction(Insn, 11, 1) |
                  fieldFromInstruction(Insn, 1, 10) << 1;
   switch (Inst.getOpcode()) {
   case ARM::t2LEUpdate:
+  case ARM::MVE_LETP:
     Inst.addOperand(MCOperand::createReg(ARM::LR));
     Inst.addOperand(MCOperand::createReg(ARM::LR));
     LLVM_FALLTHROUGH;
   case ARM::t2LE:
     if (!Check(S, DecodeBFLabelOperand<false, true, 11>(Inst, Imm, Address,
                                                         Decoder)))
       return MCDisassembler::Fail;
     break;
   case ARM::t2WLS:
+  case ARM::MVE_WLSTP_8:
+  case ARM::MVE_WLSTP_16:
+  case ARM::MVE_WLSTP_32:
+  case ARM::MVE_WLSTP_64:
     Inst.addOperand(MCOperand::createReg(ARM::LR));
     if (!Check(S,
                DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4),
                                        Address, Decoder)) ||
         !Check(S, DecodeBFLabelOperand<false, false, 11>(Inst, Imm, Address,
                                                          Decoder)))
       return MCDisassembler::Fail;
     break;
   case ARM::t2DLS:
+  case ARM::MVE_DLSTP_8:
+  case ARM::MVE_DLSTP_16:
+  case ARM::MVE_DLSTP_32:
+  case ARM::MVE_DLSTP_64:
     unsigned Rn = fieldFromInstruction(Insn, 16, 4);
     if (Rn == 0xF) {
-      return MCDisassembler::Fail;
+      // Enforce all the rest of the instruction bits in LCTP, which
+      // won't have been reliably checked based on LCTP's own tablegen
+      // record, because we came to this decode by a roundabout route.
+      uint32_t CanonicalLCTP = 0xF00FE001, SBZMask = 0x00300FFE;
+      if ((Insn & ~SBZMask) != CanonicalLCTP)
+        return MCDisassembler::Fail;   // a mandatory bit is wrong: hard fail
+      if (Insn != CanonicalLCTP)
+        Check(S, MCDisassembler::SoftFail); // an SBZ bit is wrong: soft fail
+
+      Inst.setOpcode(ARM::MVE_LCTP);
     } else {
       Inst.addOperand(MCOperand::createReg(ARM::LR));
       if (!Check(S, DecoderGPRRegisterClass(Inst,
                                             fieldFromInstruction(Insn, 16, 4),
                                             Address, Decoder)))
         return MCDisassembler::Fail;
     }
     break;

llvm/test/MC/ARM/mve-misc.s

+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding  < %s \
+# RUN:   | FileCheck --check-prefix=CHECK-NOFP %s
+# RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding  < %s 2>%t \
+# RUN:   | FileCheck --check-prefix=CHECK %s
+# RUN:     FileCheck --check-prefix=ERROR < %t %s
+
+# CHECK: vpsel   q0, q5, q2  @ encoding: [0x3b,0xfe,0x05,0x0f]
+# CHECK-NOFP: vpsel   q0, q5, q2  @ encoding: [0x3b,0xfe,0x05,0x0f]
+vpsel   q0, q5, q2
+
+# CHECK: vpnot  @ encoding: [0x31,0xfe,0x4d,0x0f]
+# CHECK-NOFP: vpnot  @ encoding: [0x31,0xfe,0x4d,0x0f]
+vpnot
+
+# CHECK: wlstp.8     lr, r0, #1668  @ encoding: [0x00,0xf0,0x43,0xc3]
+# CHECK-NOFP: wlstp.8     lr, r0, #1668  @ encoding: [0x00,0xf0,0x43,0xc3]
+wlstp.8     lr, r0, #1668
+
+# CHECK: wlstp.16     lr, r0, #1668  @ encoding: [0x10,0xf0,0x43,0xc3]
+# CHECK-NOFP: wlstp.16     lr, r0, #1668  @ encoding: [0x10,0xf0,0x43,0xc3]
+wlstp.16     lr, r0, #1668
+
+# CHECK: wlstp.32     lr, r4, #2706  @ encoding: [0x24,0xf0,0x49,0xcd]
+# CHECK-NOFP: wlstp.32     lr, r4, #2706  @ encoding: [0x24,0xf0,0x49,0xcd]
+wlstp.32     lr, r4, #2706
+
+# CHECK: wlstp.64     lr, lr, #3026  @ encoding: [0x3e,0xf0,0xe9,0xcd]
+# CHECK-NOFP: wlstp.64     lr, lr, #3026  @ encoding: [0x3e,0xf0,0xe9,0xcd]
+wlstp.64     lr, lr, #3026
+
+# CHECK: wlstp.8     lr, r5, #3436  @ encoding: [0x05,0xf0,0xb7,0xc6]
+# CHECK-NOFP: wlstp.8     lr, r5, #3436  @ encoding: [0x05,0xf0,0xb7,0xc6]
+wlstp.8     lr, r5, #3436
+
+# CHECK: wlstp.16     lr, r1, #1060  @ encoding: [0x11,0xf0,0x13,0xc2]
+# CHECK-NOFP: wlstp.16     lr, r1, #1060  @ encoding: [0x11,0xf0,0x13,0xc2]
+wlstp.16     lr, r1, #1060
+
+# CHECK: wlstp.32     lr, r7, #4036  @ encoding: [0x27,0xf0,0xe3,0xc7]
+# CHECK-NOFP: wlstp.32     lr, r7, #4036  @ encoding: [0x27,0xf0,0xe3,0xc7]
+wlstp.32     lr, r7, #4036
+
+# CHECK: wlstp.8     lr, r1, #538  @ encoding: [0x01,0xf0,0x0d,0xc9]
+# CHECK-NOFP: wlstp.8     lr, r1, #538  @ encoding: [0x01,0xf0,0x0d,0xc9]
+wlstp.8     lr, r1, #538
+
+# CHECK: wlstp.8     lr, r10, #1404  @ encoding: [0x0a,0xf0,0xbf,0xc2]
+# CHECK-NOFP: wlstp.8     lr, r10, #1404  @ encoding: [0x0a,0xf0,0xbf,0xc2]
+wlstp.8     lr, r10, #1404
+
+# CHECK: wlstp.8     lr, r10, #1408  @ encoding: [0x0a,0xf0,0xc1,0xc2]
+# CHECK-NOFP: wlstp.8     lr, r10, #1408  @ encoding: [0x0a,0xf0,0xc1,0xc2]
+wlstp.8     lr, r10, #1408
+
+# CHECK: wlstp.8     lr, r10, #2358  @ encoding: [0x0a,0xf0,0x9b,0xcc]
+# CHECK-NOFP: wlstp.8     lr, r10, #2358  @ encoding: [0x0a,0xf0,0x9b,0xcc]
+wlstp.8     lr, r10, #2358
+
+# CHECK: wlstp.8     lr, r10, #4086  @ encoding: [0x0a,0xf0,0xfb,0xcf]
+# CHECK-NOFP: wlstp.8     lr, r10, #4086  @ encoding: [0x0a,0xf0,0xfb,0xcf]
+wlstp.8     lr, r10, #4086
+
+# CHECK: wlstp.8     lr, r11, #1442  @ encoding: [0x0b,0xf0,0xd1,0xca]
+# CHECK-NOFP: wlstp.8     lr, r11, #1442  @ encoding: [0x0b,0xf0,0xd1,0xca]
+wlstp.8     lr, r11, #1442
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: loop end is out of range or not a positive multiple of 2
+wlstp.8     lr, r10, #1443
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: loop end is out of range or not a positive multiple of 2
+wlstp.8     lr, r10, #4096
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
+wlstp.8     lr, sp, #1442
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
+wlstp.16     lr, sp, #1442
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+wlstp.32     r10, r11, #1442
+
+# CHECK: dlstp.8     lr, r5  @ encoding: [0x05,0xf0,0x01,0xe0]
+# CHECK-NOFP: dlstp.8     lr, r5  @ encoding: [0x05,0xf0,0x01,0xe0]
+dlstp.8     lr, r5
+
+# CHECK: dlstp.16     lr, r5  @ encoding: [0x15,0xf0,0x01,0xe0]
+# CHECK-NOFP: dlstp.16     lr, r5  @ encoding: [0x15,0xf0,0x01,0xe0]
+dlstp.16     lr, r5
+
+# CHECK: dlstp.32     lr, r7  @ encoding: [0x27,0xf0,0x01,0xe0]
+# CHECK-NOFP: dlstp.32     lr, r7  @ encoding: [0x27,0xf0,0x01,0xe0]
+dlstp.32     lr, r7
+
+# CHECK: dlstp.64     lr, r2  @ encoding: [0x32,0xf0,0x01,0xe0]
+# CHECK-NOFP: dlstp.64     lr, r2  @ encoding: [0x32,0xf0,0x01,0xe0]
+dlstp.64     lr, r2
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
+dlstp.64     lr, sp
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+dlstp.64     r10, r0
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: operand must be a register in range [r0, r12] or r14
+dlstp.64     lr, pc
+
+# CHECK: letp lr, #-2 @ encoding: [0x1f,0xf0,0x01,0xc8]
+# CHECK-NOFP: letp lr, #-2 @ encoding: [0x1f,0xf0,0x01,0xc8]
+letp lr, #-2
+
+# CHECK: letp lr, #-8 @ encoding: [0x1f,0xf0,0x05,0xc0]
+# CHECK-NOFP: letp lr, #-8 @ encoding: [0x1f,0xf0,0x05,0xc0]
+letp lr, #-8
+
+# CHECK: letp lr, #-4094 @ encoding: [0x1f,0xf0,0xff,0xcf]
+# CHECK-NOFP: letp lr, #-4094 @ encoding: [0x1f,0xf0,0xff,0xcf]
+letp lr, #-4094
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: invalid operand for instruction
+letp r0, #-8
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: loop start is out of range or not a negative multiple of 2
+letp lr, #8
+
+# ERROR: [[@LINE+1]]:{{[0-9]+}}: {{error|note}}: loop start is out of range or not a negative multiple of 2
+letp lr, #-4096
+
+# CHECK: lctp @ encoding: [0x0f,0xf0,0x01,0xe0]
+# CHECK-NOFP: lctp @ encoding: [0x0f,0xf0,0x01,0xe0]
+lctp
+
+# CHECK: it eq @ encoding: [0x08,0xbf]
+# CHECK-NOFP: it eq @ encoding: [0x08,0xbf]
+it eq
+# CHECK: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0]
+# CHECK-NOFP: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0]
+lctpeq
+
+vpste
+vpselt.s16 q0, q1, q2
+vpsele.i32 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vpselt q0, q1, q2 @ encoding: [0x33,0xfe,0x05,0x0f]
+# CHECK-NOFP: vpselt q0, q1, q2 @ encoding: [0x33,0xfe,0x05,0x0f]
+# CHECK: vpsele q0, q1, q2 @ encoding: [0x33,0xfe,0x05,0x0f]
+# CHECK-NOFP: vpsele q0, q1, q2 @ encoding: [0x33,0xfe,0x05,0x0f]

llvm/test/MC/Disassembler/ARM/mve-misc.txt

+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s 2> %t | FileCheck %s
+# RUN: FileCheck --check-prefix=ERROR < %t %s
+# RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
+# RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
+
+# CHECK: vpsel   q0, q5, q2  @ encoding: [0x3b,0xfe,0x05,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x3b,0xfe,0x05,0x0f]
+
+# CHECK: vpnot  @ encoding: [0x31,0xfe,0x4d,0x0f]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x31,0xfe,0x4d,0x0f]
+
+# CHECK: wlstp.8     lr, r0, #1668  @ encoding: [0x00,0xf0,0x43,0xc3]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x00,0xf0,0x43,0xc3]
+
+# CHECK: wlstp.16     lr, r0, #1668  @ encoding: [0x10,0xf0,0x43,0xc3]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x10,0xf0,0x43,0xc3]
+
+# CHECK: wlstp.32     lr, r4, #2706  @ encoding: [0x24,0xf0,0x49,0xcd]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x24,0xf0,0x49,0xcd]
+
+# CHECK: wlstp.64     lr, lr, #3026  @ encoding: [0x3e,0xf0,0xe9,0xcd]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x3e,0xf0,0xe9,0xcd]
+
+# CHECK: wlstp.8     lr, r5, #3436  @ encoding: [0x05,0xf0,0xb7,0xc6]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x05,0xf0,0xb7,0xc6]
+
+# CHECK: wlstp.16     lr, r1, #1060  @ encoding: [0x11,0xf0,0x13,0xc2]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x11,0xf0,0x13,0xc2]
+
+# CHECK: wlstp.32     lr, r7, #4036  @ encoding: [0x27,0xf0,0xe3,0xc7]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x27,0xf0,0xe3,0xc7]
+
+# CHECK: wlstp.8     lr, r1, #538  @ encoding: [0x01,0xf0,0x0d,0xc9]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x01,0xf0,0x0d,0xc9]
+
+# CHECK: wlstp.8     lr, r10, #1404  @ encoding: [0x0a,0xf0,0xbf,0xc2]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0a,0xf0,0xbf,0xc2]
+
+# CHECK: wlstp.8     lr, r10, #1408  @ encoding: [0x0a,0xf0,0xc1,0xc2]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0a,0xf0,0xc1,0xc2]
+
+# CHECK: wlstp.8     lr, r10, #2358  @ encoding: [0x0a,0xf0,0x9b,0xcc]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0a,0xf0,0x9b,0xcc]
+
+# CHECK: wlstp.8     lr, r10, #4086  @ encoding: [0x0a,0xf0,0xfb,0xcf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0a,0xf0,0xfb,0xcf]
+
+# CHECK: wlstp.8     lr, r11, #1442  @ encoding: [0x0b,0xf0,0xd1,0xca]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0b,0xf0,0xd1,0xca]
+
+# CHECK: dlstp.8     lr, r5  @ encoding: [0x05,0xf0,0x01,0xe0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x05,0xf0,0x01,0xe0]
+
+# CHECK: dlstp.16     lr, r5  @ encoding: [0x15,0xf0,0x01,0xe0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x15,0xf0,0x01,0xe0]
+
+# CHECK: dlstp.32     lr, r7  @ encoding: [0x27,0xf0,0x01,0xe0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x27,0xf0,0x01,0xe0]
+
+# CHECK: dlstp.64     lr, r2  @ encoding: [0x32,0xf0,0x01,0xe0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x32,0xf0,0x01,0xe0]
+
+# CHECK: letp lr, #-2 @ encoding: [0x1f,0xf0,0x01,0xc8]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x1f,0xf0,0x01,0xc8]
+
+# CHECK: letp lr, #-8 @ encoding: [0x1f,0xf0,0x05,0xc0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x1f,0xf0,0x05,0xc0]
+
+# CHECK: letp lr, #-4094 @ encoding: [0x1f,0xf0,0xff,0xcf]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x1f,0xf0,0xff,0xcf]
+
+# CHECK: lctp @ encoding: [0x0f,0xf0,0x01,0xe0]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x0f,0xf0,0x01,0xe0]
+
+# ERROR: [[@LINE+1]]:2: warning: potentially undefined instruction encoding
+[0x1f,0xf0,0x01,0xe0]
+
+# ERROR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x4f,0xf0,0x01,0xe0]
+
+# The following tests have to go last because of the NOMVE-NOT checks.
+
+# CHECK: it eq @ encoding: [0x08,0xbf]
+# CHECK-NOMVE: it eq @ encoding: [0x08,0xbf]
+[0x08,0xbf]
+# CHECK: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0]
+# CHECK-NOMVE-NOT: lctpeq @ encoding: [0x0f,0xf0,0x01,0xe0]
+[0x0f,0xf0,0x01,0xe0]