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[ARM] Add MVE 64-bit GPR <-> vector move instructions.

Authored by simon_tatham on May 30 2019, 8:23 AM.



These instructions let you load half a vector register at once from
two general-purpose registers, or vice versa.

The assembly syntax for these instructions mentions the vector
register name twice. For the move _into_ a vector register, the MC
operand list also has to mention the register name twice (once as the
output, and once as an input to represent where the unchanged half of
the output register comes from). So we can conveniently assign one of
the two asm operands to be the output $Qd, and the other $QdSrc, which
avoids confusing the auto-generated AsmMatcher too much. For the move
_from_ a vector register, there's no way to get round the fact that
both instances of that register name have to be inputs, so we need a
custom AsmMatchConverter to avoid generating two separate output MC
operands. (And even that wouldn't have worked if it hadn't been for

Diff Detail

Event Timeline

simon_tatham created this revision.May 30 2019, 8:23 AM

Remastered patch to apply cleanly against current trunk.

miyuki added a subscriber: miyuki.Jun 11 2019, 5:54 AM

Updated instruction id naming in line with intended MVE policy. Also added a comment explaining the complicated MC operand-juggling for these instructions with tricky asm syntax.

ostannard accepted this revision.Jun 21 2019, 3:35 AM
ostannard added a subscriber: ostannard.

LGTM with one nit.


The names "start" and "end" are misleading if we're checking for those two exact values, rather than a range of values.

This revision is now accepted and ready to land.Jun 21 2019, 3:35 AM
This revision was automatically updated to reflect the committed changes.