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[ARM] Add MVE vector instructions that take a scalar input.
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Authored by simon_tatham on May 30 2019, 8:22 AM.

Details

Summary

This adds the MVE_qDest_rSrc superclass and all its instances.
Instructions in this category take a scalar register (or register
pair) as one of the inputs, and combine it with each lane of the other
vector input.

Event Timeline

simon_tatham created this revision.May 30 2019, 8:22 AM

Remastered patch to apply cleanly against current trunk.

miyuki added a subscriber: miyuki.Jun 11 2019, 5:54 AM

Renamed instruction records in line with the intended MVE naming policy. Also generally tidied up while I was going along, by creating multiclasses and merging pairs of base classes where it saved space.

ostannard added inline comments.
llvm/lib/Target/ARM/ARMInstrMVE.td
2693

Rm should be 4 bits.

2720

Rm should be 4 bits.

llvm/test/MC/ARM/mve-qdest-rsrc.s
484

Maybe not one for this patch, but you shoyld be able to add a DiagnosticString to the RegisterClass to get a better diagnostic here.

Revised the VIDUP immediate operand handling so as to draw a distinction between the general concept 'power of 2 which is encoded as a left-shift count in the instruction', and the specific case used in VIDUP which takes a fixed range of inputs and has a custom DiagnosticString as you suggested that explains what it's used for.

Also, while I was adding custom DiagnosticStrings, I realised there could usefully be one on the even- and odd-numbered GPR classes. So I've added those too, which meant changing a couple of existing test files.

Finally, fixed those bits<5> Rx fields, and a couple of others I spotted in a more thorough search (including one in the previous patch, ahem).

This revision is now accepted and ready to land.Jun 21 2019, 6:07 AM
This revision was automatically updated to reflect the committed changes.