This is an archive of the discontinued LLVM Phabricator instance.

[ARM] Add MVE vector compare instructions.

Authored by simon_tatham on May 30 2019, 8:21 AM.



These take a pair of vector register to compare, and a comparison type
(written in the form of an Arm condition suffix); they output a vector
of booleans in the VPR register, where predication can conveniently
use them.

Event Timeline

simon_tatham created this revision.May 30 2019, 8:21 AM

Remastered patch to apply cleanly against current trunk.

miyuki added a subscriber: miyuki.Jun 11 2019, 5:54 AM

Updated to rename instruction classes in line with the general MVE policy. Also improved the custom decoder function for the VCMP family, by eliminating the huge secondary switch inside it on the opcode (instead we now pass in template parameters from Tablegen, which already knew what the opcode should be) and adding a comment explaining why that function even needs to be there.

ostannard added inline comments.

Rm only needs 4 bits.


We should also check the error message which is emitted in the NOFP case, and instructions with invalid conditions (the available conditions vary with type).

Added tests for invalid condition codes, and also added custom DiagnosticStrings that improve the error messages.

simon_tatham marked an inline comment as done.Jun 21 2019, 3:03 AM
This revision is now accepted and ready to land.Jun 21 2019, 3:42 AM
This revision was automatically updated to reflect the committed changes.