[ARM] Add MVE integer vector min/max instructions.

[simon_tatham]

Summary

These form a small family of their own, to go with the floating-point
VMINNM/VMAXNM instructions added in a previous commit.

They introduce the first of many special cases in the mnemonic
recognition code, because VMIN with the E suffix used by the VPT
predication system needs to avoid being interpreted as the nonexistent
instruction 'VMI' with an ordinary 'NE' condition suffix.

[ostannard]

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

5938

Why is this a startswith check, I don't see any valid mnemonics with extra letters on the end.

[simon_tatham]

Remastered patch to apply cleanly against current trunk.

[miyuki]

llvm/lib/Target/ARM/ARMInstrMVE.td

647

These definitions can be combined into a multiclass.

[simon_tatham]

• Removed the pointless startswith (which I'll have to do in a lot of the rest of the series too)
• Added multiclass as suggested

[ostannard]

llvm/test/MC/ARM/mve-minmax.s

3

Why have you removed this? There are still ERROR-NOFP check lines, which are now unused.

[simon_tatham]

Reinstated RUN: lines that vanished in a rebase error (sorry)

[simon_tatham]

Renamed the instructions' Tablegen ids for consistency, in line with a
review comment @ostannard made on the followup patch D62672.

[ostannard]

LGTM

llvm/lib/Target/ARM/ARMInstrMVE.td

 }
 
 def VMAXNMf32 : VMINMAXNM<"vmaxnm", "f32", 0b0, 0b0>;
 def VMAXNMf16 : VMINMAXNM<"vmaxnm", "f16", 0b1, 0b0>;
 
 def VMINNMf32 : VMINMAXNM<"vminnm", "f32", 0b0, 0b1>;
 def VMINNMf16 : VMINMAXNM<"vminnm", "f16", 0b1, 0b1>;
 
+class VMINMAX<string iname, string suffix, bit U, bits<2> size,
+              bit bit_4, list<dag> pattern=[]>
+  : MVE_comp<NoItinerary, iname, suffix, "", pattern> {
+
+  let Inst{28} = U;
+  let Inst{25-24} = 0b11;
+  let Inst{23} = 0b0;
+  let Inst{21-20} = size{1-0};
+  let Inst{11} = 0b0;
+  let Inst{8} = 0b0;
+  let Inst{6} = 0b1;
+  let Inst{4} = bit_4;
+}
+
+multiclass VMINMAX_all_sizes<string iname, bit bit_4> {
+  def s8  : VMINMAX<iname, "s8",  0b0, 0b00, bit_4>;
+  def s16 : VMINMAX<iname, "s16", 0b0, 0b01, bit_4>;
+  def s32 : VMINMAX<iname, "s32", 0b0, 0b10, bit_4>;
+  def u8  : VMINMAX<iname, "u8",  0b1, 0b00, bit_4>;
+  def u16 : VMINMAX<iname, "u16", 0b1, 0b01, bit_4>;
+  def u32 : VMINMAX<iname, "u32", 0b1, 0b10, bit_4>;
+}
+
+// Prefix these names with MVE to avoid conflict with NEON equivalents.
+defm MVE_VMAX : VMINMAX_all_sizes<"vmax", 0b0>;
+defm MVE_VMIN : VMINMAX_all_sizes<"vmin", 0b1>;
+
 // end of mve_comp instructions
 
 class t2VPT<string suffix, bits<2> size, dag iops, string asm, list<dag> pattern=[]>
   : MVE_MI<(outs ), iops, NoItinerary, !strconcat("vpt", "${Mk}", ".", suffix), asm, "", pattern> {
   bits<3> fc;
   bits<4> Mk;
   bits<3> Qn;
 

llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

if ((Mnemonic == "movs" && isThumb()) ||
       Mnemonic == "csetm")
     return Mnemonic;
 
   // First, split out any predication code. Ignore mnemonics we know aren't
   // predicated but do have a carry-set and so weren't caught above.
   if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
       Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
       Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
-      Mnemonic != "sbcs" && Mnemonic != "rscs") {
+      Mnemonic != "sbcs" && Mnemonic != "rscs" &&
+      !(hasMVE() && Mnemonic == "vmine")) {
     unsigned CC = ARMCondCodeFromString(Mnemonic.substr(Mnemonic.size()-2));
     if (CC != ~0U) {
       Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
       PredicationCode = CC;
     }
   }
 
   // Next, determine if we have a carry setting bit. We explicitly ignore all
   // the instructions we know end in 's'.

llvm/test/MC/ARM/mve-minmax.s

 # RUN: not llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding  < %s 2> %t \
 # RUN:   | FileCheck --check-prefix=CHECK-NOFP %s
 # RUN: FileCheck --check-prefix=ERROR-NOFP %s < %t
 # RUN: llvm-mc -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding  < %s \
 # RUN:   | FileCheck --check-prefix=CHECK %s
 
 # CHECK: vmaxnm.f32 q0, q1, q4  @ encoding: [0x02,0xff,0x58,0x0f]
 # CHECK-NOFP-NOT: vmaxnm.f32 q0, q1, q4  @ encoding: [0x02,0xff,0x58,0x0f]
 # ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
 vmaxnm.f32 q0, q1, q4
 
 # CHECK: vminnm.f16 q3, q0, q1  @ encoding: [0x30,0xff,0x52,0x6f]
 # CHECK-NOFP-NOT: vminnm.f16 q3, q0, q1  @ encoding: [0x30,0xff,0x52,0x6f]
 # ERROR-NOFP: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve.fp
 vminnm.f16 q3, q0, q1
+
+# CHECK: vmin.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x5e,0x66]
+# CHECK-NOFP: vmin.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x5e,0x66]
+vmin.s8 q3, q0, q7
+
+# CHECK: vmin.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x06]
+# CHECK-NOFP: vmin.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x06]
+vmin.s16 q0, q1, q2
+
+# CHECK: vmin.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x54,0x06]
+# CHECK-NOFP: vmin.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x54,0x06]
+vmin.s32 q0, q1, q2
+
+# CHECK: vmin.u8 q0, q1, q2 @ encoding: [0x02,0xff,0x54,0x06]
+# CHECK-NOFP: vmin.u8 q0, q1, q2 @ encoding: [0x02,0xff,0x54,0x06]
+vmin.u8 q0, q1, q2
+
+# CHECK: vmin.u16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x06]
+# CHECK-NOFP: vmin.u16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x06]
+vmin.u16 q0, q1, q2
+
+# CHECK: vmin.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x54,0x06]
+# CHECK-NOFP: vmin.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x54,0x06]
+vmin.u32 q0, q1, q2
+
+# CHECK: vmax.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x4e,0x66]
+# CHECK-NOFP: vmax.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x4e,0x66]
+vmax.s8 q3, q0, q7
+
+# CHECK: vmax.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x44,0x06]
+# CHECK-NOFP: vmax.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x44,0x06]
+vmax.s16 q0, q1, q2
+
+# CHECK: vmax.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x44,0x06]
+# CHECK-NOFP: vmax.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x44,0x06]
+vmax.s32 q0, q1, q2
+
+# CHECK: vmax.u8 q0, q1, q2 @ encoding: [0x02,0xff,0x44,0x06]
+# CHECK-NOFP: vmax.u8 q0, q1, q2 @ encoding: [0x02,0xff,0x44,0x06]
+vmax.u8 q0, q1, q2
+
+# CHECK: vmax.u16 q0, q1, q2 @ encoding: [0x12,0xff,0x44,0x06]
+# CHECK-NOFP: vmax.u16 q0, q1, q2 @ encoding: [0x12,0xff,0x44,0x06]
+vmax.u16 q0, q1, q2
+
+# CHECK: vmax.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x44,0x06]
+# CHECK-NOFP: vmax.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x44,0x06]
+vmax.u32 q0, q1, q2
+
+vpste
+vmint.s8 q0, q1, q2
+vmine.s16 q0, q1, q2
+# CHECK: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK-NOFP: vpste @ encoding: [0x71,0xfe,0x4d,0x8f]
+# CHECK: vmint.s8 q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x06]
+# CHECK-NOFP: vmint.s8 q0, q1, q2 @ encoding: [0x02,0xef,0x54,0x06]
+# CHECK: vmine.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x06]
+# CHECK-NOFP: vmine.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x06]

llvm/test/MC/Disassembler/ARM/mve-minmax.txt

 # RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve.fp,+fp64 -show-encoding %s | FileCheck %s
 # RUN: not llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -show-encoding %s &> %t
 # RUN: FileCheck --check-prefix=CHECK-NOMVE < %t %s
 
 # CHECK: vmaxnm.f32 q0, q1, q4  @ encoding: [0x02,0xff,0x58,0x0f]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x02,0xff,0x58,0x0f]
 
 # CHECK: vminnm.f16 q3, q0, q1  @ encoding: [0x30,0xff,0x52,0x6f]
 # CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
 [0x30,0xff,0x52,0x6f]
+
+# CHECK: vmin.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x5e,0x66]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xef,0x5e,0x66]
+
+# CHECK: vmin.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xef,0x54,0x06]
+
+# CHECK: vmin.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x54,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xef,0x54,0x06]
+
+# CHECK: vmin.u8 q0, q1, q2 @ encoding: [0x02,0xff,0x54,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xff,0x54,0x06]
+
+# CHECK: vmin.u16 q0, q1, q2 @ encoding: [0x12,0xff,0x54,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xff,0x54,0x06]
+
+# CHECK: vmin.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x54,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xff,0x54,0x06]
+
+# CHECK: vmax.s8 q3, q0, q7 @ encoding: [0x00,0xef,0x4e,0x66]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xef,0x4e,0x66]
+
+# CHECK: vmax.s16 q0, q1, q2 @ encoding: [0x12,0xef,0x44,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xef,0x44,0x06]
+
+# CHECK: vmax.s32 q0, q1, q2 @ encoding: [0x22,0xef,0x44,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xef,0x44,0x06]
+
+# CHECK: vmax.u8 q0, q1, q2 @ encoding: [0x02,0xff,0x44,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x02,0xff,0x44,0x06]
+
+# CHECK: vmax.u16 q0, q1, q2 @ encoding: [0x12,0xff,0x44,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x12,0xff,0x44,0x06]
+
+# CHECK: vmax.u32 q0, q1, q2 @ encoding: [0x22,0xff,0x44,0x06]
+# CHECK-NOMVE: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x22,0xff,0x44,0x06]