[DAGCombine] Allow GatherAllAliases to pass through inline asm calls and glued nodes.

[niravd]

Summary

Teach GatherAllAliases to reason about inline assembly nodes and
associated glued CopyToReg/CopyFromReg nodes.

This fixes PR9517.

[niravd]

Actual Patch.

[niravd]

This is a refactored and rebased version of D49691 so that it looks reasonable on Phabricator. I've factored out a initial NFC patch (the first snapshot in history) to highlight the actual functional change.

[niravd]

Ping.

Just a reminder to ease review: The first diff in the history is an extracted NFC refactoring and difference between Diffs 1 and 2 highlight the actual change.

[efriedma]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

19527

"If this had a glued output, return C"?

I don't follow why it matters if the output is glued, given there isn't a glue input. If I'm understanding correctly, if the copy isn't glued, in it doesn't modify memory. If the copy is glued, the only way to reach this case should be through a recursive call of ImproveChain. Or are you just trying to be conservative here?

[niravd]

Realized explanatory comment and associate fixup had been lost in patch stack. Folding it back in.

[efriedma]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

19546

In terms of the actual checks here, is this sufficient to catch any inline asm that accesses memory? Do you need to check for Extra_HasSideEffects? Do you need to check for "indirect" operands separately? (I think it's possible to write an indirect register operand in IR, although I'm not sure clang ever generates them...)

[niravd]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

19546

SelectionDAGBuilder updates the inlineasm's ExtraInfo based on the asm parameter constraints so checking extra info should be should be sufficient.

Also, a check for HasExtraSideEffects is probably needed. I've updated the patch as such.

[niravd]

Check HasSideEffects in analysis for inlineasm.

[efriedma]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

19546

With the change to check HasExtraSideEffects, can you remove the Mips test changes?

[niravd]

Revert mips test changes

[efriedma]

LGTM

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (UseAA && AA &&
     if (AAResult == NoAlias)
       return false;
   }
 
   // Otherwise we have to assume they alias.
   return true;
 }
 
+static bool hasGluedInputChain(SDNode *N) {
+  auto LastOpNo = N->getNumOperands() - 1;
+  bool hasChain = N->getOperand(0).getValueType() == MVT::Other;
+  bool hasInputGlue = N->getOperand(LastOpNo).getValueType() == MVT::Glue;
+  return hasChain && hasInputGlue &&
+         (N->getOperand(0).getNode() == N->getOperand(LastOpNo).getNode());
+}
+
+static bool hasGluedOutput(SDNode *N) {
+  if (N->getNumValues() <= 1)
+    return false;
+  auto LastValNo = N->getNumValues() - 1;
+  bool hasChainOut = N->getValueType(LastValNo - 1) == MVT::Other;
+  bool hasGlueOut = N->getValueType(LastValNo) == MVT::Glue;
+  return hasChainOut && hasGlueOut;
+}
+
 /// Walk up chain skipping non-aliasing memory nodes,
 /// looking for aliasing nodes and adding them to the Aliases vector.
 void DAGCombiner::GatherAllAliases(LSBaseSDNode *N, SDValue OriginalChain,
                                    SmallVectorImpl<SDValue> &Aliases) {
   SmallVector<SDValue, 8> Chains;     // List of chains to visit.
   SmallPtrSet<SDNode *, 16> Visited;  // Visited node set.
 
   // Get alias information for node.
   bool IsLoad = isa<LoadSDNode>(N) && !N->isVolatile();
   const BaseIndexOffset LSBasePtr = BaseIndexOffset::match(N, DAG);
   const unsigned LSNumBytes = N->getMemoryVT().getStoreSize();
 
   // Starting off.
   Chains.push_back(OriginalChain);
   unsigned Depth = 0;
 
+  // Attempt to improve chain by a single step
+  std::function<bool(SDValue &)> ImproveChain = [&](SDValue &C) -> bool {
+    switch (C.getOpcode()) {
+    case ISD::EntryToken:
+      // No need to mark EntryToken.
+      C = SDValue();
+      return true;
+    case ISD::LOAD:
+    case ISD::STORE: {
+      // Get alias information for C.
+      auto LSChain = cast<LSBaseSDNode>(C.getNode());
+      bool IsOpLoad = isa<LoadSDNode>(C.getNode()) && !LSChain->isVolatile();
+      if ((IsLoad && IsOpLoad) || !isAlias(N, LSChain)) {
+        // Look further up the chain.
+        C = C.getOperand(0);
+        return true;
+      }
+      // Alias, so stop here.
+      return false;
+    }
+
+    case ISD::CopyFromReg:
+      // If this is glued, recursively check chain to see if we can skip the
+      // full glued chain..
+      if (hasGluedInputChain(C.getNode())) {
+        C = C.getOperand(0);
+        return ImproveChain(C);
+      }
+      // Unglued node can always be skipped.
+      C = C.getOperand(0);
+      return true;
+
+    case ISD::CopyToReg: {
+      if (hasGluedInputChain(C.getNode())) {
+        C = C.getOperand(0);
+        return ImproveChain(C);
+      }
+
+      // CopyToReg is used to introduce values into the DAG. Forwarding past
+      // these nodes appears to violate some assumtion in the DAG logic. As
+      // such, we avoid bypassing unglued CopyToReg nodes.
+
+      // Succeed if we're at the top of a glued region.
+      if (hasGluedOutput(C.getNode())) {
+        C = C.getOperand(0);
+        return true;
+      }
+      return false;
+    }
+
+    case ISD::INLINEASM: {
+      auto *ExtraInfo =
+          cast<ConstantSDNode>(C->getOperand(InlineAsm::Op_ExtraInfo));
+      unsigned EIInt = ExtraInfo->getZExtValue();
+      bool IsSafe = !(EIInt & InlineAsm::Extra_MayStore);
+      if (!IsLoad)
+        IsSafe = IsSafe && !(EIInt & (InlineAsm::Extra_MayLoad |
+                                      InlineAsm::Extra_HasSideEffects));
+      if (IsSafe && hasGluedInputChain(C.getNode())) {
+        C = C.getOperand(0);
+        return ImproveChain(C);
+      }
+      return false;
+    }
+
+    case ISD::LIFETIME_START:
+    case ISD::LIFETIME_END: {
+      // We can forward past any lifetime start/end that can be proven not to
+      // alias the memory access.
+      const auto *Lifetime = cast<LifetimeSDNode>(C);
+      if (!Lifetime->hasOffset())
+        return false; // Be conservative if we don't know the extents of the object.
+
+      const BaseIndexOffset LifetimePtr(Lifetime->getOperand(1), SDValue(),
+                                        Lifetime->getOffset(), false);
+      bool IsAlias;
+      if (BaseIndexOffset::computeAliasing(LifetimePtr, Lifetime->getSize(),
+                                           LSBasePtr, LSNumBytes, DAG,
+                                           IsAlias) && !IsAlias) {
+        C = C.getOperand(0);
+        return true;
+      }
+      return false;
+    }
+
+    default:
+      return false;
+    }
+  };
+
   // Look at each chain and determine if it is an alias.  If so, add it to the
   // aliases list.  If not, then continue up the chain looking for the next
   // candidate.
   while (!Chains.empty()) {
     SDValue Chain = Chains.pop_back_val();
 
+    // Don't bother if we've seen Chain before.
+    if (!Visited.insert(Chain.getNode()).second)
+      continue;
+
     // For TokenFactor nodes, look at each operand and only continue up the
     // chain until we reach the depth limit.
     //
     // FIXME: The depth check could be made to return the last non-aliasing
     // chain we found before we hit a tokenfactor rather than the original
     // chain.
     if (Depth > TLI.getGatherAllAliasesMaxDepth()) {
       Aliases.clear();
       Aliases.push_back(OriginalChain);
       return;
     }
 
-    // Don't bother if we've been before.
-    if (!Visited.insert(Chain.getNode()).second)
-      continue;
-
-    switch (Chain.getOpcode()) {
-    case ISD::EntryToken:
-      // Entry token is ideal chain operand, but handled in FindBetterChain.
-      break;
-
-    case ISD::LOAD:
-    case ISD::STORE: {
-      // Get alias information for Chain.
-      bool IsOpLoad = isa<LoadSDNode>(Chain.getNode()) &&
-          !cast<LSBaseSDNode>(Chain.getNode())->isVolatile();
-
-      // If chain is alias then stop here.
-      if (!(IsLoad && IsOpLoad) &&
-          isAlias(N, cast<LSBaseSDNode>(Chain.getNode()))) {
-        Aliases.push_back(Chain);
-      } else {
-        // Look further up the chain.
-        Chains.push_back(Chain.getOperand(0));
-        ++Depth;
-      }
-      break;
-    }
-
-    case ISD::TokenFactor:
+    if (Chain.getOpcode() == ISD::TokenFactor) {
       // We have to check each of the operands of the token factor for "small"
       // token factors, so we queue them up.  Adding the operands to the queue
       // (stack) in reverse order maintains the original order and increases the
       // likelihood that getNode will find a matching token factor (CSE.)
       if (Chain.getNumOperands() > 16) {
         Aliases.push_back(Chain);
-        break;
+        continue;
       }
       for (unsigned n = Chain.getNumOperands(); n;)
         Chains.push_back(Chain.getOperand(--n));
       ++Depth;
-      break;
-
-    case ISD::CopyFromReg:
-      // Forward past CopyFromReg.
-      Chains.push_back(Chain.getOperand(0));
-      ++Depth;
-      break;
-
-    case ISD::LIFETIME_START:
-    case ISD::LIFETIME_END: {
-      // We can forward past any lifetime start/end that can be proven not to
-      // alias the memory access.
-      const auto *Lifetime = cast<LifetimeSDNode>(Chain);
-      if (!Lifetime->hasOffset()) {
-        Aliases.push_back(Chain);
-        break; // Be conservative if we don't know the extents of the object.
-      }
-
-      const BaseIndexOffset LifetimePtr(Lifetime->getOperand(1), SDValue(),
-                                        Lifetime->getOffset(), false);
-      bool IsAlias;
-      if (BaseIndexOffset::computeAliasing(LifetimePtr, Lifetime->getSize(),
-                                           LSBasePtr, LSNumBytes, DAG,
-                                           IsAlias) &&
-          !IsAlias) {
-        Chains.push_back(Chain.getOperand(0));
-        ++Depth;
-      } else {
-        Aliases.push_back(Chain);
-      }
-      break;
+      continue;
+    // Everything else
+    if (ImproveChain(Chain)) {
+      // Updated Chain Found, Consider new chain if one exists.
+      if (Chain.getNode())
+        Chains.push_back(Chain);
+      continue;
     }
-
-    default:
-      // For all other instructions we will just have to take what we can get.
-      Aliases.push_back(Chain);
-      break;
-    }
+    // No Improved Chain Possible, treat as Alias.
   }
 }
 
 /// Walk up chain skipping non-aliasing memory nodes, looking for a better chain
 /// (aliasing node.)
 SDValue DAGCombiner::FindBetterChain(LSBaseSDNode *N, SDValue OldChain) {
   if (OptLevel == CodeGenOpt::None)
     return OldChain;

llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll

 
 ; Copy the arg to the global
 ; ALL-DAG:       sh [[ARG2]], 4([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i16
   %e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1
   store volatile i16 %arg1, i16* %e1, align 2
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i16
   %e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2
   store volatile i16 %arg2, i16* %e2, align 2
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; Copy the arg to the global
 ; ALL-DAG:       sw [[ARG2]], 8([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i32
   %e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1
   store volatile i32 %arg1, i32* %e1, align 4
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i32
   %e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2
   store volatile i32 %arg2, i32* %e2, align 4
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; NEW-DAG:       ld [[ARG2:\$[0-9]+]], 0([[VA2]])
 ; NEW-DAG:       sd [[ARG2]], 16([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i64
   %e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1
   store volatile i64 %arg1, i64* %e1, align 8
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i64
   %e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2
   store volatile i64 %arg2, i64* %e2, align 8
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; Copy the arg to the global
 ; ALL-DAG:       sh [[ARG2]], 4([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i16
   %e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1
   store volatile i16 %arg1, i16* %e1, align 2
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i16
   %e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2
   store volatile i16 %arg2, i16* %e2, align 2
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; Copy the arg to the global
 ; ALL-DAG:       sw [[ARG2]], 8([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i32
   %e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1
   store volatile i32 %arg1, i32* %e1, align 4
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i32
   %e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2
   store volatile i32 %arg2, i32* %e2, align 4
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; NEW-DAG:       ld [[ARG2:\$[0-9]+]], 0([[VA2]])
 ; NEW-DAG:       sd [[ARG2]], 16([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i64
   %e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1
   store volatile i64 %arg1, i64* %e1, align 8
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i64
   %e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2
   store volatile i64 %arg2, i64* %e2, align 8
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; Copy the arg to the global
 ; ALL-DAG:       sh [[ARG2]], 4([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i16
   %e1 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 1
   store volatile i16 %arg1, i16* %e1, align 2
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i16
   %e2 = getelementptr [3 x i16], [3 x i16]* @hwords, i32 0, i32 2
   store volatile i16 %arg2, i16* %e2, align 2
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; Copy the arg to the global
 ; ALL-DAG:       sw [[ARG2]], 8([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i32
   %e1 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 1
   store volatile i32 %arg1, i32* %e1, align 4
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i32
   %e2 = getelementptr [3 x i32], [3 x i32]* @words, i32 0, i32 2
   store volatile i32 %arg2, i32* %e2, align 4
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }

 
 ; NEW-DAG:       ld [[ARG2:\$[0-9]+]], 0([[VA2]])
 ; NEW-DAG:       sd [[ARG2]], 16([[GV]])
 
   %ap = alloca i8*, align 8
   %ap2 = bitcast i8** %ap to i8*
   call void @llvm.va_start(i8* %ap2)
 
-  call void asm sideeffect "teqi $$zero, 1", ""()
+  call void asm sideeffect "teqi $$zero, 1", "~{memory}"()
   %arg1 = va_arg i8** %ap, i64
   %e1 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 1
   store volatile i64 %arg1, i64* %e1, align 8
 
-  call void asm sideeffect "teqi $$zero, 2", ""()
+  call void asm sideeffect "teqi $$zero, 2", "~{memory}"()
   %arg2 = va_arg i8** %ap, i64
   %e2 = getelementptr [3 x i64], [3 x i64]* @dwords, i32 0, i32 2
   store volatile i64 %arg2, i64* %e2, align 8
 
   call void @llvm.va_end(i8* %ap2)
 
   ret void
 }
 
 declare void @llvm.va_start(i8*)
 declare void @llvm.va_end(i8*)

llvm/test/CodeGen/Thumb/frame-access.ll

 }
 ; CHECK-LABEL: test_local
 ; Arguments to `h` relative to SP
 ; CHECK:       add r0, sp, #20
 ; CHECK-NEXT:  add r1, sp, #16
 ; CHECK-NEXT:  add r2, sp, #12
 ; CHECK-NEXT:  bl  h
 ; Load `x`, `y`, and `z` via SP
-; CHECK:       ldr r1, [sp, #20]
-; CHECK-NEXT:  ldr r2, [sp, #16]
-; CHECK-NEXT:  ldr r3, [sp, #12]
+; CHECK-DAG:  ldr r1, [sp, #20]
+; CHECK-DAG:  ldr r2, [sp, #16]
+; CHECK-DAG:  ldr r3, [sp, #12]
 ; CHECK:       bl  g
 
 ; Re-aligned stack, access via SP.
 ; int test_local_realign(int n) {
 ;   __attribute__((aligned(16))) int v[4];
 ;   int x, y, z;
 ;   h(&x, &y, &z);
 ;   return g(v, x, y, z, 0, 0);

 ; CHECK-NEXT:  lsls r4, r4, #4
 ; CHECK-NEXT:  mov  sp, r4
 ; Arguments to `h` computed relative to SP
 ; CHECK:       add r0, sp, #28
 ; CHECK-NEXT:  add r1, sp, #24
 ; CHECK-NEXT:  add r2, sp, #20
 ; CHECK-NEXT:  bl  h
 ; Load `x`, `y`, and `z` via SP for passing to `g`
-; CHECK:       ldr r1, [sp, #28]
-; CHECK-NEXT:  ldr r2, [sp, #24]
-; CHECK-NEXT:  ldr r3, [sp, #20]
+; CHECK-DAG:       ldr r1, [sp, #28]
+; CHECK-DAG:  ldr r2, [sp, #24]
+; CHECK-DAG:  ldr r3, [sp, #20]
 ; CHECK:       bl  g
 
 ; VLAs, access via BP.
 ; int test_local_vla(int n) {
 ;   int v[n];
 ;   int x, y, z;
 ;   h(&x, &y, &z);
 ;   return g(v, x, y, z, 0, 0);

llvm/test/CodeGen/X86/inline-asm-fpstack.ll

 }
 
 ; PR4485
 define void @testPR4485(x86_fp80* %a) {
 ; CHECK-LABEL: testPR4485:
 ; CHECK:       ## %bb.0: ## %entry
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
 ; CHECK-NEXT:    fldt (%eax)
-; CHECK-NEXT:    flds LCPI10_0
-; CHECK-NEXT:    fmul %st, %st(1)
-; CHECK-NEXT:    flds LCPI10_1
-; CHECK-NEXT:    fmul %st, %st(2)
-; CHECK-NEXT:    fxch %st(2)
+; CHECK-NEXT:    fmuls LCPI10_0
+; CHECK-NEXT:    fmuls LCPI10_1
+; CHECK-NEXT:    fld %st(0)
 ; CHECK-NEXT:    ## InlineAsm Start
 ; CHECK-NEXT:    fistpl %st
 ; CHECK-NEXT:    ## InlineAsm End
-; CHECK-NEXT:    fldt (%eax)
-; CHECK-NEXT:    fmulp %st, %st(1)
-; CHECK-NEXT:    fmulp %st, %st(1)
 ; CHECK-NEXT:    ## InlineAsm Start
 ; CHECK-NEXT:    fistpl %st
 ; CHECK-NEXT:    ## InlineAsm End
 ; CHECK-NEXT:    retl
 entry:
   %0 = load x86_fp80, x86_fp80* %a, align 16
   %1 = fmul x86_fp80 %0, 0xK4006B400000000000000
   %2 = fmul x86_fp80 %1, 0xK4012F424000000000000

llvm/test/CodeGen/X86/pr9517.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -o - %s -mtriple=x86_64--unknown-linux-gnu | FileCheck %s
 
 @base = external dso_local local_unnamed_addr global i16, align 2
 
 ; We should be able to merge the two loads here
 define i16 @unify_through_trivial_asm() {
 ; CHECK-LABEL: unify_through_trivial_asm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movzwl {{.*}}(%rip), %eax
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %eax
 ; CHECK-NEXT:    incl %eax
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq
   %x = load i16, i16* @base, align 2
   tail call void asm sideeffect "nop", "r,~{dirflag},~{fpsr},~{flags}"(i16 %x)
   %x2 = load i16, i16* @base, align 2
   %v = add i16 %x2, 1
   ret i16 %v
 }
 
-; The asm call prevents the merging the loads here. 
+; The asm call prevents the merging the loads here.
 define i16 @unify_through_trival_asm_w_memory_clobber() {
 ; CHECK-LABEL: unify_through_trival_asm_w_memory_clobber:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movzwl {{.*}}(%rip), %eax
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    movzwl {{.*}}(%rip), %eax
 ; CHECK-NEXT:    incl %eax
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq
   %x = load i16, i16* @base, align 2
   tail call void asm sideeffect "nop", "+r,~{dirflag},~{fpsr},~{flags},~{base},~{memory}"(i16 %x)
   %x2 = load i16, i16* @base, align 2
   %v = add i16 %x2, 1
   ret i16 %v
 }
 
 define dso_local void @fulltest() local_unnamed_addr {
 ; CHECK-LABEL: fulltest:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
 ; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $1, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $2, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $3, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $4, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $5, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $6, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $7, %al
-; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
-; CHECK-NEXT:    movzwl {{.*}}(%rip), %edx
-; CHECK-NEXT:    addl $16, %edx
 ; CHECK-NEXT:    movb $8, %al
 ; CHECK-NEXT:    # kill: def $dx killed $dx killed $edx
 ; CHECK-NEXT:    #APP
 ; CHECK-NEXT:    outb %al, %dx
 ; CHECK-NEXT:    #NO_APP
 ; CHECK-NEXT:    retq
 entry:
   %0 = load i16, i16* @base, align 2