[RISCV] Handle EltType > XLEN case in VMV_V_X_VL to VMV_S_X_VL fold

[reames]

Summary

I'd guarded this case in D158874 to avoid regressions, and decided to go investigate what was going on. The solution turns out to be a generic splat matching extension to handle INSERT_SUBVECTOR. In theory, we could see these from other sources as well, but for some reason we only seem to see the i64 extract on rv32 case in practice. Not sure why that is to be honest.

[luke]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

2964

Are we getting multiple nested insert_subvectors? If their vector operands are undef shouldn't they be getting combined away? I found this combine in DAGCombiner.cpp:

// Eliminate an intermediate insert into an undef vector:
// insert_subvector undef, (insert_subvector undef, X, 0), N2 -->
// insert_subvector undef, X, N2
if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR &&
    N1.getOperand(0).isUndef() && isNullConstant(N1.getOperand(2)))
  return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0,
                     N1.getOperand(1), N2);

[reames]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

2964

Not that I saw, I can remove the loop if desired. This is just replacing the "while" with an "if".

[reames]

ping

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

bool RISCVDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) {
   } else {
     VL = N;
   }
 
   return true;
 }
 
 static SDValue findVSplat(SDValue N) {
+  if (N.getOpcode() == ISD::INSERT_SUBVECTOR) {
+    if (!N.getOperand(0).isUndef())
+      return SDValue();
+    N = N.getOperand(1);
+  }
   SDValue Splat = N;
   if ((Splat.getOpcode() != RISCVISD::VMV_V_X_VL &&
        Splat.getOpcode() != RISCVISD::VMV_S_X_VL) ||
       !Splat.getOperand(0).isUndef())
     return SDValue();
   assert(Splat.getNumOperands() == 3 && "Unexpected number of operands");
   return Splat;
 }

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

case RISCVISD::VMV_V_X_VL: {
     // scalar input.
     unsigned ScalarSize = Scalar.getValueSizeInBits();
     unsigned EltWidth = VT.getScalarSizeInBits();
     if (ScalarSize > EltWidth && Passthru.isUndef())
       if (SimplifyDemandedLowBitsHelper(1, EltWidth))
         return SDValue(N, 0);
 
     // If VL is 1 and the scalar value won't benefit from immediate, we can
-    // use vmv.s.x.  Do this only if legal to avoid breaking i64 sext(i32)
-    // patterns on rv32..
+    // use vmv.s.x.
     ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Scalar);
-    if (isOneConstant(VL) && EltWidth <= Subtarget.getXLen() &&
+    if (isOneConstant(VL) &&
         (!Const || Const->isZero() ||
          !Const->getAPIntValue().sextOrTrunc(EltWidth).isSignedIntN(5)))
       return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, VT, Passthru, Scalar, VL);
 
     break;
   }
   case RISCVISD::VFMV_S_F_VL: {
     SDValue Src = N->getOperand(1);

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll

 ; CHECK-ZVBB-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; CHECK-ZVBB-NEXT:    vrol.vv v8, v8, v9
 ; CHECK-ZVBB-NEXT:    ret
   %x = call <1 x i64> @llvm.fshl.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b)
   ret <1 x i64> %x
 }
 
 define <1 x i64> @vrol_vx_v1i64(<1 x i64> %a, i64 %b) {
-; CHECK-RV32-LABEL: vrol_vx_v1i64:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT:    vmv.v.x v9, a0
-; CHECK-RV32-NEXT:    li a0, 63
-; CHECK-RV32-NEXT:    vand.vx v10, v9, a0
-; CHECK-RV32-NEXT:    vsll.vv v10, v8, v10
-; CHECK-RV32-NEXT:    vrsub.vi v9, v9, 0
-; CHECK-RV32-NEXT:    vand.vx v9, v9, a0
-; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v9
-; CHECK-RV32-NEXT:    vor.vv v8, v10, v8
-; CHECK-RV32-NEXT:    ret
-;
-; CHECK-RV64-LABEL: vrol_vx_v1i64:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV64-NEXT:    vmv.s.x v9, a0
-; CHECK-RV64-NEXT:    li a0, 63
-; CHECK-RV64-NEXT:    vand.vx v10, v9, a0
-; CHECK-RV64-NEXT:    vsll.vv v10, v8, v10
-; CHECK-RV64-NEXT:    vrsub.vi v9, v9, 0
-; CHECK-RV64-NEXT:    vand.vx v9, v9, a0
-; CHECK-RV64-NEXT:    vsrl.vv v8, v8, v9
-; CHECK-RV64-NEXT:    vor.vv v8, v10, v8
-; CHECK-RV64-NEXT:    ret
+; CHECK-LABEL: vrol_vx_v1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT:    vmv.s.x v9, a0
+; CHECK-NEXT:    li a0, 63
+; CHECK-NEXT:    vand.vx v10, v9, a0
+; CHECK-NEXT:    vsll.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vx v9, v9, a0
+; CHECK-NEXT:    vsrl.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
 ;
 ; CHECK-ZVBB-LABEL: vrol_vx_v1i64:
 ; CHECK-ZVBB:       # %bb.0:
 ; CHECK-ZVBB-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
 ; CHECK-ZVBB-NEXT:    ret
   %b.head = insertelement <1 x i64> poison, i64 %b, i32 0
   %b.splat = shufflevector <1 x i64> %b.head, <1 x i64> poison, <1 x i32> zeroinitializer

 ; CHECK-ZVBB-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
 ; CHECK-ZVBB-NEXT:    vrol.vx v8, v8, a0
 ; CHECK-ZVBB-NEXT:    ret
   %b.head = insertelement <8 x i64> poison, i64 %b, i32 0
   %b.splat = shufflevector <8 x i64> %b.head, <8 x i64> poison, <8 x i32> zeroinitializer
   %x = call <8 x i64> @llvm.fshl.v8i64(<8 x i64> %a, <8 x i64> %a, <8 x i64> %b.splat)
   ret <8 x i64> %x
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-RV32: {{.*}}
+; CHECK-RV64: {{.*}}

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll

 ; CHECK-ZVBB-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; CHECK-ZVBB-NEXT:    vror.vv v8, v8, v9
 ; CHECK-ZVBB-NEXT:    ret
   %x = call <1 x i64> @llvm.fshr.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b)
   ret <1 x i64> %x
 }
 
 define <1 x i64> @vror_vx_v1i64(<1 x i64> %a, i64 %b) {
-; CHECK-RV32-LABEL: vror_vx_v1i64:
-; CHECK-RV32:       # %bb.0:
-; CHECK-RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV32-NEXT:    vmv.v.x v9, a0
-; CHECK-RV32-NEXT:    li a0, 63
-; CHECK-RV32-NEXT:    vand.vx v10, v9, a0
-; CHECK-RV32-NEXT:    vsrl.vv v10, v8, v10
-; CHECK-RV32-NEXT:    vrsub.vi v9, v9, 0
-; CHECK-RV32-NEXT:    vand.vx v9, v9, a0
-; CHECK-RV32-NEXT:    vsll.vv v8, v8, v9
-; CHECK-RV32-NEXT:    vor.vv v8, v10, v8
-; CHECK-RV32-NEXT:    ret
-;
-; CHECK-RV64-LABEL: vror_vx_v1i64:
-; CHECK-RV64:       # %bb.0:
-; CHECK-RV64-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
-; CHECK-RV64-NEXT:    vmv.s.x v9, a0
-; CHECK-RV64-NEXT:    li a0, 63
-; CHECK-RV64-NEXT:    vand.vx v10, v9, a0
-; CHECK-RV64-NEXT:    vsrl.vv v10, v8, v10
-; CHECK-RV64-NEXT:    vrsub.vi v9, v9, 0
-; CHECK-RV64-NEXT:    vand.vx v9, v9, a0
-; CHECK-RV64-NEXT:    vsll.vv v8, v8, v9
-; CHECK-RV64-NEXT:    vor.vv v8, v10, v8
-; CHECK-RV64-NEXT:    ret
+; CHECK-LABEL: vror_vx_v1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
+; CHECK-NEXT:    vmv.s.x v9, a0
+; CHECK-NEXT:    li a0, 63
+; CHECK-NEXT:    vand.vx v10, v9, a0
+; CHECK-NEXT:    vsrl.vv v10, v8, v10
+; CHECK-NEXT:    vrsub.vi v9, v9, 0
+; CHECK-NEXT:    vand.vx v9, v9, a0
+; CHECK-NEXT:    vsll.vv v8, v8, v9
+; CHECK-NEXT:    vor.vv v8, v10, v8
+; CHECK-NEXT:    ret
 ;
 ; CHECK-ZVBB-LABEL: vror_vx_v1i64:
 ; CHECK-ZVBB:       # %bb.0:
 ; CHECK-ZVBB-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; CHECK-ZVBB-NEXT:    vror.vx v8, v8, a0
 ; CHECK-ZVBB-NEXT:    ret
   %b.head = insertelement <1 x i64> poison, i64 %b, i32 0
   %b.splat = shufflevector <1 x i64> %b.head, <1 x i64> poison, <1 x i32> zeroinitializer
   %x = call <1 x i64> @llvm.fshr.v1i64(<1 x i64> %a, <1 x i64> %a, <1 x i64> %b.splat)
   ret <1 x i64> %x
 }
 
 define <1 x i64> @vror_vi_v1i64(<1 x i64> %a) {
 ; CHECK-RV32-LABEL: vror_vi_v1i64:
 ; CHECK-RV32:       # %bb.0:
 ; CHECK-RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; CHECK-RV32-NEXT:    vmv.v.i v9, 1
 ; CHECK-RV32-NEXT:    vrsub.vi v9, v9, 0
 ; CHECK-RV32-NEXT:    li a0, 63
 ; CHECK-RV32-NEXT:    vand.vx v9, v9, a0
 ; CHECK-RV32-NEXT:    vsll.vv v9, v8, v9
-; CHECK-RV32-NEXT:    vmv.v.x v10, a0
+; CHECK-RV32-NEXT:    vmv.s.x v10, a0
 ; CHECK-RV32-NEXT:    vand.vi v10, v10, 1
 ; CHECK-RV32-NEXT:    vsrl.vv v8, v8, v10
 ; CHECK-RV32-NEXT:    vor.vv v8, v8, v9
 ; CHECK-RV32-NEXT:    ret
 ;
 ; CHECK-RV64-LABEL: vror_vi_v1i64:
 ; CHECK-RV64:       # %bb.0:
 ; CHECK-RV64-NEXT:    li a0, 63

 ; CHECK-RV32-LABEL: vror_vi_rotl_v1i64:
 ; CHECK-RV32:       # %bb.0:
 ; CHECK-RV32-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
 ; CHECK-RV32-NEXT:    vmv.v.i v9, 1
 ; CHECK-RV32-NEXT:    vrsub.vi v9, v9, 0
 ; CHECK-RV32-NEXT:    li a0, 63
 ; CHECK-RV32-NEXT:    vand.vx v9, v9, a0
 ; CHECK-RV32-NEXT:    vsrl.vv v9, v8, v9
-; CHECK-RV32-NEXT:    vmv.v.x v10, a0
+; CHECK-RV32-NEXT:    vmv.s.x v10, a0
 ; CHECK-RV32-NEXT:    vand.vi v10, v10, 1
 ; CHECK-RV32-NEXT:    vsll.vv v8, v8, v10
 ; CHECK-RV32-NEXT:    vor.vv v8, v8, v9
 ; CHECK-RV32-NEXT:    ret
 ;
 ; CHECK-RV64-LABEL: vror_vi_rotl_v1i64:
 ; CHECK-RV64:       # %bb.0:
 ; CHECK-RV64-NEXT:    li a0, 63