Page MenuHomePhabricator

Please use GitHub pull requests for new patches. Phabricator shutdown timeline

[RISCV] Handle EltType > XLEN case in VMV_V_X_VL to VMV_S_X_VL fold

Authored by reames on Wed, Aug 30, 2:31 PM.



I'd guarded this case in D158874 to avoid regressions, and decided to go investigate what was going on. The solution turns out to be a generic splat matching extension to handle INSERT_SUBVECTOR. In theory, we could see these from other sources as well, but for some reason we only seem to see the i64 extract on rv32 case in practice. Not sure why that is to be honest.

Diff Detail

Event Timeline

reames created this revision.Wed, Aug 30, 2:31 PM
reames requested review of this revision.Wed, Aug 30, 2:31 PM
Herald added a project: Restricted Project. · View Herald TranscriptWed, Aug 30, 2:31 PM
luke added inline comments.Thu, Aug 31, 4:09 AM

Are we getting multiple nested insert_subvectors? If their vector operands are undef shouldn't they be getting combined away? I found this combine in DAGCombiner.cpp:

// Eliminate an intermediate insert into an undef vector:
// insert_subvector undef, (insert_subvector undef, X, 0), N2 -->
// insert_subvector undef, X, N2
if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR &&
    N1.getOperand(0).isUndef() && isNullConstant(N1.getOperand(2)))
  return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, N0,
                     N1.getOperand(1), N2);
reames added inline comments.Thu, Aug 31, 9:59 AM

Not that I saw, I can remove the loop if desired. This is just replacing the "while" with an "if".

This revision is now accepted and ready to land.Fri, Sep 22, 11:43 AM
This revision was landed with ongoing or failed builds.Fri, Sep 22, 1:44 PM
This revision was automatically updated to reflect the committed changes.