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Differential D158590

[RISCV] Fix assertion of getShuffleCost
ClosedPublic

Authored by wangpc on Aug 23 2023, 2:56 AM.

Details

Reviewers
luke
ABataev
craig.topper
reames
Commits
rG9a82bda9dedf: [RISCV] Fix assertion of getShuffleCost
Summary

This assertion is introduced by D157425.

We should calculate the cost iff Mask is not empty.

Fixes 64901

Diff Detail

Event Timeline

wangpc created this revision.Aug 23 2023, 2:56 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 23 2023, 2:56 AM
Herald added subscribers: jobnoorman, sunshaoce, VincentWu and 28 others. · View Herald Transcript
wangpc requested review of this revision.Aug 23 2023, 2:56 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 23 2023, 2:56 AM
Herald added subscribers: llvm-commits, eopXD, MaskRay. · View Herald Transcript
wangpc edited the summary of this revision. (Show Details)Aug 23 2023, 3:25 AM
Harbormaster completed remote builds in B254288: Diff 552641.Aug 23 2023, 3:26 AM
ABataev added inline comments.Aug 23 2023, 4:15 AM
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
364

!Mask.empty()

wangpc updated this revision to Diff 552661.Aug 23 2023, 4:54 AM

Address comment.

ABataev accepted this revision.Aug 23 2023, 4:55 AM

LG

This revision is now accepted and ready to land.Aug 23 2023, 4:55 AM
wangpc updated this revision to Diff 552664.Aug 23 2023, 5:09 AM

move test to reductions.ll.

This revision was landed with ongoing or failed builds.Aug 23 2023, 5:12 AM
Closed by commit rG9a82bda9dedf: [RISCV] Fix assertion of getShuffleCost (authored by wangpc). · Explain Why
This revision was automatically updated to reflect the committed changes.
wangpc added a commit: rG9a82bda9dedf: [RISCV] Fix assertion of getShuffleCost.
Harbormaster completed remote builds in B254305: Diff 552664.Aug 23 2023, 5:46 AM

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
2 lines
test/
Transforms/
SLPVectorizer/
RISCV/
92 lines

Diff 552661

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

Show First 20 Lines • Show All 355 Lines • ▼ Show 20 Lines case TTI::SK_PermuteTwoSrc: {
} }
} }
[[fallthrough]]; [[fallthrough]];
} }
case TTI::SK_Select: { case TTI::SK_Select: {
// We are going to permute multiple sources and the result will be in // We are going to permute multiple sources and the result will be in
// multiple destinations. Providing an accurate cost only for splits where // multiple destinations. Providing an accurate cost only for splits where
// the element type remains the same. // the element type remains the same.
if (LT.first.isValid() && LT.first != 1 && if (!Mask.empty() && LT.first.isValid() && LT.first != 1 &&
ABataevUnsubmitted
Not Done
ReplyInline Actions

!Mask.empty()

ABataev: !Mask.empty()
LT.second.isFixedLengthVector() && LT.second.isFixedLengthVector() &&
LT.second.getVectorElementType().getSizeInBits() == LT.second.getVectorElementType().getSizeInBits() ==
Tp->getElementType()->getPrimitiveSizeInBits() && Tp->getElementType()->getPrimitiveSizeInBits() &&
LT.second.getVectorNumElements() < LT.second.getVectorNumElements() <
cast<FixedVectorType>(Tp)->getNumElements()) { cast<FixedVectorType>(Tp)->getNumElements()) {
unsigned NumRegs = *LT.first.getValue(); unsigned NumRegs = *LT.first.getValue();
unsigned VF = cast<FixedVectorType>(Tp)->getNumElements(); unsigned VF = cast<FixedVectorType>(Tp)->getNumElements();
unsigned SubVF = PowerOf2Ceil(VF / NumRegs); unsigned SubVF = PowerOf2Ceil(VF / NumRegs);
▲ Show 20 Lines • Show All 1,453 Lines • Show Last 20 Lines

llvm/test/Transforms/SLPVectorizer/RISCV/vecreduce.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
; RUN: opt -S -passes=slp-vectorizer < %s -mtriple=riscv64-unknown-linux -mattr=+v | FileCheck %s
define void @vecreduce_or() {
; CHECK-LABEL: define void @vecreduce_or
; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[TMP1:%.*]] = shl i64 0, 0
; CHECK-NEXT: [[TMP2:%.*]] = insertelement <16 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison>, i64 [[TMP1]], i32 15
; CHECK-NEXT: [[TMP3:%.*]] = icmp ult <16 x i64> [[TMP2]], zeroinitializer
; CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x i64> <i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 poison, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0>, i64 [[TMP1]], i32 6
; CHECK-NEXT: [[TMP5:%.*]] = icmp ult <16 x i64> [[TMP4]], zeroinitializer
; CHECK-NEXT: [[TMP6:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP3]])
; CHECK-NEXT: [[TMP7:%.*]] = call i1 @llvm.vector.reduce.or.v16i1(<16 x i1> [[TMP5]])
; CHECK-NEXT: [[OP_RDX:%.*]] = or i1 [[TMP6]], [[TMP7]]
; CHECK-NEXT: br i1 [[OP_RDX]], label [[TMP9:%.*]], label [[TMP8:%.*]]
; CHECK: 8:
; CHECK-NEXT: ret void
; CHECK: 9:
; CHECK-NEXT: ret void
;
%1 = shl i64 0, 0
%2 = icmp ult i64 0, 0
%3 = icmp ult i64 0, 0
%4 = or i1 %2, %3
%5 = icmp ult i64 0, 0
%6 = or i1 %4, %5
%7 = icmp ult i64 0, 0
%8 = or i1 %6, %7
%9 = icmp ult i64 0, 0
%10 = or i1 %8, %9
%11 = icmp ult i64 0, 0
%12 = or i1 %10, %11
%13 = icmp ult i64 0, 0
%14 = or i1 %12, %13
%15 = icmp ult i64 0, 0
%16 = or i1 %14, %15
%17 = icmp ult i64 0, 0
%18 = or i1 %16, %17
%19 = icmp ult i64 0, 0
%20 = or i1 %18, %19
%21 = icmp ult i64 0, 0
%22 = or i1 %20, %21
%23 = icmp ult i64 0, 0
%24 = or i1 %22, %23
%25 = icmp ult i64 0, 0
%26 = or i1 %24, %25
%27 = icmp ult i64 0, 0
%28 = or i1 %26, %27
%29 = icmp ult i64 0, 0
%30 = or i1 %28, %29
%31 = icmp ult i64 %1, 0
%32 = or i1 %30, %31
%33 = icmp ult i64 0, 0
%34 = or i1 %32, %33
%35 = icmp ult i64 0, 0
%36 = or i1 %34, %35
%37 = icmp ult i64 0, 0
%38 = or i1 %36, %37
%39 = icmp ult i64 0, 0
%40 = or i1 %38, %39
%41 = icmp ult i64 0, 0
%42 = or i1 %40, %41
%43 = icmp ult i64 0, 0
%44 = or i1 %42, %43
%45 = icmp ult i64 %1, 0
%46 = or i1 %44, %45
%47 = icmp ult i64 0, 0
%48 = or i1 %46, %47
%49 = icmp ult i64 0, 0
%50 = or i1 %48, %49
%51 = icmp ult i64 0, 0
%52 = or i1 %50, %51
%53 = icmp ult i64 0, 0
%54 = or i1 %52, %53
%55 = icmp ult i64 0, 0
%56 = or i1 %54, %55
%57 = icmp ult i64 0, 0
%58 = or i1 %56, %57
%59 = icmp ult i64 0, 0
%60 = or i1 %58, %59
%61 = icmp ult i64 0, 0
%62 = or i1 %60, %61
%63 = icmp ult i64 0, 0
%64 = or i1 %62, %63
br i1 %64, label %66, label %65
65: ; preds = %0
ret void
66: ; preds = %0
ret void
}