[RISCV] Fix assertion when passing f64 vectors via integer registers

[wangpc]

Summary

The vector arguments are split but assignments won't be pending.

Fixes #64645

[asb]

LGTM (thanks!) with a minor modification: please extend the test case so the argument is actually accessed (by adding a new function or otherwise).

e.g. define <2 x double> @v2f64(<2 x double> %x, <2 x double> %y) { and %1 = fadd <2 x double> %x, %y; ret <2 x double> %1

Such a test also demonstrates that atrociously poor code is generated in that case (copying arguments to and from the stack unnecessarily). It does seem to be correct though. I suspect more attention is needed for zdinx code quality.

One point to note is that if whatever frontend that generated this code is aiming to comply with the standard calling convention, it should be passing that vector in memory (as Clang does).

[asb]

Oh, and please add "Fixes #64645" or similar to the commit message.

[liaolucy]

llvm/test/CodeGen/RISCV/pr64645.ll

9

I have a question, do I need to load and store from the stack here?

eg:
        lw      a2, 12(a1)
        lw      a3, 8(a1)
        lw      a4, 4(a1)
        lw      a1, 0(a1)
        sw      a2, 12(a0)
        sw      a3, 8(a0)
        sw      a4, 4(a0)
        sw      a1, 0(a0)

[wangpc]

Update test.

[wangpc]

llvm/test/CodeGen/RISCV/pr64645.ll

9

The previous test can generate load/store after ISel but these load/store will be deleted during RA as they are not used.
As @asb suggested, I added some operations on arguments so the lowering of arguments will be visible.

[asb]

llvm/test/CodeGen/RISCV/pr64645.ll

6

Nit: we'd normally at nounwind here as there's nothing we're specifically trying to test about the .cfi stuff.

[wangpc]

Add nounwind.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

SmallVectorImpl<ISD::ArgFlagsTy> &PendingArgFlags =
       State.getPendingArgFlags();
 
   assert(PendingLocs.size() == PendingArgFlags.size() &&
          "PendingLocs and PendingArgFlags out of sync");
 
   // Handle passing f64 on RV32D with a soft float ABI or when floating point
   // registers are exhausted.
   if (UseGPRForF64 && XLen == 32 && ValVT == MVT::f64) {
-    assert(!ArgFlags.isSplit() && PendingLocs.empty() &&
-           "Can't lower f64 if it is split");
+    assert(PendingLocs.empty() && "Can't lower f64 if it is split");
     // Depending on available argument GPRS, f64 may be passed in a pair of
     // GPRs, split between a GPR and the stack, or passed completely on the
     // stack. LowerCall/LowerFormalArguments/LowerReturn must recognise these
     // cases.
     Register Reg = State.AllocateReg(ArgGPRs);
     LocVT = MVT::i32;
     if (!Reg) {
       unsigned StackOffset = State.AllocateStack(8, Align(8));

llvm/test/CodeGen/RISCV/pr64645.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32 < %s \
+; RUN:   | FileCheck %s
+
+define <2 x double> @v2f64(<2 x double> %x, <2 x double> %y) nounwind {
+; CHECK-LABEL: v2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw a4, 8(sp)
+; CHECK-NEXT:    sw a5, 12(sp)
+; CHECK-NEXT:    lw a4, 8(sp)
+; CHECK-NEXT:    lw a5, 12(sp)
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    lw a0, 8(sp)
+; CHECK-NEXT:    lw a1, 12(sp)
+; CHECK-NEXT:    sw a6, 8(sp)
+; CHECK-NEXT:    sw a7, 12(sp)
+; CHECK-NEXT:    lw a6, 8(sp)
+; CHECK-NEXT:    lw a7, 12(sp)
+; CHECK-NEXT:    sw a2, 8(sp)
+; CHECK-NEXT:    sw a3, 12(sp)
+; CHECK-NEXT:    lw a2, 8(sp)
+; CHECK-NEXT:    lw a3, 12(sp)
+; CHECK-NEXT:    fadd.d a2, a2, a6
+; CHECK-NEXT:    fadd.d a0, a0, a4
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    lw a0, 8(sp)
+; CHECK-NEXT:    lw a1, 12(sp)
+; CHECK-NEXT:    sw a2, 8(sp)
+; CHECK-NEXT:    sw a3, 12(sp)
+; CHECK-NEXT:    lw a2, 8(sp)
+; CHECK-NEXT:    lw a3, 12(sp)
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %1 = fadd <2 x double> %x, %y
+  ret <2 x double> %1
+}