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[RISCV] Scalarize binop followed by extractelement to custom lowered instruction
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Authored by Jim on Jul 31 2023, 7:14 AM.

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Summary

isOperationLegalOrCustomOrPromote returns true only if VT is other or legal
and operation action is Legal, Custom or Promote.
Permit a vector binary operation can be converted to scalar binary operation which is custom lowered with illegal type.
One of cases is i32 isn't a legal type on RV64 and its ALU operations is set to custom lowering,
so vadd for element type i32 can be converted to addw.

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Event Timeline

Jim created this revision.Jul 31 2023, 7:14 AM
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Jim requested review of this revision.Jul 31 2023, 7:14 AM
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craig.topper added inline comments.Jul 31 2023, 7:29 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
1857–1858

Can we use isOperationLegalOrCustomOrPromote?

Jim updated this revision to Diff 545661.Jul 31 2023, 7:49 AM

Address @craig.topper's comment

craig.topper added inline comments.Jul 31 2023, 7:50 AM
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
1858

Do we still need the || isOperationCustom(Opc, ScalarVT)?

Jim marked 2 inline comments as done.Jul 31 2023, 7:59 AM
Jim added inline comments.
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
1858

isOperationLegalOrCustomOrPromote(Opc, ScalarVT) would return false for that i32 type (is not legal) with custom lowering operation on RV64 (ADDW, ADDIW, SUBW, ...).

bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT,
                                         bool LegalOnly = false) const {
    if (LegalOnly)
      return isOperationLegal(Op, VT);
 
    return (VT == MVT::Other || isTypeLegal(VT)) &&
      (getOperationAction(Op, VT) == Legal ||
       getOperationAction(Op, VT) == Custom ||
       getOperationAction(Op, VT) == Promote);
  }

isOperationCustom(Opc, ScalarVT) is for ADDW, ADDIW, SUBW ... can be scalarized to.

It's not clear to me this should be restricted to i64 and i32 either. An i16 or i8 add for example doesn't require any extra code unless the result needs to be sign/zero extended.

Jim marked an inline comment as done.Jul 31 2023, 6:49 PM

It's not clear to me this should be restricted to i64 and i32 either. An i16 or i8 add for example doesn't require any extra code unless the result needs to be sign/zero extended.

It doesn't need to be restricted to i64 or i32 either. i32 type ALU operation on RV64 is one of cases here (Maybe is only case in all of tests we had now).
The change of this patch is if any type is not legal, but its operation action is set to custom. That we permit a vector binary operation can be converted to it. (one of cases here is vadd for element type i32 can be converted to addw).
Thanks for your feedback.

Jim retitled this revision from [RISCV] Scalarize binop followed by extractelement to W instruction on RV64 to [RISCV] Scalarize binop followed by extractelement to custom lowered instruction.Jul 31 2023, 7:00 PM
Jim edited the summary of this revision. (Show Details)
Jim edited the summary of this revision. (Show Details)
This revision is now accepted and ready to land.Aug 1 2023, 3:49 PM
Jim updated this revision to Diff 546293.Aug 1 2023, 7:13 PM

Update comment.

jacquesguan accepted this revision.Aug 2 2023, 12:27 AM
This revision was landed with ongoing or failed builds.Aug 2 2023, 10:03 PM
This revision was automatically updated to reflect the committed changes.