[RISCV] Use the stack for MVT::f16 for fastcc when there are no other registers available

[eopXD]

Summary

In D155502, we added code for the compiler to check GPR-s for f16
under zhinx. This commit adds code to hit the stack when we run out of
GPR-s.

With this patch and D155502, resolves #63922

[eopXD]

Add test coverage

[craig.topper]

The title of this commit isn't very informative. Should mention calls and fastcc.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

bool RISCV::CC_RISCV_FastCC(const DataLayout &DL, RISCVABI::ABI ABI,
   if (LocVT == MVT::f16 || LocVT == MVT::f32 ||
       (LocVT == MVT::f64 && Subtarget.is64Bit())) {
     if (unsigned Reg = State.AllocateReg(GPRList)) {
       State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
       return false;
     }
   }
 
+  if (LocVT == MVT::f16) {
+    unsigned Offset2 = State.AllocateStack(2, Align(2));
+    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
+    return false;
+  }
+
   if (LocVT == MVT::i32 || LocVT == MVT::f32) {
     unsigned Offset4 = State.AllocateStack(4, Align(4));
     State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo));
     return false;
   }
 
   if (LocVT == MVT::i64 || LocVT == MVT::f64) {
     unsigned Offset5 = State.AllocateStack(8, Align(8));