[GlobalISel] Generalize `InstructionSelector` Match Tables

[Pierre-vh]

Summary

Makes InstructionSelector.h/InstructionSelectorImpl.h generic so the match tables can also be used for the combiner.

Some notes:

• Coverage was made an optional parameter of executeMatchTable, combines won't use it for now.
• GIPFP_ -> GICXXPred_ so it's more generic. Those are just C++ predicates and aren't PatFrag-specific.
• Pass the MatcherState directly to testMIPredicate_MI, the combiner will need it.

[arsenm]

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h

77–80

What's the point of having 4 copies of 0?

448–451

wrong word why

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h

328–329

could this be a const reference? I guess this is a preexisting issue

[Pierre-vh]

Address comments

[Pierre-vh]

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h

77–80

(It was here before, I didn't touch it, just moved it) No point really. I'd be fine with just having a GICXXPred_Invalid

Though, if that's ok, I'd rather fix it in a later diff such as D153757 (which adds more flags here). It makes rebasing less annoying, and none of those patch land unless they all land anyway.

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h

328–329

It was indeed already there but I fixed it anyway, and also fixed the APInt one.

[arsenm]

This is just renaming things anyway

[foad]

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h

456

Hi @Pierre-vh, after merging this patch into a downstream branch I find I have to write this in some of our C++ combines:

struct KnownBits Op0KnownBits = KnownBits->getKnownBits(Reg0);

This is a bit ugly because of the name clash between the KnownBits struct and this KnownBits field. I guess this is not a new problem, since you did not change this line, but it is now affecting more code.

Do you think it would make sense to change the name of this field?

[Pierre-vh]

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h

456

Sure, I wouldn't mind changing the name. Should we just name it KB?
Do you want me to make a patch?

Those fields really ought to be cleaned-up some day anyway. Once the older backend is removed I plan to do a pass over this code and eliminate as much redundancy as possible. Things aren't a good state right now because we still need to allow downstream users to use the older combiner backend. e.g. the whole "CombinerInfo" class is useless with the new combiner.

[foad]

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h

456

Yes KB sounds good to me, thanks!

If CombinerInfo is useless with the new scheme then can we get rid of AMDGPU derived classes like AMDGPUPostLegalizerCombinerInfo right now?

[Pierre-vh]

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h

456

We could but it wouldn't give us anything I think. IIRC there's also some things that expect a CombinerInfo derived class.
I want to get rid of CombinerInfo directly and make the Combiner pass structure similar to ISel. It's going to be a breaking change for downstream users of the old backend so I'm waiting until it's been deprecated for a few weeks

[Pierre-vh]

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h

456

D155082

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h

-//===- llvm/CodeGen/GlobalISel/InstructionSelector.h ------------*- C++ -*-===//
+//===- llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h -----------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-/// \file This file declares the API for the instruction selector.
-/// This class is responsible for selecting machine instructions.
-/// It's implemented by the target. It's used by the InstructionSelect pass.
+/// \file This file declares the GIMatchTableExecutor API, the opcodes supported
+/// by the match table, and some associated data structures used by the
+/// executor's implementation (see `GIMatchTableExecutorImpl.h`).
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
-#define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
+#ifndef LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
+#define LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H
 
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/GlobalISel/Utils.h"
 #include "llvm/CodeGen/LowLevelType.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/IR/Function.h"
 #include <bitset>

 class RegisterBankInfo;
 class TargetInstrInfo;
 class TargetRegisterInfo;
 
 /// Container class for CodeGen predicate results.
 /// This is convenient because std::bitset does not have a constructor
 /// with an initializer list of set bits.
 ///
-/// Each InstructionSelector subclass should define a PredicateBitset class
+/// Each GIMatchTableExecutor subclass should define a PredicateBitset class
 /// with:
 ///   const unsigned MAX_SUBTARGET_PREDICATES = 192;
 ///   using PredicateBitset = PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
 /// and updating the constant to suit the target. Tablegen provides a suitable
 /// definition for the predicates in use in <Target>GenGlobalISel.inc when
 /// GET_GLOBALISEL_PREDICATE_BITSET is defined.
 template <std::size_t MaxPredicates>
 class PredicateBitsetImpl : public std::bitset<MaxPredicates> {
 public:
   // Cannot inherit constructors because it's not supported by VC++..
   PredicateBitsetImpl() = default;
 
   PredicateBitsetImpl(const std::bitset<MaxPredicates> &B)
       : std::bitset<MaxPredicates>(B) {}
 
   PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
     for (auto I : Init)
       std::bitset<MaxPredicates>::set(I);
   }
 };
 
 enum {
+  GICXXPred_I64_Invalid = 0,
+  GICXXPred_APInt_Invalid = 0,
+  GICXXPred_APFloat_Invalid = 0,
+  GICXXPred_MI_Invalid = 0,
+};
+
+enum {
   /// Begin a try-block to attempt a match and jump to OnFail if it is
   /// unsuccessful.
   /// - OnFail - The MatchTable entry at which to resume if the match fails.
   ///
   /// FIXME: This ought to take an argument indicating the number of try-blocks
   ///        to exit on failure. It's usually one but the last match attempt of
   ///        a block will need more. The (implemented) alternative is to tack a
   ///        GIM_Reject on the end of each try-block which is simpler but

 };
 
 enum {
   /// Indicates the end of the variable-length MergeInsnID list in a
   /// GIR_MergeMemOperands opcode.
   GIU_MergeMemOperands_EndOfList = -1,
 };
 
-/// Provides the logic to select generic machine instructions.
-class InstructionSelector {
+/// Provides the logic to execute GlobalISel match tables, which are used by the
+/// instruction selector and instruction combiners as their engine to match and
+/// apply MIR patterns.
+class GIMatchTableExecutor {
 public:
-  virtual ~InstructionSelector() = default;
-
-  /// Select the (possibly generic) instruction \p I to only use target-specific
-  /// opcodes. It is OK to insert multiple instructions, but they cannot be
-  /// generic pre-isel instructions.
-  ///
-  /// \returns whether selection succeeded.
-  /// \pre  I.getParent() && I.getParent()->getParent()
-  /// \post
-  ///   if returns true:
-  ///     for I in all mutated/inserted instructions:
-  ///       !isPreISelGenericOpcode(I.getOpcode())
-  virtual bool select(MachineInstr &I) = 0;
+  virtual ~GIMatchTableExecutor() = default;
 
   CodeGenCoverage *CoverageInfo = nullptr;
   GISelKnownBits *KnownBits = nullptr;
   MachineFunction *MF = nullptr;
   ProfileSummaryInfo *PSI = nullptr;
   BlockFrequencyInfo *BFI = nullptr;
   // For some predicates, we need to track the current MBB.
   MachineBasicBlock *CurMBB = nullptr;
 
   virtual void setupGeneratedPerFunctionState(MachineFunction &MF) {
     llvm_unreachable("TableGen should have emitted implementation");
   }
 
-  /// Setup per-MF selector state.
+  /// Setup per-MF executor state.
   virtual void setupMF(MachineFunction &mf, GISelKnownBits *KB,
                        CodeGenCoverage &covinfo, ProfileSummaryInfo *psi,
                        BlockFrequencyInfo *bfi) {
     CoverageInfo = &covinfo;
     KnownBits = KB;
     MF = &mf;
     PSI = psi;
     BFI = bfi;
bool shouldOptForSize(const MachineFunction *MF) const {
     const auto &F = MF->getFunction();
     return F.hasOptSize() || F.hasMinSize() ||
            (PSI && BFI && CurMBB && llvm::shouldOptForSize(*CurMBB, PSI, BFI));
   }
 
 public:
   template <class PredicateBitset, class ComplexMatcherMemFn,
             class CustomRendererFn>
-  struct ISelInfoTy {
-    ISelInfoTy(const LLT *TypeObjects, size_t NumTypeObjects,
+  struct ExecInfoTy {
+    ExecInfoTy(const LLT *TypeObjects, size_t NumTypeObjects,
                const PredicateBitset *FeatureBitsets,
                const ComplexMatcherMemFn *ComplexPredicates,
                const CustomRendererFn *CustomRenderers)
-        : TypeObjects(TypeObjects),
-          FeatureBitsets(FeatureBitsets),
+        : TypeObjects(TypeObjects), FeatureBitsets(FeatureBitsets),
           ComplexPredicates(ComplexPredicates),
           CustomRenderers(CustomRenderers) {
 
       for (size_t I = 0; I < NumTypeObjects; ++I)
         TypeIDMap[TypeObjects[I]] = I;
     }
     const LLT *TypeObjects;
     const PredicateBitset *FeatureBitsets;
     const ComplexMatcherMemFn *ComplexPredicates;
     const CustomRendererFn *CustomRenderers;
 
     SmallDenseMap<LLT, unsigned, 64> TypeIDMap;
   };
 
 protected:
-  InstructionSelector();
+  GIMatchTableExecutor();
 
   /// Execute a given matcher table and return true if the match was successful
   /// and false otherwise.
-  template <class TgtInstructionSelector, class PredicateBitset,
-            class ComplexMatcherMemFn, class CustomRendererFn>
+  template <class TgtExecutor, class PredicateBitset, class ComplexMatcherMemFn,
+            class CustomRendererFn>
   bool executeMatchTable(
-      TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State,
-      const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn>
+      TgtExecutor &Exec, NewMIVector &OutMIs, MatcherState &State,
+      const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn>
           &ISelInfo,
       const int64_t *MatchTable, const TargetInstrInfo &TII,
       MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
       const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
-      CodeGenCoverage &CoverageInfo) const;
+      CodeGenCoverage *CoverageInfo) const;
 
   virtual const int64_t *getMatchTable() const {
     llvm_unreachable("Should have been overridden by tablegen if used");
   }
 
   virtual bool testImmPredicate_I64(unsigned, int64_t) const {
     llvm_unreachable(
         "Subclasses must override this with a tablegen-erated function");
   }
   virtual bool testImmPredicate_APInt(unsigned, const APInt &) const {
     llvm_unreachable(
         "Subclasses must override this with a tablegen-erated function");
   }
   virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const {
     llvm_unreachable(
         "Subclasses must override this with a tablegen-erated function");
   }
-  virtual bool testMIPredicate_MI(
-      unsigned, const MachineInstr &,
-      const std::array<const MachineOperand *, 3> &Operands) const {
+  virtual bool testMIPredicate_MI(unsigned, const MachineInstr &,
+                                  const MatcherState &State) const {
     llvm_unreachable(
         "Subclasses must override this with a tablegen-erated function");
   }
 
   bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
                          const MachineRegisterInfo &MRI) const;
 
-  /// Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the
-  /// right-hand side. GlobalISel's separation of pointer and integer types
+  /// Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on
+  /// the right-hand side. GlobalISel's separation of pointer and integer types
   /// means that we don't need to worry about G_OR with equivalent semantics.
   bool isBaseWithConstantOffset(const MachineOperand &Root,
                                 const MachineRegisterInfo &MRI) const;
 
   /// Return true if MI can obviously be folded into IntoMI.
   /// MI and IntoMI do not need to be in the same basic blocks, but MI must
   /// preceed IntoMI.
   bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const;
 };
 
 } // end namespace llvm
 
-#endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
+#endif // LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTOR_H

llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h

-//===- llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h --------*- C++ -*-===//
+//===- llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h -------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
-/// \file This file declares the API for the instruction selector.
-/// This class is responsible for selecting machine instructions.
-/// It's implemented by the target. It's used by the InstructionSelect pass.
+/// \file This file implements GIMatchTableExecutor's `executeMatchTable`
+/// function. This is implemented in a separate file because the function is
+/// quite large.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
-#define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
+#ifndef LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTORIMPL_H
+#define LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTORIMPL_H
 
 #include "llvm/ADT/SmallVector.h"
-#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h"
 #include "llvm/CodeGen/GlobalISel/Utils.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RegisterBankInfo.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/CodeGen/TargetOpcodes.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/DataLayout.h"
 #include "llvm/Support/CodeGenCoverage.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
 #include <cassert>
 #include <cstddef>
 #include <cstdint>
 
 namespace llvm {
 
-/// GlobalISel PatFrag Predicates
-enum {
-  GIPFP_I64_Invalid = 0,
-  GIPFP_APInt_Invalid = 0,
-  GIPFP_APFloat_Invalid = 0,
-  GIPFP_MI_Invalid = 0,
-};
-
-template <class TgtInstructionSelector, class PredicateBitset,
-          class ComplexMatcherMemFn, class CustomRendererFn>
-bool InstructionSelector::executeMatchTable(
-    TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State,
-    const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn>
-        &ISelInfo,
+template <class TgtExecutor, class PredicateBitset, class ComplexMatcherMemFn,
+          class CustomRendererFn>
+bool GIMatchTableExecutor::executeMatchTable(
+    TgtExecutor &Exec, NewMIVector &OutMIs, MatcherState &State,
+    const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn>
+        &ExecInfo,
     const int64_t *MatchTable, const TargetInstrInfo &TII,
     MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
     const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
-    CodeGenCoverage &CoverageInfo) const {
+    CodeGenCoverage *CoverageInfo) const {
 
   uint64_t CurrentIdx = 0;
   SmallVector<uint64_t, 4> OnFailResumeAt;
 
   // Bypass the flag check on the instruction, and only look at the MCInstrDesc.
   bool NoFPException = !State.MIs[0]->getDesc().mayRaiseFPException();
 
   const uint16_t Flags = State.MIs[0]->getFlags();
 
   enum RejectAction { RejectAndGiveUp, RejectAndResume };
   auto handleReject = [&]() -> RejectAction {
-    DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+    DEBUG_WITH_TYPE(TgtExecutor::getName(),
                     dbgs() << CurrentIdx << ": Rejected\n");
     if (OnFailResumeAt.empty())
       return RejectAndGiveUp;
     CurrentIdx = OnFailResumeAt.pop_back_val();
-    DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+    DEBUG_WITH_TYPE(TgtExecutor::getName(),
                     dbgs() << CurrentIdx << ": Resume at " << CurrentIdx << " ("
                            << OnFailResumeAt.size() << " try-blocks remain)\n");
     return RejectAndResume;
   };
 
   auto propagateFlags = [=](NewMIVector &OutMIs) {
     for (auto MIB : OutMIs) {
       // Set the NoFPExcept flag when no original matched instruction could
       // raise an FP exception, but the new instruction potentially might.
       uint16_t MIBFlags = Flags;
       if (NoFPException && MIB->mayRaiseFPException())
         MIBFlags |= MachineInstr::NoFPExcept;
       MIB.setMIFlags(MIBFlags);
     }
 
     return true;
   };
 
   while (true) {
     assert(CurrentIdx != ~0u && "Invalid MatchTable index");
     int64_t MatcherOpcode = MatchTable[CurrentIdx++];
     switch (MatcherOpcode) {
     case GIM_Try: {
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": Begin try-block\n");
       OnFailResumeAt.push_back(MatchTable[CurrentIdx++]);
       break;
     }
 
     case GIM_RecordInsn:
     case GIM_RecordInsnIgnoreCopies: {
       int64_t NewInsnID = MatchTable[CurrentIdx++];
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
 
       // As an optimisation we require that MIs[0] is always the root. Refuse
       // any attempt to modify it.
       assert(NewInsnID != 0 && "Refusing to modify MIs[0]");
 
       MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
       if (!MO.isReg()) {
-        DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+        DEBUG_WITH_TYPE(TgtExecutor::getName(),
                         dbgs() << CurrentIdx << ": Not a register\n");
         if (handleReject() == RejectAndGiveUp)
           return false;
         break;
       }
       if (MO.getReg().isPhysical()) {
-        DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+        DEBUG_WITH_TYPE(TgtExecutor::getName(),
                         dbgs() << CurrentIdx << ": Is a physical register\n");
         if (handleReject() == RejectAndGiveUp)
           return false;
         break;
       }
 
       MachineInstr *NewMI;
       if (MatcherOpcode == GIM_RecordInsnIgnoreCopies)
         NewMI = getDefIgnoringCopies(MO.getReg(), MRI);
       else
         NewMI = MRI.getVRegDef(MO.getReg());
 
       if ((size_t)NewInsnID < State.MIs.size())
         State.MIs[NewInsnID] = NewMI;
       else {
         assert((size_t)NewInsnID == State.MIs.size() &&
                "Expected to store MIs in order");
         State.MIs.push_back(NewMI);
       }
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": MIs[" << NewInsnID
                              << "] = GIM_RecordInsn(" << InsnID << ", " << OpIdx
                              << ")\n");
       break;
     }
 
     case GIM_CheckFeatures: {
       int64_t ExpectedBitsetID = MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx
                              << ": GIM_CheckFeatures(ExpectedBitsetID="
                              << ExpectedBitsetID << ")\n");
-      if ((AvailableFeatures & ISelInfo.FeatureBitsets[ExpectedBitsetID]) !=
-          ISelInfo.FeatureBitsets[ExpectedBitsetID]) {
+      if ((AvailableFeatures & ExecInfo.FeatureBitsets[ExpectedBitsetID]) !=
+          ExecInfo.FeatureBitsets[ExpectedBitsetID]) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       }
       break;
     }
-
     case GIM_CheckOpcode:
     case GIM_CheckOpcodeIsEither: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t Expected0 = MatchTable[CurrentIdx++];
       int64_t Expected1 = -1;
       if (MatcherOpcode == GIM_CheckOpcodeIsEither)
         Expected1 = MatchTable[CurrentIdx++];
 
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       unsigned Opcode = State.MIs[InsnID]->getOpcode();
 
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_CheckOpcode(MIs[" << InsnID
                              << "], ExpectedOpcode=" << Expected0;
-        if (MatcherOpcode == GIM_CheckOpcodeIsEither)
-          dbgs() << " || " << Expected1;
-        dbgs() << ") // Got=" << Opcode << "\n";
-      );
+                      if (MatcherOpcode == GIM_CheckOpcodeIsEither) dbgs()
+                      << " || " << Expected1;
+                      dbgs() << ") // Got=" << Opcode << "\n";);
 
       if (Opcode != Expected0 && Opcode != Expected1) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       }
       break;
     }
     case GIM_SwitchOpcode: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t LowerBound = MatchTable[CurrentIdx++];
       int64_t UpperBound = MatchTable[CurrentIdx++];
       int64_t Default = MatchTable[CurrentIdx++];
 
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       const int64_t Opcode = State.MIs[InsnID]->getOpcode();
 
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(), {
+      DEBUG_WITH_TYPE(TgtExecutor::getName(), {
         dbgs() << CurrentIdx << ": GIM_SwitchOpcode(MIs[" << InsnID << "], ["
                << LowerBound << ", " << UpperBound << "), Default=" << Default
                << ", JumpTable...) // Got=" << Opcode << "\n";
       });
       if (Opcode < LowerBound || UpperBound <= Opcode) {
         CurrentIdx = Default;
         break;
       }
case GIM_SwitchType: {
       int64_t OpIdx = MatchTable[CurrentIdx++];
       int64_t LowerBound = MatchTable[CurrentIdx++];
       int64_t UpperBound = MatchTable[CurrentIdx++];
       int64_t Default = MatchTable[CurrentIdx++];
 
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
 
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(), {
+      DEBUG_WITH_TYPE(TgtExecutor::getName(), {
         dbgs() << CurrentIdx << ": GIM_SwitchType(MIs[" << InsnID
                << "]->getOperand(" << OpIdx << "), [" << LowerBound << ", "
                << UpperBound << "), Default=" << Default
                << ", JumpTable...) // Got=";
         if (!MO.isReg())
           dbgs() << "Not a VReg\n";
         else
           dbgs() << MRI.getType(MO.getReg()) << "\n";
       });
       if (!MO.isReg()) {
         CurrentIdx = Default;
         break;
       }
       const LLT Ty = MRI.getType(MO.getReg());
-      const auto TyI = ISelInfo.TypeIDMap.find(Ty);
-      if (TyI == ISelInfo.TypeIDMap.end()) {
+      const auto TyI = ExecInfo.TypeIDMap.find(Ty);
+      if (TyI == ExecInfo.TypeIDMap.end()) {
         CurrentIdx = Default;
         break;
       }
       const int64_t TypeID = TyI->second;
       if (TypeID < LowerBound || UpperBound <= TypeID) {
         CurrentIdx = Default;
         break;
       }
       CurrentIdx = MatchTable[CurrentIdx + (TypeID - LowerBound)];
       if (!CurrentIdx) {
         CurrentIdx = Default;
         break;
       }
       OnFailResumeAt.push_back(Default);
       break;
     }
 
     case GIM_CheckNumOperands: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t Expected = MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_CheckNumOperands(MIs["
                              << InsnID << "], Expected=" << Expected << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       if (State.MIs[InsnID]->getNumOperands() != Expected) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       }
       break;
     }
     case GIM_CheckI64ImmPredicate:
     case GIM_CheckImmOperandPredicate: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatcherOpcode == GIM_CheckImmOperandPredicate
                           ? MatchTable[CurrentIdx++]
                           : 1;
       int64_t Predicate = MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_CheckImmPredicate(MIs["
                              << InsnID << "]->getOperand(" << OpIdx
                              << "), Predicate=" << Predicate << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       assert((State.MIs[InsnID]->getOperand(OpIdx).isImm() ||
               State.MIs[InsnID]->getOperand(OpIdx).isCImm()) &&
              "Expected immediate operand");
-      assert(Predicate > GIPFP_I64_Invalid && "Expected a valid predicate");
+      assert(Predicate > GICXXPred_I64_Invalid && "Expected a valid predicate");
       int64_t Value = 0;
       if (State.MIs[InsnID]->getOperand(OpIdx).isCImm())
         Value = State.MIs[InsnID]->getOperand(OpIdx).getCImm()->getSExtValue();
       else if (State.MIs[InsnID]->getOperand(OpIdx).isImm())
         Value = State.MIs[InsnID]->getOperand(OpIdx).getImm();
       else
         llvm_unreachable("Expected Imm or CImm operand");
 
       if (!testImmPredicate_I64(Predicate, Value))
         if (handleReject() == RejectAndGiveUp)
           return false;
       break;
     }
     case GIM_CheckAPIntImmPredicate: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t Predicate = MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs()
                           << CurrentIdx << ": GIM_CheckAPIntImmPredicate(MIs["
                           << InsnID << "], Predicate=" << Predicate << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_CONSTANT &&
              "Expected G_CONSTANT");
-      assert(Predicate > GIPFP_APInt_Invalid && "Expected a valid predicate");
-      APInt Value;
-      if (State.MIs[InsnID]->getOperand(1).isCImm())
-        Value = State.MIs[InsnID]->getOperand(1).getCImm()->getValue();
-      else
+      assert(Predicate > GICXXPred_APInt_Invalid &&
+             "Expected a valid predicate");
+      if (!State.MIs[InsnID]->getOperand(1).isCImm())
         llvm_unreachable("Expected Imm or CImm operand");
 
+      const APInt &Value =
+          State.MIs[InsnID]->getOperand(1).getCImm()->getValue();
       if (!testImmPredicate_APInt(Predicate, Value))
         if (handleReject() == RejectAndGiveUp)
           return false;
       break;
     }
     case GIM_CheckAPFloatImmPredicate: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t Predicate = MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs()
                           << CurrentIdx << ": GIM_CheckAPFloatImmPredicate(MIs["
                           << InsnID << "], Predicate=" << Predicate << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       assert(State.MIs[InsnID]->getOpcode() == TargetOpcode::G_FCONSTANT &&
              "Expected G_FCONSTANT");
-      assert(State.MIs[InsnID]->getOperand(1).isFPImm() && "Expected FPImm operand");
-      assert(Predicate > GIPFP_APFloat_Invalid && "Expected a valid predicate");
-      APFloat Value = State.MIs[InsnID]->getOperand(1).getFPImm()->getValueAPF();
+      assert(State.MIs[InsnID]->getOperand(1).isFPImm() &&
+             "Expected FPImm operand");
+      assert(Predicate > GICXXPred_APFloat_Invalid &&
+             "Expected a valid predicate");
+      const APFloat &Value =
+          State.MIs[InsnID]->getOperand(1).getFPImm()->getValueAPF();
 
       if (!testImmPredicate_APFloat(Predicate, Value))
         if (handleReject() == RejectAndGiveUp)
           return false;
       break;
     }
     case GIM_CheckIsBuildVectorAllOnes:
     case GIM_CheckIsBuildVectorAllZeros: {
       int64_t InsnID = MatchTable[CurrentIdx++];
 
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx
                              << ": GIM_CheckBuildVectorAll{Zeros|Ones}(MIs["
                              << InsnID << "])\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
 
       const MachineInstr *MI = State.MIs[InsnID];
       assert((MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR ||
               MI->getOpcode() == TargetOpcode::G_BUILD_VECTOR_TRUNC) &&
case GIM_CheckIsBuildVectorAllZeros: {
         }
       }
 
       break;
     }
     case GIM_CheckCxxInsnPredicate: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t Predicate = MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs()
                           << CurrentIdx << ": GIM_CheckCxxPredicate(MIs["
                           << InsnID << "], Predicate=" << Predicate << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
-      assert(Predicate > GIPFP_MI_Invalid && "Expected a valid predicate");
+      assert(Predicate > GICXXPred_MI_Invalid && "Expected a valid predicate");
 
-      if (!testMIPredicate_MI(Predicate, *State.MIs[InsnID],
-                              State.RecordedOperands))
+      if (!testMIPredicate_MI(Predicate, *State.MIs[InsnID], State))
         if (handleReject() == RejectAndGiveUp)
           return false;
       break;
     }
     case GIM_CheckHasNoUse: {
       int64_t InsnID = MatchTable[CurrentIdx++];
 
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_CheckHasNoUse(MIs["
                              << InsnID << "]\n");
 
       const MachineInstr *MI = State.MIs[InsnID];
       assert(MI && "Used insn before defined");
       assert(MI->getNumDefs() > 0 && "No defs");
       const Register Res = MI->getOperand(0).getReg();
 
       if (!MRI.use_nodbg_empty(Res)) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       }
 
       break;
     }
     case GIM_CheckAtomicOrdering: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_CheckAtomicOrdering(MIs["
                              << InsnID << "], " << (uint64_t)Ordering << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       if (!State.MIs[InsnID]->hasOneMemOperand())
         if (handleReject() == RejectAndGiveUp)
           return false;
 
       for (const auto &MMO : State.MIs[InsnID]->memoperands())
         if (MMO->getMergedOrdering() != Ordering)
           if (handleReject() == RejectAndGiveUp)
             return false;
       break;
     }
     case GIM_CheckAtomicOrderingOrStrongerThan: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx
                              << ": GIM_CheckAtomicOrderingOrStrongerThan(MIs["
                              << InsnID << "], " << (uint64_t)Ordering << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       if (!State.MIs[InsnID]->hasOneMemOperand())
         if (handleReject() == RejectAndGiveUp)
           return false;
 
       for (const auto &MMO : State.MIs[InsnID]->memoperands())
         if (!isAtLeastOrStrongerThan(MMO->getMergedOrdering(), Ordering))
           if (handleReject() == RejectAndGiveUp)
             return false;
       break;
     }
     case GIM_CheckAtomicOrderingWeakerThan: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       AtomicOrdering Ordering = (AtomicOrdering)MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx
                              << ": GIM_CheckAtomicOrderingWeakerThan(MIs["
                              << InsnID << "], " << (uint64_t)Ordering << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       if (!State.MIs[InsnID]->hasOneMemOperand())
         if (handleReject() == RejectAndGiveUp)
           return false;
 
case GIM_CheckMemoryAddressSpace: {
           return false;
         break;
       }
 
       // Need to still jump to the end of the list of address spaces if we find
       // a match earlier.
       const uint64_t LastIdx = CurrentIdx + NumAddrSpace;
 
-      const MachineMemOperand *MMO
-        = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
+      const MachineMemOperand *MMO =
+          *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
       const unsigned MMOAddrSpace = MMO->getAddrSpace();
 
       bool Success = false;
       for (int I = 0; I != NumAddrSpace; ++I) {
         unsigned AddrSpace = MatchTable[CurrentIdx++];
-        DEBUG_WITH_TYPE(
-          TgtInstructionSelector::getName(),
+        DEBUG_WITH_TYPE(TgtExecutor::getName(),
                         dbgs() << "addrspace(" << MMOAddrSpace << ") vs "
                                << AddrSpace << '\n');
 
         if (AddrSpace == MMOAddrSpace) {
           Success = true;
           break;
         }
       }
 
       CurrentIdx = LastIdx;
case GIM_CheckMemoryAlignment: {
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
 
       if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
         if (handleReject() == RejectAndGiveUp)
           return false;
         break;
       }
 
-      MachineMemOperand *MMO
-        = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      MachineMemOperand *MMO =
+          *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_CheckMemoryAlignment"
-                      << "(MIs[" << InsnID << "]->memoperands() + " << MMOIdx
-                      << ")->getAlignment() >= " << MinAlign << ")\n");
+                             << "(MIs[" << InsnID << "]->memoperands() + "
+                             << MMOIdx << ")->getAlignment() >= " << MinAlign
+                             << ")\n");
       if (MMO->getAlign() < MinAlign && handleReject() == RejectAndGiveUp)
         return false;
 
       break;
     }
     case GIM_CheckMemorySizeEqualTo: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t MMOIdx = MatchTable[CurrentIdx++];
       uint64_t Size = MatchTable[CurrentIdx++];
 
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
-                      dbgs() << CurrentIdx
-                             << ": GIM_CheckMemorySizeEqual(MIs[" << InsnID
-                             << "]->memoperands() + " << MMOIdx
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
+                      dbgs() << CurrentIdx << ": GIM_CheckMemorySizeEqual(MIs["
+                             << InsnID << "]->memoperands() + " << MMOIdx
                              << ", Size=" << Size << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
 
       if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
         if (handleReject() == RejectAndGiveUp)
           return false;
         break;
       }
 
-      MachineMemOperand *MMO = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
+      MachineMemOperand *MMO =
+          *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
 
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
-                      dbgs() << MMO->getSize() << " bytes vs " << Size
+      DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << MMO->getSize()
+                                                     << " bytes vs " << Size
                                                      << " bytes\n");
       if (MMO->getSize() != Size)
         if (handleReject() == RejectAndGiveUp)
           return false;
 
       break;
     }
     case GIM_CheckMemorySizeEqualToLLT:
     case GIM_CheckMemorySizeLessThanLLT:
     case GIM_CheckMemorySizeGreaterThanLLT: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t MMOIdx = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
 
       DEBUG_WITH_TYPE(
-          TgtInstructionSelector::getName(),
+          TgtExecutor::getName(),
           dbgs() << CurrentIdx << ": GIM_CheckMemorySize"
-                 << (MatcherOpcode == GIM_CheckMemorySizeEqualToLLT
-                         ? "EqualTo"
-                         : MatcherOpcode == GIM_CheckMemorySizeGreaterThanLLT
-                               ? "GreaterThan"
-                               : "LessThan")
+                 << (MatcherOpcode == GIM_CheckMemorySizeEqualToLLT ? "EqualTo"
                  << "LLT(MIs[" << InsnID << "]->memoperands() + " << MMOIdx
                  << ", OpIdx=" << OpIdx << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
 
       MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
       if (!MO.isReg()) {
-        DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+        DEBUG_WITH_TYPE(TgtExecutor::getName(),
                         dbgs() << CurrentIdx << ": Not a register\n");
         if (handleReject() == RejectAndGiveUp)
           return false;
         break;
       }
 
       if (State.MIs[InsnID]->getNumMemOperands() <= MMOIdx) {
         if (handleReject() == RejectAndGiveUp)
           return false;
         break;
       }
 
-      MachineMemOperand *MMO = *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
+      MachineMemOperand *MMO =
+          *(State.MIs[InsnID]->memoperands_begin() + MMOIdx);
 
       unsigned Size = MRI.getType(MO.getReg()).getSizeInBits();
       if (MatcherOpcode == GIM_CheckMemorySizeEqualToLLT &&
           MMO->getSizeInBits() != Size) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       } else if (MatcherOpcode == GIM_CheckMemorySizeLessThanLLT &&
                  MMO->getSizeInBits() >= Size) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       } else if (MatcherOpcode == GIM_CheckMemorySizeGreaterThanLLT &&
                  MMO->getSizeInBits() <= Size)
         if (handleReject() == RejectAndGiveUp)
           return false;
 
       break;
     }
     case GIM_CheckType: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
       int64_t TypeID = MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_CheckType(MIs[" << InsnID
                              << "]->getOperand(" << OpIdx
                              << "), TypeID=" << TypeID << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
       if (!MO.isReg() ||
-          MRI.getType(MO.getReg()) != ISelInfo.TypeObjects[TypeID]) {
+          MRI.getType(MO.getReg()) != ExecInfo.TypeObjects[TypeID]) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       }
       break;
     }
     case GIM_CheckPointerToAny: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
       uint64_t SizeInBits = MatchTable[CurrentIdx++];
 
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_CheckPointerToAny(MIs["
                              << InsnID << "]->getOperand(" << OpIdx
                              << "), SizeInBits=" << SizeInBits << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
       const LLT Ty = MRI.getType(MO.getReg());
 
       // iPTR must be looked up in the target.
case GIM_CheckPointerToAny: {
 
       break;
     }
     case GIM_RecordNamedOperand: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
       uint64_t StoreIdx = MatchTable[CurrentIdx++];
 
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_RecordNamedOperand(MIs["
                              << InsnID << "]->getOperand(" << OpIdx
                              << "), StoreIdx=" << StoreIdx << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       assert(StoreIdx < State.RecordedOperands.size() && "Index out of range");
       State.RecordedOperands[StoreIdx] = &State.MIs[InsnID]->getOperand(OpIdx);
       break;
     }
     case GIM_CheckRegBankForClass: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
       int64_t RCEnum = MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_CheckRegBankForClass(MIs["
                              << InsnID << "]->getOperand(" << OpIdx
                              << "), RCEnum=" << RCEnum << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
       if (!MO.isReg() ||
           &RBI.getRegBankFromRegClass(*TRI.getRegClass(RCEnum),
                                       MRI.getType(MO.getReg())) !=
               RBI.getRegBank(MO.getReg(), MRI, TRI)) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       }
       break;
     }
 
     case GIM_CheckComplexPattern: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
       int64_t RendererID = MatchTable[CurrentIdx++];
       int64_t ComplexPredicateID = MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": State.Renderers[" << RendererID
                              << "] = GIM_CheckComplexPattern(MIs[" << InsnID
                              << "]->getOperand(" << OpIdx
                              << "), ComplexPredicateID=" << ComplexPredicateID
                              << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       // FIXME: Use std::invoke() when it's available.
       ComplexRendererFns Renderer =
-          (ISel.*ISelInfo.ComplexPredicates[ComplexPredicateID])(
+          (Exec.*ExecInfo.ComplexPredicates[ComplexPredicateID])(
               State.MIs[InsnID]->getOperand(OpIdx));
       if (Renderer)
         State.Renderers[RendererID] = *Renderer;
-      else
-        if (handleReject() == RejectAndGiveUp)
-          return false;
+      else if (handleReject() == RejectAndGiveUp)
       break;
     }
 
     case GIM_CheckConstantInt: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
       int64_t Value = MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_CheckConstantInt(MIs["
                              << InsnID << "]->getOperand(" << OpIdx
                              << "), Value=" << Value << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
       if (MO.isReg()) {
         // isOperandImmEqual() will sign-extend to 64-bits, so should we.
         LLT Ty = MRI.getType(MO.getReg());
         Value = SignExtend64(Value, Ty.getSizeInBits());
 
         if (!isOperandImmEqual(MO, Value, MRI)) {
           if (handleReject() == RejectAndGiveUp)
             return false;
         }
       } else if (handleReject() == RejectAndGiveUp)
         return false;
 
       break;
     }
 
     case GIM_CheckLiteralInt: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
       int64_t Value = MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_CheckLiteralInt(MIs["
                              << InsnID << "]->getOperand(" << OpIdx
                              << "), Value=" << Value << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
       if (MO.isImm() && MO.getImm() == Value)
         break;
 
       if (MO.isCImm() && MO.getCImm()->equalsInt(Value))
         break;
 
       if (handleReject() == RejectAndGiveUp)
         return false;
 
       break;
     }
 
     case GIM_CheckIntrinsicID: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
       int64_t Value = MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_CheckIntrinsicID(MIs["
                              << InsnID << "]->getOperand(" << OpIdx
                              << "), Value=" << Value << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
       if (!MO.isIntrinsicID() || MO.getIntrinsicID() != Value)
         if (handleReject() == RejectAndGiveUp)
           return false;
       break;
     }
     case GIM_CheckCmpPredicate: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
       int64_t Value = MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_CheckCmpPredicate(MIs["
                              << InsnID << "]->getOperand(" << OpIdx
                              << "), Value=" << Value << ")\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
       if (!MO.isPredicate() || MO.getPredicate() != Value)
         if (handleReject() == RejectAndGiveUp)
           return false;
       break;
     }
     case GIM_CheckIsMBB: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_CheckIsMBB(MIs[" << InsnID
                              << "]->getOperand(" << OpIdx << "))\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       if (!State.MIs[InsnID]->getOperand(OpIdx).isMBB()) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       }
       break;
     }
     case GIM_CheckIsImm: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_CheckIsImm(MIs[" << InsnID
                              << "]->getOperand(" << OpIdx << "))\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       if (!State.MIs[InsnID]->getOperand(OpIdx).isImm()) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       }
       break;
     }
     case GIM_CheckIsSafeToFold: {
       int64_t InsnID = MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_CheckIsSafeToFold(MIs["
                              << InsnID << "])\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       if (!isObviouslySafeToFold(*State.MIs[InsnID], *State.MIs[0])) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       }
       break;
     }
     case GIM_CheckIsSameOperand:
     case GIM_CheckIsSameOperandIgnoreCopies: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
       int64_t OtherInsnID = MatchTable[CurrentIdx++];
       int64_t OtherOpIdx = MatchTable[CurrentIdx++];
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_CheckIsSameOperand(MIs["
                              << InsnID << "][" << OpIdx << "], MIs["
                              << OtherInsnID << "][" << OtherOpIdx << "])\n");
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       assert(State.MIs[OtherInsnID] != nullptr && "Used insn before defined");
 
       MachineOperand &Op = State.MIs[InsnID]->getOperand(OpIdx);
       MachineOperand &OtherOp = State.MIs[OtherInsnID]->getOperand(OtherOpIdx);
case GIM_CheckIsSameOperandIgnoreCopies: {
 
       if (!Op.isIdenticalTo(OtherOp)) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       }
       break;
     }
     case GIM_Reject:
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIM_Reject\n");
       if (handleReject() == RejectAndGiveUp)
         return false;
       break;
-
     case GIR_MutateOpcode: {
       int64_t OldInsnID = MatchTable[CurrentIdx++];
       uint64_t NewInsnID = MatchTable[CurrentIdx++];
       int64_t NewOpcode = MatchTable[CurrentIdx++];
       if (NewInsnID >= OutMIs.size())
         OutMIs.resize(NewInsnID + 1);
 
       OutMIs[NewInsnID] = MachineInstrBuilder(*State.MIs[OldInsnID]->getMF(),
                                               State.MIs[OldInsnID]);
       OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode));
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIR_MutateOpcode(OutMIs["
                              << NewInsnID << "], MIs[" << OldInsnID << "], "
                              << NewOpcode << ")\n");
       break;
     }
 
     case GIR_BuildMI: {
       uint64_t NewInsnID = MatchTable[CurrentIdx++];
       int64_t Opcode = MatchTable[CurrentIdx++];
       if (NewInsnID >= OutMIs.size())
         OutMIs.resize(NewInsnID + 1);
 
       OutMIs[NewInsnID] = BuildMI(*State.MIs[0]->getParent(), State.MIs[0],
                                   MIMetadata(*State.MIs[0]), TII.get(Opcode));
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIR_BuildMI(OutMIs["
                              << NewInsnID << "], " << Opcode << ")\n");
       break;
     }
 
     case GIR_Copy: {
       int64_t NewInsnID = MatchTable[CurrentIdx++];
       int64_t OldInsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
       assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
       OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(OpIdx));
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs()
                           << CurrentIdx << ": GIR_Copy(OutMIs[" << NewInsnID
                           << "], MIs[" << OldInsnID << "], " << OpIdx << ")\n");
       break;
     }
 
     case GIR_CopyOrAddZeroReg: {
       int64_t NewInsnID = MatchTable[CurrentIdx++];
       int64_t OldInsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
       int64_t ZeroReg = MatchTable[CurrentIdx++];
       assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
       MachineOperand &MO = State.MIs[OldInsnID]->getOperand(OpIdx);
       if (isOperandImmEqual(MO, 0, MRI))
         OutMIs[NewInsnID].addReg(ZeroReg);
       else
         OutMIs[NewInsnID].add(MO);
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIR_CopyOrAddZeroReg(OutMIs["
                              << NewInsnID << "], MIs[" << OldInsnID << "], "
                              << OpIdx << ", " << ZeroReg << ")\n");
       break;
     }
 
     case GIR_CopySubReg: {
       int64_t NewInsnID = MatchTable[CurrentIdx++];
       int64_t OldInsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
       int64_t SubRegIdx = MatchTable[CurrentIdx++];
       assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
       OutMIs[NewInsnID].addReg(State.MIs[OldInsnID]->getOperand(OpIdx).getReg(),
                                0, SubRegIdx);
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIR_CopySubReg(OutMIs["
                              << NewInsnID << "], MIs[" << OldInsnID << "], "
                              << OpIdx << ", " << SubRegIdx << ")\n");
       break;
     }
 
     case GIR_AddImplicitDef: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t RegNum = MatchTable[CurrentIdx++];
       assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
       OutMIs[InsnID].addDef(RegNum, RegState::Implicit);
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIR_AddImplicitDef(OutMIs["
                              << InsnID << "], " << RegNum << ")\n");
       break;
     }
 
     case GIR_AddImplicitUse: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t RegNum = MatchTable[CurrentIdx++];
       assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
       OutMIs[InsnID].addUse(RegNum, RegState::Implicit);
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIR_AddImplicitUse(OutMIs["
                              << InsnID << "], " << RegNum << ")\n");
       break;
     }
 
     case GIR_AddRegister: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t RegNum = MatchTable[CurrentIdx++];
       uint64_t RegFlags = MatchTable[CurrentIdx++];
       assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
       OutMIs[InsnID].addReg(RegNum, RegFlags);
-      DEBUG_WITH_TYPE(
-        TgtInstructionSelector::getName(),
-        dbgs() << CurrentIdx << ": GIR_AddRegister(OutMIs["
-        << InsnID << "], " << RegNum << ", " << RegFlags << ")\n");
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
+                      dbgs()
+                          << CurrentIdx << ": GIR_AddRegister(OutMIs[" << InsnID
+                          << "], " << RegNum << ", " << RegFlags << ")\n");
       break;
     }
 
     case GIR_AddTempRegister:
     case GIR_AddTempSubRegister: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t TempRegID = MatchTable[CurrentIdx++];
       uint64_t TempRegFlags = MatchTable[CurrentIdx++];
       unsigned SubReg = 0;
       if (MatcherOpcode == GIR_AddTempSubRegister)
         SubReg = MatchTable[CurrentIdx++];
 
       assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
 
-      OutMIs[InsnID].addReg(State.TempRegisters[TempRegID], TempRegFlags, SubReg);
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
-                      dbgs() << CurrentIdx << ": GIR_AddTempRegister(OutMIs["
-                             << InsnID << "], TempRegisters[" << TempRegID
-                             << "]";
-                      if (SubReg)
-                        dbgs() << '.' << TRI.getSubRegIndexName(SubReg);
-                      dbgs() << ", " << TempRegFlags << ")\n");
+      OutMIs[InsnID].addReg(State.TempRegisters[TempRegID], TempRegFlags,
+                            SubReg);
+      DEBUG_WITH_TYPE(
+          TgtExecutor::getName(),
+          dbgs() << CurrentIdx << ": GIR_AddTempRegister(OutMIs[" << InsnID
+                 << "], TempRegisters[" << TempRegID << "]";
+          if (SubReg) dbgs() << '.' << TRI.getSubRegIndexName(SubReg);
       break;
     }
 
     case GIR_AddImm: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t Imm = MatchTable[CurrentIdx++];
       assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
       OutMIs[InsnID].addImm(Imm);
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIR_AddImm(OutMIs[" << InsnID
                              << "], " << Imm << ")\n");
       break;
     }
 
     case GIR_ComplexRenderer: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t RendererID = MatchTable[CurrentIdx++];
       assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
       for (const auto &RenderOpFn : State.Renderers[RendererID])
         RenderOpFn(OutMIs[InsnID]);
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIR_ComplexRenderer(OutMIs["
                              << InsnID << "], " << RendererID << ")\n");
       break;
     }
     case GIR_ComplexSubOperandRenderer: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t RendererID = MatchTable[CurrentIdx++];
       int64_t RenderOpID = MatchTable[CurrentIdx++];
       assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
       State.Renderers[RendererID][RenderOpID](OutMIs[InsnID]);
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx
                              << ": GIR_ComplexSubOperandRenderer(OutMIs["
                              << InsnID << "], " << RendererID << ", "
                              << RenderOpID << ")\n");
       break;
     }
     case GIR_ComplexSubOperandSubRegRenderer: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t RendererID = MatchTable[CurrentIdx++];
       int64_t RenderOpID = MatchTable[CurrentIdx++];
       int64_t SubRegIdx = MatchTable[CurrentIdx++];
       MachineInstrBuilder &MI = OutMIs[InsnID];
       assert(MI && "Attempted to add to undefined instruction");
       State.Renderers[RendererID][RenderOpID](MI);
       MI->getOperand(MI->getNumOperands() - 1).setSubReg(SubRegIdx);
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx
                              << ": GIR_ComplexSubOperandSubRegRenderer(OutMIs["
                              << InsnID << "], " << RendererID << ", "
                              << RenderOpID << ", " << SubRegIdx << ")\n");
       break;
     }
 
     case GIR_CopyConstantAsSImm: {
       int64_t NewInsnID = MatchTable[CurrentIdx++];
       int64_t OldInsnID = MatchTable[CurrentIdx++];
       assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
-      assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_CONSTANT && "Expected G_CONSTANT");
+      assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_CONSTANT &&
+             "Expected G_CONSTANT");
       if (State.MIs[OldInsnID]->getOperand(1).isCImm()) {
         OutMIs[NewInsnID].addImm(
             State.MIs[OldInsnID]->getOperand(1).getCImm()->getSExtValue());
       } else if (State.MIs[OldInsnID]->getOperand(1).isImm())
         OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(1));
       else
         llvm_unreachable("Expected Imm or CImm operand");
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIR_CopyConstantAsSImm(OutMIs["
                              << NewInsnID << "], MIs[" << OldInsnID << "])\n");
       break;
     }
 
     // TODO: Needs a test case once we have a pattern that uses this.
     case GIR_CopyFConstantAsFPImm: {
       int64_t NewInsnID = MatchTable[CurrentIdx++];
       int64_t OldInsnID = MatchTable[CurrentIdx++];
       assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction");
-      assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_FCONSTANT && "Expected G_FCONSTANT");
+      assert(State.MIs[OldInsnID]->getOpcode() == TargetOpcode::G_FCONSTANT &&
+             "Expected G_FCONSTANT");
       if (State.MIs[OldInsnID]->getOperand(1).isFPImm())
         OutMIs[NewInsnID].addFPImm(
             State.MIs[OldInsnID]->getOperand(1).getFPImm());
       else
         llvm_unreachable("Expected FPImm operand");
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
-                      dbgs() << CurrentIdx << ": GIR_CopyFPConstantAsFPImm(OutMIs["
-                             << NewInsnID << "], MIs[" << OldInsnID << "])\n");
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
+                      dbgs()
+                          << CurrentIdx << ": GIR_CopyFPConstantAsFPImm(OutMIs["
       break;
     }
 
     case GIR_CustomRenderer: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OldInsnID = MatchTable[CurrentIdx++];
       int64_t RendererFnID = MatchTable[CurrentIdx++];
       assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIR_CustomRenderer(OutMIs["
                              << InsnID << "], MIs[" << OldInsnID << "], "
                              << RendererFnID << ")\n");
-      (ISel.*ISelInfo.CustomRenderers[RendererFnID])(
+      (Exec.*ExecInfo.CustomRenderers[RendererFnID])(
           OutMIs[InsnID], *State.MIs[OldInsnID],
           -1); // Not a source operand of the old instruction.
       break;
     }
     case GIR_CustomOperandRenderer: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OldInsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
       int64_t RendererFnID = MatchTable[CurrentIdx++];
       assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
 
-      DEBUG_WITH_TYPE(
-        TgtInstructionSelector::getName(),
-        dbgs() << CurrentIdx << ": GIR_CustomOperandRenderer(OutMIs["
-               << InsnID << "], MIs[" << OldInsnID << "]->getOperand("
-               << OpIdx << "), "
-        << RendererFnID << ")\n");
-      (ISel.*ISelInfo.CustomRenderers[RendererFnID])(OutMIs[InsnID],
-                                                     *State.MIs[OldInsnID],
-                                                     OpIdx);
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
+                      dbgs() << CurrentIdx
+                             << ": GIR_CustomOperandRenderer(OutMIs[" << InsnID
+                             << "], MIs[" << OldInsnID << "]->getOperand("
+                             << OpIdx << "), " << RendererFnID << ")\n");
+      (Exec.*ExecInfo.CustomRenderers[RendererFnID])(
+          OutMIs[InsnID], *State.MIs[OldInsnID], OpIdx);
       break;
     }
     case GIR_ConstrainOperandRC: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t OpIdx = MatchTable[CurrentIdx++];
       int64_t RCEnum = MatchTable[CurrentIdx++];
       assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
       MachineInstr &I = *OutMIs[InsnID].getInstr();
       MachineFunction &MF = *I.getParent()->getParent();
       MachineRegisterInfo &MRI = MF.getRegInfo();
       const TargetRegisterClass &RC = *TRI.getRegClass(RCEnum);
       MachineOperand &MO = I.getOperand(OpIdx);
       constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, RC, MO);
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIR_ConstrainOperandRC(OutMIs["
                              << InsnID << "], " << OpIdx << ", " << RCEnum
                              << ")\n");
       break;
     }
 
     case GIR_ConstrainSelectedInstOperands: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
       constrainSelectedInstRegOperands(*OutMIs[InsnID].getInstr(), TII, TRI,
                                        RBI);
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx
                              << ": GIR_ConstrainSelectedInstOperands(OutMIs["
                              << InsnID << "])\n");
       break;
     }
 
     case GIR_MergeMemOperands: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       assert(OutMIs[InsnID] && "Attempted to add to undefined instruction");
 
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIR_MergeMemOperands(OutMIs["
                              << InsnID << "]");
       int64_t MergeInsnID = GIU_MergeMemOperands_EndOfList;
       while ((MergeInsnID = MatchTable[CurrentIdx++]) !=
              GIU_MergeMemOperands_EndOfList) {
-        DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+        DEBUG_WITH_TYPE(TgtExecutor::getName(),
                         dbgs() << ", MIs[" << MergeInsnID << "]");
         for (const auto &MMO : State.MIs[MergeInsnID]->memoperands())
           OutMIs[InsnID].addMemOperand(MMO);
       }
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(), dbgs() << ")\n");
+      DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << ")\n");
       break;
     }
 
     case GIR_EraseFromParent: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       assert(State.MIs[InsnID] &&
              "Attempted to erase an undefined instruction");
       State.MIs[InsnID]->eraseFromParent();
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIR_EraseFromParent(MIs["
                              << InsnID << "])\n");
       break;
     }
 
     case GIR_MakeTempReg: {
       int64_t TempRegID = MatchTable[CurrentIdx++];
       int64_t TypeID = MatchTable[CurrentIdx++];
 
       State.TempRegisters[TempRegID] =
-          MRI.createGenericVirtualRegister(ISelInfo.TypeObjects[TypeID]);
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+          MRI.createGenericVirtualRegister(ExecInfo.TypeObjects[TypeID]);
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": TempRegs[" << TempRegID
                              << "] = GIR_MakeTempReg(" << TypeID << ")\n");
       break;
     }
 
     case GIR_Coverage: {
       int64_t RuleID = MatchTable[CurrentIdx++];
-      CoverageInfo.setCovered(RuleID);
+      assert(CoverageInfo);
+      CoverageInfo->setCovered(RuleID);
 
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
-                      dbgs()
-                          << CurrentIdx << ": GIR_Coverage(" << RuleID << ")");
+      DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx
+                                                     << ": GIR_Coverage("
+                                                     << RuleID << ")");
       break;
     }
 
     case GIR_Done:
-      DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
+      DEBUG_WITH_TYPE(TgtExecutor::getName(),
                       dbgs() << CurrentIdx << ": GIR_Done\n");
       propagateFlags(OutMIs);
       return true;
-
     default:
       llvm_unreachable("Unexpected command");
     }
   }
 }
 
 } // end namespace llvm
 
-#endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTORIMPL_H
+#endif // LLVM_CODEGEN_GLOBALISEL_GIMATCHTABLEEXECUTORIMPL_H

llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h

 //===- llvm/CodeGen/GlobalISel/InstructionSelector.h ------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file This file declares the API for the instruction selector.
-/// This class is responsible for selecting machine instructions.
-/// It's implemented by the target. It's used by the InstructionSelect pass.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
 #define LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
 
-#include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/SmallVector.h"
-#include "llvm/CodeGen/GlobalISel/Utils.h"
-#include "llvm/CodeGen/LowLevelType.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/IR/Function.h"
-#include <bitset>
-#include <cstddef>
-#include <cstdint>
-#include <functional>
-#include <initializer_list>
-#include <optional>
-#include <vector>
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h"
 
 namespace llvm {
-
-class BlockFrequencyInfo;
-class CodeGenCoverage;
-class MachineBasicBlock;
-class ProfileSummaryInfo;
-class APInt;
-class APFloat;
-class GISelKnownBits;
-class MachineInstr;
-class MachineInstrBuilder;
-class MachineFunction;
-class MachineOperand;
-class MachineRegisterInfo;
-class RegisterBankInfo;
-class TargetInstrInfo;
-class TargetRegisterInfo;
-
-/// Container class for CodeGen predicate results.
-/// This is convenient because std::bitset does not have a constructor
-/// with an initializer list of set bits.
-///
-/// Each InstructionSelector subclass should define a PredicateBitset class
-/// with:
-///   const unsigned MAX_SUBTARGET_PREDICATES = 192;
-///   using PredicateBitset = PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
-/// and updating the constant to suit the target. Tablegen provides a suitable
-/// definition for the predicates in use in <Target>GenGlobalISel.inc when
-/// GET_GLOBALISEL_PREDICATE_BITSET is defined.
-template <std::size_t MaxPredicates>
-class PredicateBitsetImpl : public std::bitset<MaxPredicates> {
+class InstructionSelector : public GIMatchTableExecutor {
 public:
-  // Cannot inherit constructors because it's not supported by VC++..
-  PredicateBitsetImpl() = default;
-
-  PredicateBitsetImpl(const std::bitset<MaxPredicates> &B)
-      : std::bitset<MaxPredicates>(B) {}
-
-  PredicateBitsetImpl(std::initializer_list<unsigned> Init) {
-    for (auto I : Init)
-      std::bitset<MaxPredicates>::set(I);
-  }
-};
-
-enum {
-  /// Begin a try-block to attempt a match and jump to OnFail if it is
-  /// unsuccessful.
-  /// - OnFail - The MatchTable entry at which to resume if the match fails.
-  ///
-  /// FIXME: This ought to take an argument indicating the number of try-blocks
-  ///        to exit on failure. It's usually one but the last match attempt of
-  ///        a block will need more. The (implemented) alternative is to tack a
-  ///        GIM_Reject on the end of each try-block which is simpler but
-  ///        requires an extra opcode and iteration in the interpreter on each
-  ///        failed match.
-  GIM_Try,
-
-  /// Switch over the opcode on the specified instruction
-  /// - InsnID - Instruction ID
-  /// - LowerBound - numerically minimum opcode supported
-  /// - UpperBound - numerically maximum + 1 opcode supported
-  /// - Default - failure jump target
-  /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
-  GIM_SwitchOpcode,
-
-  /// Switch over the LLT on the specified instruction operand
-  /// - InsnID - Instruction ID
-  /// - OpIdx - Operand index
-  /// - LowerBound - numerically minimum Type ID supported
-  /// - UpperBound - numerically maximum + 1 Type ID supported
-  /// - Default - failure jump target
-  /// - JumpTable... - (UpperBound - LowerBound) (at least 2) jump targets
-  GIM_SwitchType,
-
-  /// Record the specified instruction.
-  /// The IgnoreCopies variant ignores COPY instructions.
-  /// - NewInsnID - Instruction ID to define
-  /// - InsnID - Instruction ID
-  /// - OpIdx - Operand index
-  GIM_RecordInsn,
-  GIM_RecordInsnIgnoreCopies,
-
-  /// Check the feature bits
-  /// - Expected features
-  GIM_CheckFeatures,
-
-  /// Check the opcode on the specified instruction
-  /// - InsnID - Instruction ID
-  /// - Expected opcode
-  GIM_CheckOpcode,
-
-  /// Check the opcode on the specified instruction, checking 2 acceptable
-  /// alternatives.
-  /// - InsnID - Instruction ID
-  /// - Expected opcode
-  /// - Alternative expected opcode
-  GIM_CheckOpcodeIsEither,
-
-  /// Check the instruction has the right number of operands
-  /// - InsnID - Instruction ID
-  /// - Expected number of operands
-  GIM_CheckNumOperands,
-  /// Check an immediate predicate on the specified instruction
-  /// - InsnID - Instruction ID
-  /// - The predicate to test
-  GIM_CheckI64ImmPredicate,
-  /// Check an immediate predicate on the specified instruction via an APInt.
-  /// - InsnID - Instruction ID
-  /// - The predicate to test
-  GIM_CheckAPIntImmPredicate,
-  /// Check a floating point immediate predicate on the specified instruction.
-  /// - InsnID - Instruction ID
-  /// - The predicate to test
-  GIM_CheckAPFloatImmPredicate,
-  /// Check an immediate predicate on the specified instruction
-  /// - InsnID - Instruction ID
-  /// - OpIdx - Operand index
-  /// - The predicate to test
-  GIM_CheckImmOperandPredicate,
-  /// Check a memory operation has the specified atomic ordering.
-  /// - InsnID - Instruction ID
-  /// - Ordering - The AtomicOrdering value
-  GIM_CheckAtomicOrdering,
-  GIM_CheckAtomicOrderingOrStrongerThan,
-  GIM_CheckAtomicOrderingWeakerThan,
-  /// Check the size of the memory access for the given machine memory operand.
-  /// - InsnID - Instruction ID
-  /// - MMOIdx - MMO index
-  /// - Size - The size in bytes of the memory access
-  GIM_CheckMemorySizeEqualTo,
-
-  /// Check the address space of the memory access for the given machine memory
-  /// operand.
-  /// - InsnID - Instruction ID
-  /// - MMOIdx - MMO index
-  /// - NumAddrSpace - Number of valid address spaces
-  /// - AddrSpaceN - An allowed space of the memory access
-  /// - AddrSpaceN+1 ...
-  GIM_CheckMemoryAddressSpace,
-
-  /// Check the minimum alignment of the memory access for the given machine
-  /// memory operand.
-  /// - InsnID - Instruction ID
-  /// - MMOIdx - MMO index
-  /// - MinAlign - Minimum acceptable alignment
-  GIM_CheckMemoryAlignment,
-
-  /// Check the size of the memory access for the given machine memory operand
-  /// against the size of an operand.
-  /// - InsnID - Instruction ID
-  /// - MMOIdx - MMO index
-  /// - OpIdx - The operand index to compare the MMO against
-  GIM_CheckMemorySizeEqualToLLT,
-  GIM_CheckMemorySizeLessThanLLT,
-  GIM_CheckMemorySizeGreaterThanLLT,
-
-  /// Check if this is a vector that can be treated as a vector splat
-  /// constant. This is valid for both G_BUILD_VECTOR as well as
-  /// G_BUILD_VECTOR_TRUNC. For AllOnes refers to individual bits, so a -1
-  /// element.
-  /// - InsnID - Instruction ID
-  GIM_CheckIsBuildVectorAllOnes,
-  GIM_CheckIsBuildVectorAllZeros,
-
-  /// Check a generic C++ instruction predicate
-  /// - InsnID - Instruction ID
-  /// - PredicateID - The ID of the predicate function to call
-  GIM_CheckCxxInsnPredicate,
-
-  /// Check if there's no use of the first result.
-  /// - InsnID - Instruction ID
-  GIM_CheckHasNoUse,
-
-  /// Check the type for the specified operand
-  /// - InsnID - Instruction ID
-  /// - OpIdx - Operand index
-  /// - Expected type
-  GIM_CheckType,
-  /// Check the type of a pointer to any address space.
-  /// - InsnID - Instruction ID
-  /// - OpIdx - Operand index
-  /// - SizeInBits - The size of the pointer value in bits.
-  GIM_CheckPointerToAny,
-  /// Check the register bank for the specified operand
-  /// - InsnID - Instruction ID
-  /// - OpIdx - Operand index
-  /// - Expected register bank (specified as a register class)
-  GIM_CheckRegBankForClass,
-
-  /// Check the operand matches a complex predicate
-  /// - InsnID - Instruction ID
-  /// - OpIdx - Operand index
-  /// - RendererID - The renderer to hold the result
-  /// - Complex predicate ID
-  GIM_CheckComplexPattern,
-
-  /// Check the operand is a specific integer
-  /// - InsnID - Instruction ID
-  /// - OpIdx - Operand index
-  /// - Expected integer
-  GIM_CheckConstantInt,
-  /// Check the operand is a specific literal integer (i.e. MO.isImm() or
-  /// MO.isCImm() is true).
-  /// - InsnID - Instruction ID
-  /// - OpIdx - Operand index
-  /// - Expected integer
-  GIM_CheckLiteralInt,
-  /// Check the operand is a specific intrinsic ID
-  /// - InsnID - Instruction ID
-  /// - OpIdx - Operand index
-  /// - Expected Intrinsic ID
-  GIM_CheckIntrinsicID,
-
-  /// Check the operand is a specific predicate
-  /// - InsnID - Instruction ID
-  /// - OpIdx - Operand index
-  /// - Expected predicate
-  GIM_CheckCmpPredicate,
-
-  /// Check the specified operand is an MBB
-  /// - InsnID - Instruction ID
-  /// - OpIdx - Operand index
-  GIM_CheckIsMBB,
-
-  /// Check the specified operand is an Imm
-  /// - InsnID - Instruction ID
-  /// - OpIdx - Operand index
-  GIM_CheckIsImm,
-
-  /// Check if the specified operand is safe to fold into the current
-  /// instruction.
-  /// - InsnID - Instruction ID
-  GIM_CheckIsSafeToFold,
-
-  /// Check the specified operands are identical.
-  /// The IgnoreCopies variant looks through COPY instructions before
-  /// comparing the operands.
-  /// - InsnID - Instruction ID
-  /// - OpIdx - Operand index
-  /// - OtherInsnID - Other instruction ID
-  /// - OtherOpIdx - Other operand index
-  GIM_CheckIsSameOperand,
-  GIM_CheckIsSameOperandIgnoreCopies,
-
-  /// Predicates with 'let PredicateCodeUsesOperands = 1' need to examine some
-  /// named operands that will be recorded in RecordedOperands. Names of these
-  /// operands are referenced in predicate argument list. Emitter determines
-  /// StoreIdx(corresponds to the order in which names appear in argument list).
-  /// - InsnID - Instruction ID
-  /// - OpIdx - Operand index
-  /// - StoreIdx - Store location in RecordedOperands.
-  GIM_RecordNamedOperand,
-
-  /// Fail the current try-block, or completely fail to match if there is no
-  /// current try-block.
-  GIM_Reject,
-
-  //=== Renderers ===
-
-  /// Mutate an instruction
-  /// - NewInsnID - Instruction ID to define
-  /// - OldInsnID - Instruction ID to mutate
-  /// - NewOpcode - The new opcode to use
-  GIR_MutateOpcode,
-
-  /// Build a new instruction
-  /// - InsnID - Instruction ID to define
-  /// - Opcode - The new opcode to use
-  GIR_BuildMI,
-
-  /// Copy an operand to the specified instruction
-  /// - NewInsnID - Instruction ID to modify
-  /// - OldInsnID - Instruction ID to copy from
-  /// - OpIdx - The operand to copy
-  GIR_Copy,
-
-  /// Copy an operand to the specified instruction or add a zero register if the
-  /// operand is a zero immediate.
-  /// - NewInsnID - Instruction ID to modify
-  /// - OldInsnID - Instruction ID to copy from
-  /// - OpIdx - The operand to copy
-  /// - ZeroReg - The zero register to use
-  GIR_CopyOrAddZeroReg,
-  /// Copy an operand to the specified instruction
-  /// - NewInsnID - Instruction ID to modify
-  /// - OldInsnID - Instruction ID to copy from
-  /// - OpIdx - The operand to copy
-  /// - SubRegIdx - The subregister to copy
-  GIR_CopySubReg,
-
-  /// Add an implicit register def to the specified instruction
-  /// - InsnID - Instruction ID to modify
-  /// - RegNum - The register to add
-  GIR_AddImplicitDef,
-  /// Add an implicit register use to the specified instruction
-  /// - InsnID - Instruction ID to modify
-  /// - RegNum - The register to add
-  GIR_AddImplicitUse,
-  /// Add an register to the specified instruction
-  /// - InsnID - Instruction ID to modify
-  /// - RegNum - The register to add
-  GIR_AddRegister,
-
-  /// Add a temporary register to the specified instruction
-  /// - InsnID - Instruction ID to modify
-  /// - TempRegID - The temporary register ID to add
-  /// - TempRegFlags - The register flags to set
-  GIR_AddTempRegister,
-
-  /// Add a temporary register to the specified instruction
-  /// - InsnID - Instruction ID to modify
-  /// - TempRegID - The temporary register ID to add
-  /// - TempRegFlags - The register flags to set
-  /// - SubRegIndex - The subregister index to set
-  GIR_AddTempSubRegister,
-
-  /// Add an immediate to the specified instruction
-  /// - InsnID - Instruction ID to modify
-  /// - Imm - The immediate to add
-  GIR_AddImm,
-
-  /// Render complex operands to the specified instruction
-  /// - InsnID - Instruction ID to modify
-  /// - RendererID - The renderer to call
-  GIR_ComplexRenderer,
-  /// Render sub-operands of complex operands to the specified instruction
-  /// - InsnID - Instruction ID to modify
-  /// - RendererID - The renderer to call
-  /// - RenderOpID - The suboperand to render.
-  GIR_ComplexSubOperandRenderer,
-  /// Render subregisters of suboperands of complex operands to the
-  /// specified instruction
-  /// - InsnID - Instruction ID to modify
-  /// - RendererID - The renderer to call
-  /// - RenderOpID - The suboperand to render
-  /// - SubRegIdx - The subregister to extract
-  GIR_ComplexSubOperandSubRegRenderer,
-
-  /// Render operands to the specified instruction using a custom function
-  /// - InsnID - Instruction ID to modify
-  /// - OldInsnID - Instruction ID to get the matched operand from
-  /// - RendererFnID - Custom renderer function to call
-  GIR_CustomRenderer,
-
-  /// Render operands to the specified instruction using a custom function,
-  /// reading from a specific operand.
-  /// - InsnID - Instruction ID to modify
-  /// - OldInsnID - Instruction ID to get the matched operand from
-  /// - OpIdx - Operand index in OldInsnID the render function should read
-  /// from..
-  /// - RendererFnID - Custom renderer function to call
-  GIR_CustomOperandRenderer,
-
-  /// Render a G_CONSTANT operator as a sign-extended immediate.
-  /// - NewInsnID - Instruction ID to modify
-  /// - OldInsnID - Instruction ID to copy from
-  /// The operand index is implicitly 1.
-  GIR_CopyConstantAsSImm,
-
-  /// Render a G_FCONSTANT operator as a sign-extended immediate.
-  /// - NewInsnID - Instruction ID to modify
-  /// - OldInsnID - Instruction ID to copy from
-  /// The operand index is implicitly 1.
-  GIR_CopyFConstantAsFPImm,
-
-  /// Constrain an instruction operand to a register class.
-  /// - InsnID - Instruction ID to modify
-  /// - OpIdx - Operand index
-  /// - RCEnum - Register class enumeration value
-  GIR_ConstrainOperandRC,
-
-  /// Constrain an instructions operands according to the instruction
-  /// description.
-  /// - InsnID - Instruction ID to modify
-  GIR_ConstrainSelectedInstOperands,
-
-  /// Merge all memory operands into instruction.
-  /// - InsnID - Instruction ID to modify
-  /// - MergeInsnID... - One or more Instruction ID to merge into the result.
-  /// - GIU_MergeMemOperands_EndOfList - Terminates the list of instructions to
-  ///                                    merge.
-  GIR_MergeMemOperands,
-
-  /// Erase from parent.
-  /// - InsnID - Instruction ID to erase
-  GIR_EraseFromParent,
-
-  /// Create a new temporary register that's not constrained.
-  /// - TempRegID - The temporary register ID to initialize.
-  /// - Expected type
-  GIR_MakeTempReg,
-
-  /// A successful emission
-  GIR_Done,
-
-  /// Increment the rule coverage counter.
-  /// - RuleID - The ID of the rule that was covered.
-  GIR_Coverage,
-
-  /// Keeping track of the number of the GI opcodes. Must be the last entry.
-  GIU_NumOpcodes,
-};
-
-enum {
-  /// Indicates the end of the variable-length MergeInsnID list in a
-  /// GIR_MergeMemOperands opcode.
-  GIU_MergeMemOperands_EndOfList = -1,
-};
-
-/// Provides the logic to select generic machine instructions.
-class InstructionSelector {
-public:
-  virtual ~InstructionSelector() = default;
+  virtual ~InstructionSelector();
 
   /// Select the (possibly generic) instruction \p I to only use target-specific
   /// opcodes. It is OK to insert multiple instructions, but they cannot be
   /// generic pre-isel instructions.
   ///
   /// \returns whether selection succeeded.
   /// \pre  I.getParent() && I.getParent()->getParent()
   /// \post
   ///   if returns true:
   ///     for I in all mutated/inserted instructions:
   ///       !isPreISelGenericOpcode(I.getOpcode())
   virtual bool select(MachineInstr &I) = 0;
-
-  CodeGenCoverage *CoverageInfo = nullptr;
-  GISelKnownBits *KnownBits = nullptr;
-  MachineFunction *MF = nullptr;
-  ProfileSummaryInfo *PSI = nullptr;
-  BlockFrequencyInfo *BFI = nullptr;
-  // For some predicates, we need to track the current MBB.
-  MachineBasicBlock *CurMBB = nullptr;
-
-  virtual void setupGeneratedPerFunctionState(MachineFunction &MF) {
-    llvm_unreachable("TableGen should have emitted implementation");
-  }
-
-  /// Setup per-MF selector state.
-  virtual void setupMF(MachineFunction &mf, GISelKnownBits *KB,
-                       CodeGenCoverage &covinfo, ProfileSummaryInfo *psi,
-                       BlockFrequencyInfo *bfi) {
-    CoverageInfo = &covinfo;
-    KnownBits = KB;
-    MF = &mf;
-    PSI = psi;
-    BFI = bfi;
-    CurMBB = nullptr;
-    setupGeneratedPerFunctionState(mf);
-  }
-
-protected:
-  using ComplexRendererFns =
-      std::optional<SmallVector<std::function<void(MachineInstrBuilder &)>, 4>>;
-  using RecordedMIVector = SmallVector<MachineInstr *, 4>;
-  using NewMIVector = SmallVector<MachineInstrBuilder, 4>;
-
-  struct MatcherState {
-    std::vector<ComplexRendererFns::value_type> Renderers;
-    RecordedMIVector MIs;
-    DenseMap<unsigned, unsigned> TempRegisters;
-    /// Named operands that predicate with 'let PredicateCodeUsesOperands = 1'
-    /// referenced in its argument list. Operands are inserted at index set by
-    /// emitter, it corresponds to the order in which names appear in argument
-    /// list. Currently such predicates don't have more then 3 arguments.
-    std::array<const MachineOperand *, 3> RecordedOperands;
-
-    MatcherState(unsigned MaxRenderers);
-  };
-
-  bool shouldOptForSize(const MachineFunction *MF) const {
-    const auto &F = MF->getFunction();
-    return F.hasOptSize() || F.hasMinSize() ||
-           (PSI && BFI && CurMBB && llvm::shouldOptForSize(*CurMBB, PSI, BFI));
-  }
-
-public:
-  template <class PredicateBitset, class ComplexMatcherMemFn,
-            class CustomRendererFn>
-  struct ISelInfoTy {
-    ISelInfoTy(const LLT *TypeObjects, size_t NumTypeObjects,
-               const PredicateBitset *FeatureBitsets,
-               const ComplexMatcherMemFn *ComplexPredicates,
-               const CustomRendererFn *CustomRenderers)
-        : TypeObjects(TypeObjects),
-          FeatureBitsets(FeatureBitsets),
-          ComplexPredicates(ComplexPredicates),
-          CustomRenderers(CustomRenderers) {
-
-      for (size_t I = 0; I < NumTypeObjects; ++I)
-        TypeIDMap[TypeObjects[I]] = I;
-    }
-    const LLT *TypeObjects;
-    const PredicateBitset *FeatureBitsets;
-    const ComplexMatcherMemFn *ComplexPredicates;
-    const CustomRendererFn *CustomRenderers;
-
-    SmallDenseMap<LLT, unsigned, 64> TypeIDMap;
-  };
+} // namespace llvm
 
-protected:
-  InstructionSelector();
-
-  /// Execute a given matcher table and return true if the match was successful
-  /// and false otherwise.
-  template <class TgtInstructionSelector, class PredicateBitset,
-            class ComplexMatcherMemFn, class CustomRendererFn>
-  bool executeMatchTable(
-      TgtInstructionSelector &ISel, NewMIVector &OutMIs, MatcherState &State,
-      const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn>
-          &ISelInfo,
-      const int64_t *MatchTable, const TargetInstrInfo &TII,
-      MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
-      const RegisterBankInfo &RBI, const PredicateBitset &AvailableFeatures,
-      CodeGenCoverage &CoverageInfo) const;
-
-  virtual const int64_t *getMatchTable() const {
-    llvm_unreachable("Should have been overridden by tablegen if used");
-  }
-
-  virtual bool testImmPredicate_I64(unsigned, int64_t) const {
-    llvm_unreachable(
-        "Subclasses must override this with a tablegen-erated function");
-  }
-  virtual bool testImmPredicate_APInt(unsigned, const APInt &) const {
-    llvm_unreachable(
-        "Subclasses must override this with a tablegen-erated function");
-  }
-  virtual bool testImmPredicate_APFloat(unsigned, const APFloat &) const {
-    llvm_unreachable(
-        "Subclasses must override this with a tablegen-erated function");
-  }
-  virtual bool testMIPredicate_MI(
-      unsigned, const MachineInstr &,
-      const std::array<const MachineOperand *, 3> &Operands) const {
-    llvm_unreachable(
-        "Subclasses must override this with a tablegen-erated function");
-  }
-
-  bool isOperandImmEqual(const MachineOperand &MO, int64_t Value,
-                         const MachineRegisterInfo &MRI) const;
-
-  /// Return true if the specified operand is a G_PTR_ADD with a G_CONSTANT on the
-  /// right-hand side. GlobalISel's separation of pointer and integer types
-  /// means that we don't need to worry about G_OR with equivalent semantics.
-  bool isBaseWithConstantOffset(const MachineOperand &Root,
-                                const MachineRegisterInfo &MRI) const;
-
-  /// Return true if MI can obviously be folded into IntoMI.
-  /// MI and IntoMI do not need to be in the same basic blocks, but MI must
-  /// preceed IntoMI.
-  bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const;
-};
-
-} // end namespace llvm
-
-#endif // LLVM_CODEGEN_GLOBALISEL_INSTRUCTIONSELECTOR_H
+#endif

llvm/lib/CodeGen/GlobalISel/CMakeLists.txt

 add_llvm_component_library(LLVMGlobalISel
   CSEInfo.cpp
   GISelKnownBits.cpp
   CSEMIRBuilder.cpp
   CallLowering.cpp
   GlobalISel.cpp
   Combiner.cpp
   CombinerHelper.cpp
+  GIMatchTableExecutor.cpp
   GISelChangeObserver.cpp
   IRTranslator.cpp
   InlineAsmLowering.cpp
   InstructionSelect.cpp
   InstructionSelector.cpp
   LegalityPredicates.cpp
   LegalizeMutations.cpp
   Legalizer.cpp

llvm/lib/CodeGen/GlobalISel/GIMatchTableExecutor.cpp

-//===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp --------------------===//
+//===- llvm/CodeGen/GlobalISel/GIMatchTableExecutor.cpp -------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file
-/// This file implements the InstructionSelector class.
+/// This file implements the GIMatchTableExecutor class.
 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h"
 #include "llvm/CodeGen/GlobalISel/Utils.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 
-#define DEBUG_TYPE "instructionselector"
+#define DEBUG_TYPE "gi-match-table-executor"
 
 using namespace llvm;
 
-InstructionSelector::MatcherState::MatcherState(unsigned MaxRenderers)
+GIMatchTableExecutor::MatcherState::MatcherState(unsigned MaxRenderers)
     : Renderers(MaxRenderers) {}
 
-InstructionSelector::InstructionSelector() = default;
+GIMatchTableExecutor::GIMatchTableExecutor() = default;
 
-bool InstructionSelector::isOperandImmEqual(
+bool GIMatchTableExecutor::isOperandImmEqual(
     const MachineOperand &MO, int64_t Value,
     const MachineRegisterInfo &MRI) const {
   if (MO.isReg() && MO.getReg())
     if (auto VRegVal = getIConstantVRegValWithLookThrough(MO.getReg(), MRI))
       return VRegVal->Value.getSExtValue() == Value;
   return false;
 }
 
-bool InstructionSelector::isBaseWithConstantOffset(
+bool GIMatchTableExecutor::isBaseWithConstantOffset(
     const MachineOperand &Root, const MachineRegisterInfo &MRI) const {
   if (!Root.isReg())
     return false;
 
   MachineInstr *RootI = MRI.getVRegDef(Root.getReg());
   if (RootI->getOpcode() != TargetOpcode::G_PTR_ADD)
     return false;
 
   MachineOperand &RHS = RootI->getOperand(2);
   MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg());
   if (RHSI->getOpcode() != TargetOpcode::G_CONSTANT)
     return false;
 
   return true;
 }
 
-bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI,
+bool GIMatchTableExecutor::isObviouslySafeToFold(MachineInstr &MI,
                                                  MachineInstr &IntoMI) const {
   // Immediate neighbours are already folded.
   if (MI.getParent() == IntoMI.getParent() &&
       std::next(MI.getIterator()) == IntoMI.getIterator())
     return true;
 
   // Convergent instructions cannot be moved in the CFG.
   if (MI.isConvergent() && MI.getParent() != IntoMI.getParent())
     return false;
 
   return !MI.mayLoadOrStore() && !MI.mayRaiseFPException() &&
          !MI.hasUnmodeledSideEffects() && MI.implicit_operands().empty();
 }

llvm/lib/CodeGen/GlobalISel/InstructionSelector.cpp

 //===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
-//
-/// \file
-/// This file implements the InstructionSelector class.
-//
-//===----------------------------------------------------------------------===//
 
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
-#include "llvm/CodeGen/GlobalISel/Utils.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineOperand.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-
-#define DEBUG_TYPE "instructionselector"
-
-using namespace llvm;
-
-InstructionSelector::MatcherState::MatcherState(unsigned MaxRenderers)
-    : Renderers(MaxRenderers) {}
-
-InstructionSelector::InstructionSelector() = default;
-
-bool InstructionSelector::isOperandImmEqual(
-    const MachineOperand &MO, int64_t Value,
-    const MachineRegisterInfo &MRI) const {
-  if (MO.isReg() && MO.getReg())
-    if (auto VRegVal = getIConstantVRegValWithLookThrough(MO.getReg(), MRI))
-      return VRegVal->Value.getSExtValue() == Value;
-  return false;
-}
-
-bool InstructionSelector::isBaseWithConstantOffset(
-    const MachineOperand &Root, const MachineRegisterInfo &MRI) const {
-  if (!Root.isReg())
-    return false;
-
-  MachineInstr *RootI = MRI.getVRegDef(Root.getReg());
-  if (RootI->getOpcode() != TargetOpcode::G_PTR_ADD)
-    return false;
-
-  MachineOperand &RHS = RootI->getOperand(2);
-  MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg());
-  if (RHSI->getOpcode() != TargetOpcode::G_CONSTANT)
-    return false;
-
-  return true;
-}
 
-bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI,
-                                                MachineInstr &IntoMI) const {
-  // Immediate neighbours are already folded.
-  if (MI.getParent() == IntoMI.getParent() &&
-      std::next(MI.getIterator()) == IntoMI.getIterator())
-    return true;
+namespace llvm {
 
-  // Convergent instructions cannot be moved in the CFG.
-  if (MI.isConvergent() && MI.getParent() != IntoMI.getParent())
-    return false;
+// vtable anchor
+InstructionSelector::~InstructionSelector() = default;
 
-  return !MI.mayLoadOrStore() && !MI.mayRaiseFPException() &&
-         !MI.hasUnmodeledSideEffects() && MI.implicit_operands().empty();
-}
+} // namespace llvm

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

 #include "AArch64MachineFunctionInfo.h"
 #include "AArch64RegisterBankInfo.h"
 #include "AArch64RegisterInfo.h"
 #include "AArch64Subtarget.h"
 #include "AArch64TargetMachine.h"
 #include "MCTargetDesc/AArch64AddressingModes.h"
 #include "MCTargetDesc/AArch64MCTargetDesc.h"
 #include "llvm/BinaryFormat/Dwarf.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
 #include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
-#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/CodeGen/GlobalISel/Utils.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

 #include "AMDGPUInstructionSelector.h"
 #include "AMDGPU.h"
 #include "AMDGPUGlobalISelUtils.h"
 #include "AMDGPUInstrInfo.h"
 #include "AMDGPURegisterBankInfo.h"
 #include "AMDGPUTargetMachine.h"
 #include "SIMachineFunctionInfo.h"
 #include "Utils/AMDGPUBaseInfo.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
-#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/IR/IntrinsicsAMDGPU.h"
 #include <optional>
 
 #define DEBUG_TYPE "amdgpu-isel"

llvm/lib/Target/ARM/ARMInstructionSelector.cpp

 //===- ARMInstructionSelector.cpp ----------------------------*- C++ -*-==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 /// \file
 /// This file implements the targeting of the InstructionSelector class for ARM.
 /// \todo This should be generated by TableGen.
 //===----------------------------------------------------------------------===//
 
 #include "ARMRegisterBankInfo.h"
 #include "ARMSubtarget.h"
 #include "ARMTargetMachine.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
-#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/IR/IntrinsicsARM.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "arm-isel"
 
 using namespace llvm;

llvm/lib/Target/M68k/GISel/M68kInstructionSelector.cpp

 //===-- M68kInstructionSelector.cpp -----------------------------*- C++ -*-===//
 //===----------------------------------------------------------------------===//
 /// \file
 /// This file implements the targeting of the InstructionSelector class for
 /// M68k.
 /// \todo This should be generated by TableGen.
 //===----------------------------------------------------------------------===//
 
 #include "M68kRegisterBankInfo.h"
 #include "M68kSubtarget.h"
 #include "M68kTargetMachine.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
-#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "m68k-isel"
 
 using namespace llvm;
 
 #define GET_GLOBALISEL_PREDICATE_BITSET
 #include "M68kGenGlobalISel.inc"

llvm/lib/Target/Mips/MipsInstructionSelector.cpp

 /// Mips.
 /// \todo This should be generated by TableGen.
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/MipsInstPrinter.h"
 #include "MipsMachineFunction.h"
 #include "MipsRegisterBankInfo.h"
 #include "MipsTargetMachine.h"
-#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
 #include "llvm/IR/IntrinsicsMips.h"
 
 #define DEBUG_TYPE "mips-isel"
 
 using namespace llvm;
 

llvm/lib/Target/PowerPC/GISel/PPCInstructionSelector.cpp

 //===----------------------------------------------------------------------===//
 
 #include "PPC.h"
 #include "PPCInstrInfo.h"
 #include "PPCMachineFunctionInfo.h"
 #include "PPCRegisterBankInfo.h"
 #include "PPCSubtarget.h"
 #include "PPCTargetMachine.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
 #include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
-#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/IR/IntrinsicsPowerPC.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "ppc-gisel"
 

llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

 //===-- RISCVInstructionSelector.cpp -----------------------------*- C++ -*-==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 /// \file
 /// This file implements the targeting of the InstructionSelector class for
 /// RISC-V.
 /// \todo This should be generated by TableGen.
 //===----------------------------------------------------------------------===//
 
 #include "RISCVRegisterBankInfo.h"
 #include "RISCVSubtarget.h"
 #include "RISCVTargetMachine.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
-#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
 #include "llvm/IR/IntrinsicsRISCV.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "riscv-isel"
 
 using namespace llvm;
 
 #define GET_GLOBALISEL_PREDICATE_BITSET

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

 #include "SPIRV.h"
 #include "SPIRVGlobalRegistry.h"
 #include "SPIRVInstrInfo.h"
 #include "SPIRVRegisterBankInfo.h"
 #include "SPIRVRegisterInfo.h"
 #include "SPIRVTargetMachine.h"
 #include "SPIRVUtils.h"
 #include "llvm/ADT/APFloat.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
-#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/IR/IntrinsicsSPIRV.h"
 #include "llvm/Support/Debug.h"
 
 #define DEBUG_TYPE "spirv-isel"
 
 using namespace llvm;

llvm/lib/Target/X86/X86InstructionSelector.cpp

 #include "MCTargetDesc/X86BaseInfo.h"
 #include "X86.h"
 #include "X86InstrBuilder.h"
 #include "X86InstrInfo.h"
 #include "X86RegisterBankInfo.h"
 #include "X86RegisterInfo.h"
 #include "X86Subtarget.h"
 #include "X86TargetMachine.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
-#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
 #include "llvm/CodeGen/GlobalISel/Utils.h"
 #include "llvm/CodeGen/LowLevelType.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineMemOperand.h"

llvm/test/TableGen/ContextlessPredicates.td

 // RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=false %s -o %T/context-non-optimized.cpp
 // RUN: FileCheck %s --check-prefixes=CHECK_NOPT -input-file=%T/context-non-optimized.cpp
 // RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common -optimize-match-table=true  %s -o %T/context-optimized.cpp
 // RUN: FileCheck %s --check-prefixes=CHECK_OPT -input-file=%T/context-optimized.cpp
 
 
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 def test_atomic_op_frag : PatFrag<(ops node:$ptr, node:$val),
                                                (atomic_swap node:$ptr, node:$val)> {
   let GISelPredicateCode = [{ return !MRI.use_nodbg_empty(MI.getOperand(0).getReg()); }];
   let IsAtomic = 1;
   let MemoryVT = i32;
 }
- 
 def INSN : I<(outs GPR32:$dst), (ins GPR32Op:$src1, GPR32Op:$src2), []>;
 
 def : Pat<(test_atomic_op_frag GPR32:$ptr, GPR32:$val) ,
         (INSN GPR32:$ptr, GPR32:$val)>;
 
 // CHECK_NOPT-LABEL: const int64_t *MyTargetInstructionSelector::getMatchTable() const {
 // CHECK_NOPT-NEXT:  constexpr static int64_t MatchTable0[] = {
 // CHECK_NOPT-NEXT:    GIM_Try, /*On fail goto*//*Label 0*/ 46, // Rule ID 0 //
 // CHECK_NOPT-NEXT:      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // CHECK_NOPT-NEXT:      GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ATOMICRMW_XCHG,
 // CHECK_NOPT-NEXT:      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
 // CHECK_NOPT-NEXT:      // MIs[0] dst
 // CHECK_NOPT-NEXT:      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // CHECK_NOPT-NEXT:      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // CHECK_NOPT-NEXT:      // MIs[0] ptr
 // CHECK_NOPT-NEXT:      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
 // CHECK_NOPT-NEXT:      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 // CHECK_NOPT-NEXT:      // MIs[0] val
 // CHECK_NOPT-NEXT:      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 // CHECK_NOPT-NEXT:      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
-// CHECK_NOPT-NEXT:      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_test_atomic_op_frag,
+// CHECK_NOPT-NEXT:      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_test_atomic_op_frag,
 // CHECK_NOPT-NEXT:      // (atomic_swap:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)<<P:Predicate_test_atomic_op_frag>>  =>  (INSN:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)
 // CHECK_NOPT-NEXT:      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::INSN,
 // CHECK_NOPT-NEXT:      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 // CHECK_NOPT-NEXT:      // GIR_Coverage, 0,
 // CHECK_NOPT-NEXT:      GIR_Done,
 // CHECK_NOPT-NEXT:    // Label 0: @46
 // CHECK_NOPT-NEXT:    GIM_Reject,
 // CHECK_NOPT-NEXT:    };

 // CHECK_OPT-NEXT:      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // CHECK_OPT-NEXT:      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 // CHECK_OPT-NEXT:      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/4,
 // CHECK_OPT-NEXT:      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // CHECK_OPT-NEXT:      // MIs[0] ptr
 // CHECK_OPT-NEXT:      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
 // CHECK_OPT-NEXT:      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 // CHECK_OPT-NEXT:      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
-// CHECK_OPT-NEXT:      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_test_atomic_op_frag,
+// CHECK_OPT-NEXT:      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_test_atomic_op_frag,
 // CHECK_OPT-NEXT:      // (atomic_swap:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)<<P:Predicate_test_atomic_op_frag>>  =>  (INSN:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)
 // CHECK_OPT-NEXT:      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/MyTarget::INSN,
 // CHECK_OPT-NEXT:      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 // CHECK_OPT-NEXT:      // GIR_Coverage, 0,
 // CHECK_OPT-NEXT:      GIR_Done,
 // CHECK_OPT-NEXT:    // Label 0: @43
 // CHECK_OPT-NEXT:    GIM_Reject,
 // CHECK_OPT-NEXT:    };
 // CHECK_OPT-NEXT:  return MatchTable0;
 // CHECK_OPT-NEXT: }

llvm/test/TableGen/GlobalISelEmitter-PR39045.td

 // RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common  %s -o %t
 // RUN: FileCheck %s < %t
 
 // Both predicates should be tested
-// CHECK-DAG: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_pat_frag_b,
-// CHECK-DAG: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_pat_frag_a,
+// CHECK-DAG: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_pat_frag_b,
+// CHECK-DAG: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_pat_frag_a,
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 
 def pat_frag_a : PatFrag <(ops node:$ptr), (load node:$ptr), [{}]> {
    let PredicateCode = [{ return isInstA(MI); }];
    let GISelPredicateCode = [{ return isInstA(MI); }];
def : Pat <
   (pat_frag_a GPR32:$src),
   (inst_a GPR32:$src)
 >;
 
 def : Pat <
   (pat_frag_b GPR32:$src),
   (inst_b GPR32:$src)
 >;
-

llvm/test/TableGen/GlobalISelEmitter.td

 
 // CHECK: const unsigned MAX_SUBTARGET_PREDICATES = 3;
 // CHECK: using PredicateBitset = llvm::PredicateBitsetImpl<MAX_SUBTARGET_PREDICATES>;
 
 // CHECK-LABEL: #ifdef GET_GLOBALISEL_TEMPORARIES_DECL
 // CHECK-NEXT:    mutable MatcherState State;
 // CHECK-NEXT:    typedef ComplexRendererFns(MyTargetInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
 // CHECK-NEXT:    typedef void(MyTargetInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
-// CHECK-NEXT:    const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ISelInfo;
+// CHECK-NEXT:    const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
 // CHECK-NEXT:    static MyTargetInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
 // CHECK-NEXT:    static MyTargetInstructionSelector::CustomRendererFn CustomRenderers[];
 // CHECK-NEXT:    bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
 // CHECK-NEXT:    bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
 // CHECK-NEXT:    bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
 // CHECK-NEXT:    const int64_t *getMatchTable() const override;
-// CHECK-NEXT:    bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const std::array<const MachineOperand *, 3> &Operands) const override;
+// CHECK-NEXT:    bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
 // CHECK-NEXT:  #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
 
 // CHECK-LABEL: #ifdef GET_GLOBALISEL_TEMPORARIES_INIT
 // CHECK-NEXT:    , State(3),
-// CHECK-NEXT:    ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
+// CHECK-NEXT:    ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
 // CHECK-NEXT:  #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
 
 // CHECK-LABEL: enum SubtargetFeatureBits : uint8_t {
 // CHECK-NEXT:    Feature_HasABit = 0,
 // CHECK-NEXT:    Feature_HasBBit = 1,
 // CHECK-NEXT:    Feature_HasCBit = 2,
 // CHECK-NEXT:  };
 

 // CHECK-NEXT:  enum {
 // CHECK-NEXT:    GICP_Invalid,
 // CHECK-NEXT:    GICP_gi_complex,
 // CHECK-NEXT:    GICP_gi_complex_rr,
 // CHECK-NEXT:  };
 
 // CHECK-LABEL: // PatFrag predicates.
 // CHECK-NEXT:  enum {
-// CHECK-NEXT:    GIPFP_I64_Predicate_cimm8 = GIPFP_I64_Invalid + 1,
-// CHECK-NEXT:    GIPFP_I64_Predicate_simm8,
+// CHECK-NEXT:    GICXXPred_I64_Predicate_cimm8 = GICXXPred_I64_Invalid + 1,
+// CHECK-NEXT:    GICXXPred_I64_Predicate_simm8,
 // CHECK-NEXT:  };
 
 
 // CHECK-NEXT: bool MyTargetInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
 // CHECK-NEXT:   switch (PredicateID) {
-// CHECK-NEXT:   case GIPFP_I64_Predicate_cimm8: {
+// CHECK-NEXT:   case GICXXPred_I64_Predicate_cimm8: {
 // CHECK-NEXT:     return isInt<8>(Imm);
 // CHECK-NEXT:     llvm_unreachable("ImmediateCode should have returned");
 // CHECK-NEXT:     return false;
 // CHECK-NEXT:   }
-// CHECK-NEXT:   case GIPFP_I64_Predicate_simm8: {
+// CHECK-NEXT:   case GICXXPred_I64_Predicate_simm8: {
 // CHECK-NEXT:      return isInt<8>(Imm);
 // CHECK-NEXT:     llvm_unreachable("ImmediateCode should have returned");
 // CHECK-NEXT:     return false;
 // CHECK-NEXT:   }
 // CHECK-NEXT:   }
 // CHECK-NEXT:   llvm_unreachable("Unknown predicate");
 // CHECK-NEXT:   return false;
 // CHECK-NEXT: }
 
 // CHECK-LABEL: // PatFrag predicates.
 // CHECK-NEXT:  enum {
-// CHECK-NEXT:    GIPFP_APFloat_Predicate_fpimmz = GIPFP_APFloat_Invalid + 1,
+// CHECK-NEXT:    GICXXPred_APFloat_Predicate_fpimmz = GICXXPred_APFloat_Invalid + 1,
 // CHECK-NEXT:  };
 // CHECK-NEXT:  bool MyTargetInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
 // CHECK-NEXT:    switch (PredicateID) {
-// CHECK-NEXT:    case GIPFP_APFloat_Predicate_fpimmz: {
+// CHECK-NEXT:    case GICXXPred_APFloat_Predicate_fpimmz: {
 // CHECK-NEXT:      return Imm->isExactlyValue(0.0);
 // CHECK-NEXT:      llvm_unreachable("ImmediateCode should have returned");
 // CHECK-NEXT:      return false;
 // CHECK-NEXT:    }
 // CHECK-NEXT:    }
 // CHECK-NEXT:    llvm_unreachable("Unknown predicate");
 // CHECK-NEXT:    return false;
 // CHECK-NEXT:  }
 
 // CHECK-LABEL: // PatFrag predicates.
 // CHECK-NEXT:  enum {
-// CHECK-NEXT:    GIPFP_APInt_Predicate_simm9 = GIPFP_APInt_Invalid + 1,
+// CHECK-NEXT:    GICXXPred_APInt_Predicate_simm9 = GICXXPred_APInt_Invalid + 1,
 // CHECK-NEXT:  };
 // CHECK-NEXT:  bool MyTargetInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
 // CHECK-NEXT:    switch (PredicateID) {
-// CHECK-NEXT:    case GIPFP_APInt_Predicate_simm9: {
+// CHECK-NEXT:    case GICXXPred_APInt_Predicate_simm9: {
 // CHECK-NEXT:      return isInt<9>(Imm->getSExtValue());
 // CHECK-NEXT:      llvm_unreachable("ImmediateCode should have returned");
 // CHECK-NEXT:      return false;
 // CHECK-NEXT:    }
 // CHECK-NEXT:    }
 // CHECK-NEXT:    llvm_unreachable("Unknown predicate");
 // CHECK-NEXT:    return false;
 // CHECK-NEXT:  }

 // CHECK: bool MyTargetInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
 // CHECK-NEXT: MachineFunction &MF = *I.getParent()->getParent();
 // CHECK-NEXT: MachineRegisterInfo &MRI = MF.getRegInfo();
 // CHECK-NEXT: const PredicateBitset AvailableFeatures = getAvailableFeatures();
 // CHECK-NEXT: NewMIVector OutMIs;
 // CHECK-NEXT: State.MIs.clear();
 // CHECK-NEXT: State.MIs.push_back(&I);
 
-// CHECK:      if (executeMatchTable(*this, OutMIs, State, ISelInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, CoverageInfo)) {
+// CHECK:      if (executeMatchTable(*this, OutMIs, State, ExecInfo, getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures, &CoverageInfo)) {
 // CHECK-NEXT:   return true;
 // CHECK-NEXT: }
 
 // CHECK: const int64_t *
 // CHECK-LABEL: MyTargetInstructionSelector::getMatchTable() const {
 // CHECK-NEXT: MatchTable0[] = {
 
 //===- Test a pattern with multiple ComplexPatterns in multiple instrs ----===//

 // R21N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // R21N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // R21N-NEXT:    // MIs[0] src1
 // R21N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
 // R21N-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/MyTarget::GPR32RegClassID,
 // R21N-NEXT:    // MIs[0] src2
 // R21N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 //
-// R21O-NEXT:    GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_frag,
+// R21O-NEXT:    GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_frag,
 // R21C-NEXT:    GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/0, GICP_gi_complex,
 // R21N-NEXT:    // MIs[0] src3
 // R21N-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
 // R21C-NEXT:    GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/1, GICP_gi_complex,
-// R21N-NEXT:    GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_frag,
+// R21N-NEXT:    GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_frag,
 // R21C-NEXT:    // (select:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2, complex:{ *:[i32] }:$src3)<<P:Predicate_frag>> => (INSN2:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src3, complex:{ *:[i32] }:$src2)
 
 // R21C-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::INSN2,
 // R21C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 // R21C-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
 // R21C-NEXT:    GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/1,
 // R21C-NEXT:    GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/0,
 // R21C-NEXT:    GIR_MergeMemOperands, /*InsnID*/0, /*MergeInsnID's*/0, GIU_MergeMemOperands_EndOfList,

 
 def MOV1 : I<(outs GPR32:$dst), (ins), [(set GPR32:$dst, 1)]>;
 
 //===- Test a simple pattern with a leaf immediate and a predicate. -------===//
 //
 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
-// NOOPT-NEXT:    GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_simm8,
+// NOOPT-NEXT:    GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GICXXPred_I64_Predicate_simm8,
 // NOOPT-NEXT:    // MIs[0] dst
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] Operand 1
 // NOOPT-NEXT:    // No operand predicates
 // NOOPT-NEXT:    // (imm:{ *:[i32] })<<P:Predicate_simm8>>:$imm => (MOVimm8:{ *:[i32] } (imm:{ *:[i32] }):$imm)
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVimm8,
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 // NOOPT-NEXT:    GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 // NOOPT-NEXT:    // GIR_Coverage, 8,
 // NOOPT-NEXT:    GIR_Done,
 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 
 def simm8 : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>;
 def MOVimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, simm8:$imm)]>;
 
 //===- Same again but use an IntImmLeaf. ----------------------------------===//
 //
 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
-// NOOPT-NEXT:    GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APInt_Predicate_simm9,
+// NOOPT-NEXT:    GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GICXXPred_APInt_Predicate_simm9,
 // NOOPT-NEXT:    // MIs[0] dst
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] Operand 1
 // NOOPT-NEXT:    // No operand predicates
 // NOOPT-NEXT:    // (imm:{ *:[i32] })<<P:Predicate_simm9>>:$imm =>  (MOVimm9:{ *:[i32] } (imm:{ *:[i32] }):$imm)
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVimm9,
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 // NOOPT-NEXT:    GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 // NOOPT-NEXT:    // GIR_Coverage, 9,
 // NOOPT-NEXT:    GIR_Done,
 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 
 def simm9 : IntImmLeaf<i32, [{ return isInt<9>(Imm->getSExtValue()); }]>;
 def MOVimm9 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, simm9:$imm)]>;
 
 //===- Test a pattern with a custom renderer. -----------------------------===//
 //
 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_CONSTANT,
-// NOOPT-NEXT:    GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIPFP_I64_Predicate_cimm8,
+// NOOPT-NEXT:    GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GICXXPred_I64_Predicate_cimm8,
 // NOOPT-NEXT:    // MIs[0] dst
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] Operand 1
 // NOOPT-NEXT:    // No operand predicates
 // NOOPT-NEXT:    // (imm:{ *:[i32] })<<P:Predicate_cimm8>><<X:cimm8_xform>>:$imm  =>  (MOVcimm8:{ *:[i32] } (cimm8_xform:{ *:[i32] } (imm:{ *:[i32] }):$imm))
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVcimm8,
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
 // NOOPT-NEXT:    GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GICR_renderImm, // imm
 // NOOPT-NEXT:    GIR_EraseFromParent, /*InsnID*/0,
 // NOOPT-NEXT:    GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
 // NOOPT-NEXT:    // GIR_Coverage, 10,
 // NOOPT-NEXT:    GIR_Done,
 // NOOPT-NEXT:  // Label [[LABEL_NUM]]: @[[LABEL]]
 
 def MOVcimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, cimm8:$imm)]>;
 
 //===- Test a simple pattern with a FP immediate and a predicate. ---------===//
 //
 // NOOPT-NEXT:  GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ [[LABEL:[0-9]+]],
 // NOOPT-NEXT:    GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
 // NOOPT-NEXT:    GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FCONSTANT,
-// NOOPT-NEXT:    GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIPFP_APFloat_Predicate_fpimmz,
+// NOOPT-NEXT:    GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GICXXPred_APFloat_Predicate_fpimmz,
 // NOOPT-NEXT:    // MIs[0] dst
 // NOOPT-NEXT:    GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // NOOPT-NEXT:    GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::FPR32RegClassID,
 // NOOPT-NEXT:    // MIs[0] Operand 1
 // NOOPT-NEXT:    // No operand predicates
 // NOOPT-NEXT:    // (fpimm:{ *:[f32] })<<P:Predicate_fpimmz>>:$imm =>  (MOVfpimmz:{ *:[f32] } (fpimm:{ *:[f32] }):$imm)
 // NOOPT-NEXT:    GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::MOVfpimmz,
 // NOOPT-NEXT:    GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst

llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td

 // RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
 
 // Verify that all MI predicates are enumerated.
 //
 // CHECK: // PatFrag predicates.
 // CHECK-NEXT: enum {
-// CHECK-NEXT:   GIPFP_MI_Predicate_and_or_pat = GIPFP_MI_Invalid + 1,
-// CHECK-NEXT:   GIPFP_MI_Predicate_or_oneuse,
-// CHECK-NEXT:   GIPFP_MI_Predicate_patfrags_test_pat,
-// CHECK-NEXT:   GIPFP_MI_Predicate_sub3_pat,
+// CHECK-NEXT:   GICXXPred_MI_Predicate_and_or_pat = GICXXPred_MI_Invalid + 1,
+// CHECK-NEXT:   GICXXPred_MI_Predicate_or_oneuse,
+// CHECK-NEXT:   GICXXPred_MI_Predicate_patfrags_test_pat,
+// CHECK-NEXT:   GICXXPred_MI_Predicate_sub3_pat,
 // CHECK-NEXT: };
 
 // Verify that we emit cases for all MI predicates.
 //
 // CHECK: bool MyTargetInstructionSelector::testMIPredicate_MI(
-// CHECK:    case GIPFP_MI_Predicate_and_or_pat: {
+// CHECK:    case GICXXPred_MI_Predicate_and_or_pat: {
 // CHECK:      llvm_unreachable("GISelPredicateCode should have returned");
-// CHECK:    case GIPFP_MI_Predicate_or_oneuse: {
+// CHECK:    case GICXXPred_MI_Predicate_or_oneuse: {
 // CHECK:      llvm_unreachable("GISelPredicateCode should have returned");
-// CHECK:    case GIPFP_MI_Predicate_patfrags_test_pat: {
+// CHECK:    case GICXXPred_MI_Predicate_patfrags_test_pat: {
 // CHECK:      llvm_unreachable("GISelPredicateCode should have returned");
-// CHECK:    case GIPFP_MI_Predicate_sub3_pat: {
+// CHECK:    case GICXXPred_MI_Predicate_sub3_pat: {
 // CHECK:      llvm_unreachable("GISelPredicateCode should have returned");
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 // Boilerplate code for setting up some registers with subregs.
 class MyReg<string n, list<Register> subregs = []>
   : Register<n> {

 // CHECK-NEXT: // MIs[1] src0
 // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:3:x
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/Test::DRegsRegClassID,
 // CHECK-NEXT: // MIs[1] src1
 // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Test::DRegsRegClassID,
-// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_and_or_pat,
+// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_and_or_pat,
 // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
 // CHECK-NEXT: // (and:{ *:[i32] } DOP:{ *:[i32] }:$src2:$pred:3:z, (or:{ *:[i32] } DOP:{ *:[i32] }:$src0:$pred:3:x, DOP:{ *:[i32] }:$src1:$pred:3:y))<<P:3:Predicate_and_or_pat>>  =>  (AND_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2)
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::AND_OR,
 
 // CHECK: GIM_Try, /*On fail goto*//*Label 1*/ 198, // Rule ID 3 //
 // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
 // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_AND,
 // CHECK-NEXT: // MIs[0] dst

 // CHECK-NEXT: // MIs[1] src1
 // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/Test::DRegsRegClassID,
 // CHECK-NEXT: // MIs[0] src2
 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:3:z
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/Test::DRegsRegClassID,
-// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_and_or_pat,
+// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_and_or_pat,
 // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
 // CHECK-NEXT: // (and:{ *:[i32] } (or:{ *:[i32] } DOP:{ *:[i32] }:$src0:$pred:3:x, DOP:{ *:[i32] }:$src1:$pred:3:y), DOP:{ *:[i32] }:$src2:$pred:3:z)<<P:3:Predicate_and_or_pat>>  =>  (AND_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2)
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::AND_OR,
 
 // Test commutative, standalone pattern.
 def : Pat<
   (i32 (and_or_pat DOP:$src0, DOP:$src1, DOP:$src2)),
   (AND_OR DOP:$src0, DOP:$src1, DOP:$src2)

 // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x
 // CHECK-NEXT: // MIs[1] src1
 // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:1:y
 // CHECK-NEXT: // MIs[0] src2
 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:1:z
-// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_sub3_pat,
+// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_sub3_pat,
 // CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
 // CHECK-NEXT: // (sub:{ *:[i32] } (sub:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:1:x, i32:{ *:[i32] }:$src1:$pred:1:y), i32:{ *:[i32] }:$src2:$pred:1:z)<<P:1:Predicate_sub3_pat>>  =>  (SUB3:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SUB3,
 
 // Test a non-commutative pattern.
 def SUB3 : I<(outs DRegs:$dst),
   (ins DOP:$src0, DOP:$src1, DOP:$src2),
   [(set DRegs:$dst, (sub3_pat i32:$src0, i32:$src1, i32:$src2))]

llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td

 // GIM_CheckPointerToAny rather than a GIM_CheckType.
 //
 // CHECK: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, Intrinsic::mytarget_anyptr,
 // CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
 // CHECK-NEXT: // MIs[0] src
 // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
 // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
-// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_frag_anyptr,
+// CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GICXXPred_MI_Predicate_frag_anyptr,
 // CHECK-NEXT: // (intrinsic_w_chain:{ *:[i32] } {{[0-9]+}}:{ *:[iPTR] }, GPR32:{ *:[i32] }:$src)<<P:Predicate_frag_anyptr>>  =>  (ANYLOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src)
 // CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ANYLOAD,
 let hasSideEffects = 1 in {
   def ANYLOAD : I<(outs GPR32:$dst), (ins GPR32:$src1),
             [(set GPR32:$dst, (load GPR32:$src1))]>;
 }
 
 def frag_anyptr : PatFrag<(ops node:$src),
                    (int_mytarget_anyptr node:$src),
                    [{ return true; // C++ code }]> {
   let GISelPredicateCode = [{ return true; // C++ code }];
 }
 
 def : Pat<(frag_anyptr GPR32:$src),
           (p0 (ANYLOAD GPR32:$src))>;

llvm/test/TableGen/immarg-predicated.td

 // RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/Common -I %p/../../include %s -o - < %s | FileCheck -check-prefix=GISEL %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
 let TargetPrefix = "mytarget" in {
 def int_mytarget_sleep0 : Intrinsic<[], [llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
 }
 
 // GISEL: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS,
 // GISEL-NEXT: // MIs[0] Operand 0
 // GISEL-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, Intrinsic::mytarget_sleep0,
 // GISEL-NEXT: // MIs[0] src
 // GISEL-NEXT: GIM_CheckIsImm, /*MI*/0, /*Op*/1,
-// GISEL-NEXT: GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIPFP_I64_Predicate_tuimm9,
+// GISEL-NEXT: GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GICXXPred_I64_Predicate_tuimm9,
 // GISEL-NEXT: // (intrinsic_void {{[0-9]+}}:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_tuimm9>>:$src) => (SLEEP0 (timm:{ *:[i32] }):$src)
 // GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::SLEEP0,
 // GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
 def tuimm9 : TImmLeaf<i32, [{ return isUInt<9>(Imm); }]>;
 def SLEEP0 : I<(outs), (ins i32imm:$src),
   [(int_mytarget_sleep0 tuimm9:$src)]
 >;

llvm/test/TableGen/predicate-patfags.td

 // SDAG: OPC_CheckOpcode, TARGET_VAL(ISD::INTRINSIC_W_CHAIN),
 // SDAG: OPC_CheckPredicate, 0, // Predicate_TGTmul24_oneuse
 
 // SDAG: OPC_CheckOpcode, TARGET_VAL(TargetISD::MUL24),
 // SDAG: OPC_CheckPredicate, 0, // Predicate_TGTmul24_oneuse
 
 // GISEL: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS,
 // GISEL: GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::tgt_mul24,
-// GISEL: GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_TGTmul24_oneuse,
+// GISEL: GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GICXXPred_MI_Predicate_TGTmul24_oneuse,
 
 // GISEL: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS,
 // GISEL: GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, Intrinsic::tgt_mul24,
-// GISEL: GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_TGTmul24_oneuse,
+// GISEL: GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GICXXPred_MI_Predicate_TGTmul24_oneuse,
 
 // GISEL: GIM_CheckOpcode, /*MI*/1, MyTarget::G_TGT_MUL24,
-// GISEL: GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_TGTmul24_oneuse,
+// GISEL: GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GICXXPred_MI_Predicate_TGTmul24_oneuse,
 
 // GISEL: GIM_CheckOpcode, /*MI*/1, MyTarget::G_TGT_MUL24,
-// GISEL: GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIPFP_MI_Predicate_TGTmul24_oneuse,
+// GISEL: GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GICXXPred_MI_Predicate_TGTmul24_oneuse,
 def inst_mad24 : I<
   (outs GPR32:$dst),
   (ins GPR32:$src0, GPR32:$src1, GPR32:$src2),
   [(set GPR32:$dst, (add (TGTmul24_oneuse i32:$src0, i32:$src1), i32:$src2))]>;

llvm/utils/TableGen/GlobalISelEmitter.cpp

std::copy_if(Defs.begin(), Defs.end(), std::back_inserter(MatchedRecords),
                  return !Record->getValueAsString(CodeFieldName).empty() &&
                         Filter(Record);
                });
 
   if (!MatchedRecords.empty()) {
     OS << "// PatFrag predicates.\n"
        << "enum {\n";
     std::string EnumeratorSeparator =
-        (" = GIPFP_" + TypeIdentifier + "_Invalid + 1,\n").str();
+        (" = GICXXPred_" + TypeIdentifier + "_Invalid + 1,\n").str();
     for (const auto *Record : MatchedRecords) {
-      OS << "  GIPFP_" << TypeIdentifier << "_Predicate_" << Record->getName()
-         << EnumeratorSeparator;
+      OS << "  GICXXPred_" << TypeIdentifier << "_Predicate_"
+         << Record->getName() << EnumeratorSeparator;
       EnumeratorSeparator = ",\n";
     }
     OS << "};\n";
   }
 
   OS << "bool " << Target.getName() << "InstructionSelector::test" << ArgName
      << "Predicate_" << TypeIdentifier << "(unsigned PredicateID, " << ArgType
      << " " << ArgName << AdditionalArgs << ") const {\n"
      << AdditionalDeclarations;
   if (!AdditionalDeclarations.empty())
     OS << "\n";
   if (!MatchedRecords.empty())
     OS << "  switch (PredicateID) {\n";
   for (const auto *Record : MatchedRecords) {
-    OS << "  case GIPFP_" << TypeIdentifier << "_Predicate_"
+    OS << "  case GICXXPred_" << TypeIdentifier << "_Predicate_"
        << Record->getName() << ": {\n"
        << "    " << Record->getValueAsString(CodeFieldName) << "\n"
        << "    llvm_unreachable(\"" << CodeFieldName
        << " should have returned\");\n"
        << "    return false;\n"
        << "  }\n";
   }
   if (!MatchedRecords.empty())
     OS << "  }\n";
   OS << "  llvm_unreachable(\"Unknown predicate\");\n"
      << "  return false;\n"
      << "}\n";
 }
 
 void GlobalISelEmitter::emitImmPredicateFns(
     raw_ostream &OS, StringRef TypeIdentifier, StringRef ArgType,
     std::function<bool(const Record *R)> Filter) {
   return emitCxxPredicateFns(OS, "ImmediateCode", TypeIdentifier, ArgType,
                              "Imm", "", "", Filter);
 }
 
 void GlobalISelEmitter::emitMIPredicateFns(raw_ostream &OS) {
   return emitCxxPredicateFns(
       OS, "GISelPredicateCode", "MI", "const MachineInstr &", "MI",
-      ", const std::array<const MachineOperand *, 3> &Operands",
+      ", const MatcherState &State",
       "  const MachineFunction &MF = *MI.getParent()->getParent();\n"
       "  const MachineRegisterInfo &MRI = MF.getRegInfo();\n"
+      "  const auto &Operands = State.RecordedOperands;\n"
+      "  (void)Operands;\n"
       "  (void)MRI;",
       [](const Record *R) { return true; });
 }
 
 MatchTable
 GlobalISelEmitter::buildMatchTable(MutableArrayRef<RuleMatcher> Rules,
                                    bool Optimize, bool WithCoverage) {
   std::vector<Matcher *> InputRules;
<< "  typedef "
         "ComplexRendererFns("
      << Target.getName()
      << "InstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;\n"
 
      << "  typedef void(" << Target.getName()
      << "InstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const "
         "MachineInstr &, int) "
         "const;\n"
-     << "  const ISelInfoTy<PredicateBitset, ComplexMatcherMemFn, "
+     << "  const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, "
         "CustomRendererFn> "
-        "ISelInfo;\n";
+        "ExecInfo;\n";
   OS << "  static " << Target.getName()
      << "InstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];\n"
      << "  static " << Target.getName()
      << "InstructionSelector::CustomRendererFn CustomRenderers[];\n"
      << "  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const "
         "override;\n"
      << "  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) "
         "const override;\n"
      << "  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat "
         "&Imm) const override;\n"
      << "  const int64_t *getMatchTable() const override;\n"
      << "  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI"
-        ", const std::array<const MachineOperand *, 3> &Operands) "
+        ", const MatcherState &State) "
         "const override;\n"
      << "#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL\n\n";
 
   OS << "#ifdef GET_GLOBALISEL_TEMPORARIES_INIT\n"
      << ", State(" << MaxTemporaries << "),\n"
-     << "ISelInfo(TypeObjects, NumTypeObjects, FeatureBitsets"
+     << "ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets"
      << ", ComplexPredicateFns, CustomRenderers)\n"
      << "#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT\n\n";
 
   OS << "#ifdef GET_GLOBALISEL_IMPL\n";
   SubtargetFeatureInfo::emitSubtargetFeatureBitEnumeration(SubtargetFeatures,
                                                            OS);
 
   // Separate subtarget features by how often they must be recomputed.
OS << "bool " << Target.getName()
      << "InstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage "
         "&CoverageInfo) const {\n"
      << "  MachineFunction &MF = *I.getParent()->getParent();\n"
      << "  MachineRegisterInfo &MRI = MF.getRegInfo();\n"
      << "  const PredicateBitset AvailableFeatures = getAvailableFeatures();\n"
      << "  NewMIVector OutMIs;\n"
      << "  State.MIs.clear();\n"
      << "  State.MIs.push_back(&I);\n\n"
-     << "  if (executeMatchTable(*this, OutMIs, State, ISelInfo"
+     << "  if (executeMatchTable(*this, OutMIs, State, ExecInfo"
      << ", getMatchTable(), TII, MRI, TRI, RBI, AvailableFeatures"
-     << ", CoverageInfo)) {\n"
+     << ", &CoverageInfo)) {\n"
      << "    return true;\n"
      << "  }\n\n"
      << "  return false;\n"
      << "}\n\n";
 
   const MatchTable Table =
       buildMatchTable(Rules, OptimizeMatchTable, GenerateCoverage);
   OS << "const int64_t *" << Target.getName()

llvm/utils/TableGen/GlobalISelMatchTable.h

 //===- GlobalISelMatchTable.h ---------------------------------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 /// \file
 /// This file contains the code related to the GlobalISel Match Table emitted by
 /// GlobalISelEmitter.cpp. The generated match table is interpreted at runtime
-/// by `InstructionSelectorImpl.h` to match & apply ISel patterns.
+/// by `GIMatchTableExecutorImpl.h` to match & apply ISel patterns.
 ///
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_UTILS_TABLEGEN_GLOBALISELMATCHTABLE_H
 #define LLVM_UTILS_TABLEGEN_GLOBALISELMATCHTABLE_H
 
 #include "CodeGenDAGPatterns.h"
 #include "llvm/ADT/ArrayRef.h"

llvm/utils/TableGen/GlobalISelMatchTable.cpp

 
 Error failUnsupported(const Twine &Reason) {
   return make_error<StringError>(Reason, inconvertibleErrorCode());
 }
 
 /// Get the name of the enum value used to number the predicate function.
 std::string getEnumNameForPredicate(const TreePredicateFn &Predicate) {
   if (Predicate.hasGISelPredicateCode())
-    return "GIPFP_MI_" + Predicate.getFnName();
-  return "GIPFP_" + Predicate.getImmTypeIdentifier().str() + "_" +
+    return "GICXXPred_MI_" + Predicate.getFnName();
+  return "GICXXPred_" + Predicate.getImmTypeIdentifier().str() + "_" +
          Predicate.getFnName();
 }
 
 std::string getMatchOpcodeForImmPredicate(const TreePredicateFn &Predicate) {
   return "GIM_Check" + Predicate.getImmTypeIdentifier().str() + "ImmPredicate";
 }
 } // namespace