[DAGCombine] Fold (store (insert_elt (load p)) x p) -> (store x)

[luke]

Summary

If we have a store of a load with no other uses in between it, it's
considered dead and is removed. So sometimes when legalizing a fixed
length vector store of an insert, we end up producing better code
through scalarization than without.
An example is the follow below:

%a = load <4 x i64>, ptr %x
%b = insertelement <4 x i64> %a, i64 %y, i32 2
store <4 x i64> %b, ptr %x

If this is scalarized, then DAGCombine successfully removes 3 of the 4
stores which are considered dead, and on RISC-V we get:

sd a1, 16(a0)

However if we make the vector type legal (-mattr=+v), then we lose the
optimisation because we don't scalarize it.

This patch attempts to recover the optimisation for vectors by
identifying patterns where we store a load with a single insert
inbetween, replacing it with a scalar store of the inserted element.

[luke]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

8

This might be obscuring the behaviour of the actual insert_vector_elt codegen. Let me know if I should mark these stores as volatile

[luke]

Reuse variable, use better comment

[RKSimon]

llvm/test/CodeGen/X86/fold-load-vec.ll

17 ↗

(On Diff #528873)

Limit to cases where the insertion is the only user of the load?

[luke]

Limit to cases where the store is the only user of the insert_subvector

[luke]

llvm/test/CodeGen/X86/fold-load-vec.ll

17 ↗

(On Diff #528873)

Sorry for the delay, rebased and updated now. Limiting to loads with a single use didn't fix this case, but limiting to inserts with a single use worked instead

[RKSimon]

LGTM - we just need to clear up whether fixed-vectors-insert.ll needs tweaking

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

8

@craig.topper Any thoughts on this?

[frasercrmck]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

8

Maybe we can just write a separate test function that inserts into vectors passed by value? I personally consider the load/store idiom in these tests to be from before we added proper vector calling convention support.

[luke]

Rebase ontop of D153964

[luke]

Manually update some non-update_test_checks.py tests to use volatile stores so they don't trigger the combine

[luke]

llvm/test/CodeGen/ARM/fp16-promote.ll

902

Didn't notice some of these tests were hand written, just updated the diff there to mark some of the stores as volatile to prevent the combine from kicking in.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

private:
     SDValue visitFFLOOR(SDNode *N);
     SDValue visitFMinMax(SDNode *N);
     SDValue visitBRCOND(SDNode *N);
     SDValue visitBR_CC(SDNode *N);
     SDValue visitLOAD(SDNode *N);
 
     SDValue replaceStoreChain(StoreSDNode *ST, SDValue BetterChain);
     SDValue replaceStoreOfFPConstant(StoreSDNode *ST);
+    SDValue replaceStoreOfInsertLoad(StoreSDNode *ST);
 
     bool refineExtractVectorEltIntoMultipleNarrowExtractVectorElts(SDNode *N);
 
     SDValue visitSTORE(SDNode *N);
     SDValue visitLIFETIME_END(SDNode *N);
     SDValue visitINSERT_VECTOR_ELT(SDNode *N);
     SDValue visitEXTRACT_VECTOR_ELT(SDNode *N);
     SDValue visitBUILD_VECTOR(SDNode *N);
if (ST->isSimple() &&
       return DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
                          St0, St1);
     }
 
     return SDValue();
   }
 }
 
+// (store (insert_vector_elt (load p), x, i), p) -> (store x, p+offset)
+//
+// If a store of a load with an element inserted into it has no other
+// uses in between the chain, then we can consider the vector store
+// dead and replace it with just the single scalar element store.
+SDValue DAGCombiner::replaceStoreOfInsertLoad(StoreSDNode *ST) {
+  SDLoc DL(ST);
+  SDValue Value = ST->getValue();
+  SDValue Ptr = ST->getBasePtr();
+  SDValue Chain = ST->getChain();
+  if (Value.getOpcode() != ISD::INSERT_VECTOR_ELT || !Value.hasOneUse())
+    return SDValue();
+
+  SDValue Elt = Value.getOperand(1);
+  SDValue Idx = Value.getOperand(2);
+
+  // If the element isn't byte sized then we can't compute an offset
+  EVT EltVT = Elt.getValueType();
+  if (!EltVT.isByteSized())
+    return SDValue();
+
+  auto *Ld = dyn_cast<LoadSDNode>(Value.getOperand(0));
+  if (!Ld || Ld->getBasePtr() != Ptr ||
+      ST->getMemoryVT() != Ld->getMemoryVT() || !ST->isSimple() ||
+      !ISD::isNormalStore(ST) ||
+      Ld->getAddressSpace() != ST->getAddressSpace() ||
+      !Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1)))
+    return SDValue();
+
+  unsigned IsFast;
+  if (!TLI.allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(),
+                              Elt.getValueType(), ST->getAddressSpace(),
+                              ST->getAlign(), ST->getMemOperand()->getFlags(),
+                              &IsFast) ||
+      !IsFast)
+    return SDValue();
+  EVT PtrVT = Ptr.getValueType();
+
+  SDValue Offset =
+      DAG.getNode(ISD::MUL, DL, PtrVT, Idx,
+                  DAG.getConstant(EltVT.getSizeInBits() / 8, DL, PtrVT));
+  SDValue NewPtr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, Offset);
+  MachinePointerInfo PointerInfo(ST->getAddressSpace());
+
+  // If the offset is a known constant then try to recover the pointer
+  // info
+  if (auto *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
+    unsigned COffset = CIdx->getSExtValue() * EltVT.getSizeInBits() / 8;
+    NewPtr = DAG.getMemBasePlusOffset(Ptr, TypeSize::Fixed(COffset), DL);
+    PointerInfo = ST->getPointerInfo().getWithOffset(COffset);
+  }
+
+  return DAG.getStore(Chain, DL, Elt, NewPtr, PointerInfo, ST->getAlign(),
+                      ST->getMemOperand()->getFlags());
+}
+
 SDValue DAGCombiner::visitSTORE(SDNode *N) {
   StoreSDNode *ST  = cast<StoreSDNode>(N);
   SDValue Chain = ST->getChain();
   SDValue Value = ST->getValue();
   SDValue Ptr   = ST->getBasePtr();
 
   // If this is a store of a bit convert, store the input value if the
   // resultant store does not need a higher alignment than the original.
if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() &&
         // There can't be any side effects between the load and store, such as
         // a call or store.
         Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) {
       // The store is dead, remove it.
       return Chain;
     }
   }
 
+  // Try scalarizing vector stores of loads where we only change one element
+  if (SDValue NewST = replaceStoreOfInsertLoad(ST))
+    return NewST;
+
   // TODO: Can relax for unordered atomics (see D66309)
   if (StoreSDNode *ST1 = dyn_cast<StoreSDNode>(Chain)) {
     if (ST->isUnindexed() && ST->isSimple() &&
         ST1->isUnindexed() && ST1->isSimple()) {
       if (OptLevel != CodeGenOpt::None && ST1->getBasePtr() == Ptr &&
           ST1->getValue() == Value && ST->getMemoryVT() == ST1->getMemoryVT() &&
           ST->getAddressSpace() == ST1->getAddressSpace()) {
         // If this is a store followed by a store with the same value to the

llvm/test/CodeGen/AArch64/vector-insert-shuffle-cycle.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc %s -o - | FileCheck %s
 
 target triple = "arm64-apple-ios13.4.0"
 
 ; Make we do not get stuck in a cycle in DAGCombiner.
 
 define void @test(i1 %c, ptr %ptr) {
 ; CHECK-LABEL: test:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    movi d0, #0000000000000000
 ; CHECK-NEXT:    tbz w0, #0, LBB0_2
 ; CHECK-NEXT:  ; %bb.1: ; %bb1
 ; CHECK-NEXT:    ldr d0, [x1]
 ; CHECK-NEXT:  LBB0_2: ; %bb2
-; CHECK-NEXT:    ldr q1, [x8]
-; CHECK-NEXT:    mov.d v1[0], v0[0]
-; CHECK-NEXT:    str q1, [x8]
+; CHECK-NEXT:    str d0, [x8]
 ; CHECK-NEXT:    ret
 entry:
   br i1 %c, label %bb1, label %bb2
 
 bb1:
   %lv1 = load <1 x double>, ptr %ptr, align 16
   br label %bb2
 

llvm/test/CodeGen/ARM/fp16-promote.ll

 
 ; CHECK-VFP:  and 
 ; CHECK-VFP:  mov 
 ; CHECK-VFP:  ldrd  
 ; CHECK-VFP:  orr 
 ; CHECK-VFP:  ldrh  
 ; CHECK-VFP:  stm 
 ; CHECK-VFP:  strh  
-; CHECK-VFP:  ldm 
-; CHECK-VFP:  stm 
+; CHECK-VFP:  ldrh  
+; CHECK-VFP:  ldrh  
+; CHECK-VFP:  ldrh
+; CHECK-VFP:  ldrh
+; CHECK-VFP:  strh
+; CHECK-VFP:  strh
+; CHECK-VFP:  strh
+; CHECK-VFP:  strh  
 
 ; CHECK-NOVFP: ldrh
 ; CHECK-NOVFP: ldrh
 ; CHECK-NOVFP: ldrh
 ; CHECK-NOVFP: ldrh
 ; CHECK-NOVFP-DAG: strh
 ; CHECK-NOVFP-DAG: strh
 ; CHECK-NOVFP-DAG: mov

 ; CHECK-NOVFP-DAG: strh
 ; CHECK-NOVFP-DAG: strh
 
 ; CHECK-ALL: add sp, sp, #8
 define void @test_insertelement(ptr %p, ptr %q, i32 %i) #0 {
   %a = load half, ptr %p, align 2
   %b = load <4 x half>, ptr %q, align 8
   %c = insertelement <4 x half> %b, half %a, i32 %i
-  store <4 x half> %c, ptr %q
+  store volatile <4 x half> %c, ptr %q
   ret void
 }
 
 ; CHECK-ALL-LABEL: test_extractelement:
 ; CHECK-VFP: push {{{.*}}, lr}
 ; CHECK-VFP: sub sp, sp, #8
 ; CHECK-VFP: ldrd
 ; CHECK-VFP: mov

llvm/test/CodeGen/ARM/vector-DAGCombine.ll

; CHECK-NEXT:    bx lr
   %t1 = insertelement <2 x i64> undef, i64 %t0, i32 0
   store <2 x i64> %t1, ptr %vp
   ret void
 }
 
 define void @i64_insertelement(ptr %ptr, ptr %vp) nounwind {
 ; CHECK-LABEL: i64_insertelement:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    vld1.64 {d16, d17}, [r1]
-; CHECK-NEXT:    vldr d16, [r0]
-; CHECK-NEXT:    vst1.64 {d16, d17}, [r1]
+; CHECK-NEXT:    ldm r0, {r2, r3}
+; CHECK-NEXT:    strd r2, r3, [r1]
 ; CHECK-NEXT:    bx lr
   %t0 = load i64, ptr %ptr, align 4
   %vec = load <2 x i64>, ptr %vp
   %t1 = insertelement <2 x i64> %vec, i64 %t0, i32 0
   store <2 x i64> %t1, ptr %vp
   ret void
 }
 

llvm/test/CodeGen/Hexagon/autohvx/hfinsert.ll

 ; RUN: llc -march=hexagon < %s | FileCheck %s
 
 ; Check that we generate a proper vinsert instruction for f16 types.
 ; CHECK: vinsert
 target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
 target triple = "hexagon"
 
 define ptr @fred(ptr %v0) local_unnamed_addr #0 {
 b0:
   %v1 = load <64 x half>, ptr %v0, align 2
   %v2 = insertelement <64 x half> %v1, half 0xH4170, i32 17
-  store <64 x half> %v2, ptr %v0, align 2
+  store volatile <64 x half> %v2, ptr %v0, align 2
   ret ptr %v0
 }
 
 attributes #0 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv69" "target-features"="+hvx-length128b,+hvxv69,+v69,+hvx-qfloat,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }

llvm/test/CodeGen/Mips/msa/basic_operations.ll

 
 define void @insert_v16i8(i32 signext %a) nounwind {
 ; O32-LABEL: insert_v16i8:
 ; O32:       # %bb.0:
 ; O32-NEXT:    lui $2, %hi(_gp_disp)
 ; O32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O32-NEXT:    addu $1, $2, $25
 ; O32-NEXT:    lw $1, %got(v16i8)($1)
-; O32-NEXT:    ld.b $w0, 0($1)
-; O32-NEXT:    insert.b $w0[1], $4
 ; O32-NEXT:    jr $ra
-; O32-NEXT:    st.b $w0, 0($1)
+; O32-NEXT:    sb $4, 1($1)
 ;
 ; N32-LABEL: insert_v16i8:
 ; N32:       # %bb.0:
 ; N32-NEXT:    lui $1, %hi(%neg(%gp_rel(insert_v16i8)))
 ; N32-NEXT:    addu $1, $1, $25
 ; N32-NEXT:    addiu $1, $1, %lo(%neg(%gp_rel(insert_v16i8)))
 ; N32-NEXT:    lw $1, %got_disp(v16i8)($1)
-; N32-NEXT:    ld.b $w0, 0($1)
-; N32-NEXT:    insert.b $w0[1], $4
 ; N32-NEXT:    jr $ra
-; N32-NEXT:    st.b $w0, 0($1)
+; N32-NEXT:    sb $4, 1($1)
 ;
 ; N64-LABEL: insert_v16i8:
 ; N64:       # %bb.0:
 ; N64-NEXT:    lui $1, %hi(%neg(%gp_rel(insert_v16i8)))
 ; N64-NEXT:    daddu $1, $1, $25
 ; N64-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(insert_v16i8)))
 ; N64-NEXT:    ld $1, %got_disp(v16i8)($1)
-; N64-NEXT:    ld.b $w0, 0($1)
-; N64-NEXT:    insert.b $w0[1], $4
 ; N64-NEXT:    jr $ra
-; N64-NEXT:    st.b $w0, 0($1)
+; N64-NEXT:    sb $4, 1($1)
   %1 = load <16 x i8>, ptr @v16i8
   %a2 = trunc i32 %a to i8
   %a3 = sext i8 %a2 to i32
   %a4 = trunc i32 %a3 to i8
   %2 = insertelement <16 x i8> %1, i8 %a4, i32 1
   store <16 x i8> %2, ptr @v16i8
   ret void
 }
 
 define void @insert_v8i16(i32 signext %a) nounwind {
 ; O32-LABEL: insert_v8i16:
 ; O32:       # %bb.0:
 ; O32-NEXT:    lui $2, %hi(_gp_disp)
 ; O32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O32-NEXT:    addu $1, $2, $25
 ; O32-NEXT:    lw $1, %got(v8i16)($1)
-; O32-NEXT:    ld.h $w0, 0($1)
-; O32-NEXT:    insert.h $w0[1], $4
 ; O32-NEXT:    jr $ra
-; O32-NEXT:    st.h $w0, 0($1)
+; O32-NEXT:    sh $4, 2($1)
 ;
 ; N32-LABEL: insert_v8i16:
 ; N32:       # %bb.0:
 ; N32-NEXT:    lui $1, %hi(%neg(%gp_rel(insert_v8i16)))
 ; N32-NEXT:    addu $1, $1, $25
 ; N32-NEXT:    addiu $1, $1, %lo(%neg(%gp_rel(insert_v8i16)))
 ; N32-NEXT:    lw $1, %got_disp(v8i16)($1)
-; N32-NEXT:    ld.h $w0, 0($1)
-; N32-NEXT:    insert.h $w0[1], $4
 ; N32-NEXT:    jr $ra
-; N32-NEXT:    st.h $w0, 0($1)
+; N32-NEXT:    sh $4, 2($1)
 ;
 ; N64-LABEL: insert_v8i16:
 ; N64:       # %bb.0:
 ; N64-NEXT:    lui $1, %hi(%neg(%gp_rel(insert_v8i16)))
 ; N64-NEXT:    daddu $1, $1, $25
 ; N64-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(insert_v8i16)))
 ; N64-NEXT:    ld $1, %got_disp(v8i16)($1)
-; N64-NEXT:    ld.h $w0, 0($1)
-; N64-NEXT:    insert.h $w0[1], $4
 ; N64-NEXT:    jr $ra
-; N64-NEXT:    st.h $w0, 0($1)
+; N64-NEXT:    sh $4, 2($1)
   %1 = load <8 x i16>, ptr @v8i16
   %a2 = trunc i32 %a to i16
   %a3 = sext i16 %a2 to i32
   %a4 = trunc i32 %a3 to i16
   %2 = insertelement <8 x i16> %1, i16 %a4, i32 1
   store <8 x i16> %2, ptr @v8i16
   ret void
 }
 
 define void @insert_v4i32(i32 signext %a) nounwind {
 ; O32-LABEL: insert_v4i32:
 ; O32:       # %bb.0:
 ; O32-NEXT:    lui $2, %hi(_gp_disp)
 ; O32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O32-NEXT:    addu $1, $2, $25
 ; O32-NEXT:    lw $1, %got(v4i32)($1)
-; O32-NEXT:    ld.w $w0, 0($1)
-; O32-NEXT:    insert.w $w0[1], $4
 ; O32-NEXT:    jr $ra
-; O32-NEXT:    st.w $w0, 0($1)
+; O32-NEXT:    sw $4, 4($1)
 ;
 ; N32-LABEL: insert_v4i32:
 ; N32:       # %bb.0:
 ; N32-NEXT:    lui $1, %hi(%neg(%gp_rel(insert_v4i32)))
 ; N32-NEXT:    addu $1, $1, $25
 ; N32-NEXT:    addiu $1, $1, %lo(%neg(%gp_rel(insert_v4i32)))
 ; N32-NEXT:    lw $1, %got_disp(v4i32)($1)
-; N32-NEXT:    ld.w $w0, 0($1)
-; N32-NEXT:    insert.w $w0[1], $4
 ; N32-NEXT:    jr $ra
-; N32-NEXT:    st.w $w0, 0($1)
+; N32-NEXT:    sw $4, 4($1)
 ;
 ; N64-LABEL: insert_v4i32:
 ; N64:       # %bb.0:
 ; N64-NEXT:    lui $1, %hi(%neg(%gp_rel(insert_v4i32)))
 ; N64-NEXT:    daddu $1, $1, $25
 ; N64-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(insert_v4i32)))
 ; N64-NEXT:    ld $1, %got_disp(v4i32)($1)
-; N64-NEXT:    ld.w $w0, 0($1)
-; N64-NEXT:    insert.w $w0[1], $4
 ; N64-NEXT:    jr $ra
-; N64-NEXT:    st.w $w0, 0($1)
+; N64-NEXT:    sw $4, 4($1)
   %1 = load <4 x i32>, ptr @v4i32
   %2 = insertelement <4 x i32> %1, i32 %a, i32 1
   store <4 x i32> %2, ptr @v4i32
   ret void
 }
 define void @insert_v2i64(i64 signext %a) nounwind {
 ; O32-LABEL: insert_v2i64:
 ; O32:       # %bb.0:
 ; O32-NEXT:    lui $2, %hi(_gp_disp)
 ; O32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O32-NEXT:    addu $1, $2, $25
 ; O32-NEXT:    lw $1, %got(v2i64)($1)
-; O32-NEXT:    ld.w $w0, 0($1)
-; O32-NEXT:    insert.w $w0[2], $4
-; O32-NEXT:    insert.w $w0[3], $5
+; O32-NEXT:    sw $5, 12($1)
 ; O32-NEXT:    jr $ra
-; O32-NEXT:    st.w $w0, 0($1)
+; O32-NEXT:    sw $4, 8($1)
 ;
 ; N32-LABEL: insert_v2i64:
 ; N32:       # %bb.0:
 ; N32-NEXT:    lui $1, %hi(%neg(%gp_rel(insert_v2i64)))
 ; N32-NEXT:    addu $1, $1, $25
 ; N32-NEXT:    addiu $1, $1, %lo(%neg(%gp_rel(insert_v2i64)))
 ; N32-NEXT:    lw $1, %got_disp(v2i64)($1)
-; N32-NEXT:    ld.d $w0, 0($1)
-; N32-NEXT:    insert.d $w0[1], $4
 ; N32-NEXT:    jr $ra
-; N32-NEXT:    st.d $w0, 0($1)
+; N32-NEXT:    sd $4, 8($1)
 ;
 ; N64-LABEL: insert_v2i64:
 ; N64:       # %bb.0:
 ; N64-NEXT:    lui $1, %hi(%neg(%gp_rel(insert_v2i64)))
 ; N64-NEXT:    daddu $1, $1, $25
 ; N64-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(insert_v2i64)))
 ; N64-NEXT:    ld $1, %got_disp(v2i64)($1)
-; N64-NEXT:    ld.d $w0, 0($1)
-; N64-NEXT:    insert.d $w0[1], $4
 ; N64-NEXT:    jr $ra
-; N64-NEXT:    st.d $w0, 0($1)
+; N64-NEXT:    sd $4, 8($1)
   %1 = load <2 x i64>, ptr @v2i64
   %2 = insertelement <2 x i64> %1, i64 %a, i32 1
   store <2 x i64> %2, ptr @v2i64
   ret void
 }
 
 define void @insert_v16i8_vidx(i32 signext %a) nounwind {
 ; O32-LABEL: insert_v16i8_vidx:
 ; O32:       # %bb.0:
 ; O32-NEXT:    lui $2, %hi(_gp_disp)
 ; O32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O32-NEXT:    addu $1, $2, $25
 ; O32-NEXT:    lw $2, %got(i32)($1)
 ; O32-NEXT:    lw $2, 0($2)
 ; O32-NEXT:    lw $1, %got(v16i8)($1)
-; O32-NEXT:    ld.b $w0, 0($1)
-; O32-NEXT:    sld.b $w0, $w0[$2]
-; O32-NEXT:    insert.b $w0[0], $4
-; O32-NEXT:    neg $2, $2
-; O32-NEXT:    sld.b $w0, $w0[$2]
+; O32-NEXT:    addu $1, $1, $2
 ; O32-NEXT:    jr $ra
-; O32-NEXT:    st.b $w0, 0($1)
+; O32-NEXT:    sb $4, 0($1)
 ;
 ; N32-LABEL: insert_v16i8_vidx:
 ; N32:       # %bb.0:
 ; N32-NEXT:    lui $1, %hi(%neg(%gp_rel(insert_v16i8_vidx)))
 ; N32-NEXT:    addu $1, $1, $25
 ; N32-NEXT:    addiu $1, $1, %lo(%neg(%gp_rel(insert_v16i8_vidx)))
 ; N32-NEXT:    lw $2, %got_disp(i32)($1)
 ; N32-NEXT:    lw $2, 0($2)
 ; N32-NEXT:    lw $1, %got_disp(v16i8)($1)
-; N32-NEXT:    ld.b $w0, 0($1)
-; N32-NEXT:    sld.b $w0, $w0[$2]
-; N32-NEXT:    insert.b $w0[0], $4
-; N32-NEXT:    neg $2, $2
-; N32-NEXT:    sld.b $w0, $w0[$2]
+; N32-NEXT:    addu $1, $1, $2
 ; N32-NEXT:    jr $ra
-; N32-NEXT:    st.b $w0, 0($1)
+; N32-NEXT:    sb $4, 0($1)
 ;
 ; N64-LABEL: insert_v16i8_vidx:
 ; N64:       # %bb.0:
 ; N64-NEXT:    lui $1, %hi(%neg(%gp_rel(insert_v16i8_vidx)))
 ; N64-NEXT:    daddu $1, $1, $25
 ; N64-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(insert_v16i8_vidx)))
 ; N64-NEXT:    ld $2, %got_disp(i32)($1)
 ; N64-NEXT:    lwu $2, 0($2)
 ; N64-NEXT:    ld $1, %got_disp(v16i8)($1)
-; N64-NEXT:    ld.b $w0, 0($1)
-; N64-NEXT:    sld.b $w0, $w0[$2]
-; N64-NEXT:    insert.b $w0[0], $4
-; N64-NEXT:    dneg $2, $2
-; N64-NEXT:    sld.b $w0, $w0[$2]
+; N64-NEXT:    daddu $1, $1, $2
 ; N64-NEXT:    jr $ra
-; N64-NEXT:    st.b $w0, 0($1)
+; N64-NEXT:    sb $4, 0($1)
   %1 = load <16 x i8>, ptr @v16i8
   %2 = load i32, ptr @i32
   %a2 = trunc i32 %a to i8
   %a3 = sext i8 %a2 to i32
   %a4 = trunc i32 %a3 to i8
   %3 = insertelement <16 x i8> %1, i8 %a4, i32 %2
   store <16 x i8> %3, ptr @v16i8
   ret void
 }
 
 define void @insert_v8i16_vidx(i32 signext %a) nounwind {
 ; O32-LABEL: insert_v8i16_vidx:
 ; O32:       # %bb.0:
 ; O32-NEXT:    lui $2, %hi(_gp_disp)
 ; O32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O32-NEXT:    addu $1, $2, $25
 ; O32-NEXT:    lw $2, %got(i32)($1)
 ; O32-NEXT:    lw $2, 0($2)
 ; O32-NEXT:    lw $1, %got(v8i16)($1)
-; O32-NEXT:    ld.h $w0, 0($1)
-; O32-NEXT:    sll $2, $2, 1
-; O32-NEXT:    sld.b $w0, $w0[$2]
-; O32-NEXT:    insert.h $w0[0], $4
-; O32-NEXT:    neg $2, $2
-; O32-NEXT:    sld.b $w0, $w0[$2]
+; O32-NEXT:    lsa $1, $2, $1, 1
 ; O32-NEXT:    jr $ra
-; O32-NEXT:    st.h $w0, 0($1)
+; O32-NEXT:    sh $4, 0($1)
 ;
 ; N32-LABEL: insert_v8i16_vidx:
 ; N32:       # %bb.0:
 ; N32-NEXT:    lui $1, %hi(%neg(%gp_rel(insert_v8i16_vidx)))
 ; N32-NEXT:    addu $1, $1, $25
 ; N32-NEXT:    addiu $1, $1, %lo(%neg(%gp_rel(insert_v8i16_vidx)))
 ; N32-NEXT:    lw $2, %got_disp(i32)($1)
 ; N32-NEXT:    lw $2, 0($2)
 ; N32-NEXT:    lw $1, %got_disp(v8i16)($1)
-; N32-NEXT:    ld.h $w0, 0($1)
-; N32-NEXT:    sll $2, $2, 1
-; N32-NEXT:    sld.b $w0, $w0[$2]
-; N32-NEXT:    insert.h $w0[0], $4
-; N32-NEXT:    neg $2, $2
-; N32-NEXT:    sld.b $w0, $w0[$2]
+; N32-NEXT:    lsa $1, $2, $1, 1
 ; N32-NEXT:    jr $ra
-; N32-NEXT:    st.h $w0, 0($1)
+; N32-NEXT:    sh $4, 0($1)
 ;
 ; N64-LABEL: insert_v8i16_vidx:
 ; N64:       # %bb.0:
 ; N64-NEXT:    lui $1, %hi(%neg(%gp_rel(insert_v8i16_vidx)))
 ; N64-NEXT:    daddu $1, $1, $25
 ; N64-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(insert_v8i16_vidx)))
 ; N64-NEXT:    ld $2, %got_disp(i32)($1)
 ; N64-NEXT:    lwu $2, 0($2)
 ; N64-NEXT:    ld $1, %got_disp(v8i16)($1)
-; N64-NEXT:    ld.h $w0, 0($1)
-; N64-NEXT:    dsll $2, $2, 1
-; N64-NEXT:    sld.b $w0, $w0[$2]
-; N64-NEXT:    insert.h $w0[0], $4
-; N64-NEXT:    dneg $2, $2
-; N64-NEXT:    sld.b $w0, $w0[$2]
+; N64-NEXT:    dlsa $1, $2, $1, 1
 ; N64-NEXT:    jr $ra
-; N64-NEXT:    st.h $w0, 0($1)
+; N64-NEXT:    sh $4, 0($1)
   %1 = load <8 x i16>, ptr @v8i16
   %2 = load i32, ptr @i32
   %a2 = trunc i32 %a to i16
   %a3 = sext i16 %a2 to i32
   %a4 = trunc i32 %a3 to i16
   %3 = insertelement <8 x i16> %1, i16 %a4, i32 %2
   store <8 x i16> %3, ptr @v8i16
   ret void
 }
 
 define void @insert_v4i32_vidx(i32 signext %a) nounwind {
 ; O32-LABEL: insert_v4i32_vidx:
 ; O32:       # %bb.0:
 ; O32-NEXT:    lui $2, %hi(_gp_disp)
 ; O32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O32-NEXT:    addu $1, $2, $25
 ; O32-NEXT:    lw $2, %got(i32)($1)
 ; O32-NEXT:    lw $2, 0($2)
 ; O32-NEXT:    lw $1, %got(v4i32)($1)
-; O32-NEXT:    ld.w $w0, 0($1)
-; O32-NEXT:    sll $2, $2, 2
-; O32-NEXT:    sld.b $w0, $w0[$2]
-; O32-NEXT:    insert.w $w0[0], $4
-; O32-NEXT:    neg $2, $2
-; O32-NEXT:    sld.b $w0, $w0[$2]
+; O32-NEXT:    lsa $1, $2, $1, 2
 ; O32-NEXT:    jr $ra
-; O32-NEXT:    st.w $w0, 0($1)
+; O32-NEXT:    sw $4, 0($1)
 ;
 ; N32-LABEL: insert_v4i32_vidx:
 ; N32:       # %bb.0:
 ; N32-NEXT:    lui $1, %hi(%neg(%gp_rel(insert_v4i32_vidx)))
 ; N32-NEXT:    addu $1, $1, $25
 ; N32-NEXT:    addiu $1, $1, %lo(%neg(%gp_rel(insert_v4i32_vidx)))
 ; N32-NEXT:    lw $2, %got_disp(i32)($1)
 ; N32-NEXT:    lw $2, 0($2)
 ; N32-NEXT:    lw $1, %got_disp(v4i32)($1)
-; N32-NEXT:    ld.w $w0, 0($1)
-; N32-NEXT:    sll $2, $2, 2
-; N32-NEXT:    sld.b $w0, $w0[$2]
-; N32-NEXT:    insert.w $w0[0], $4
-; N32-NEXT:    neg $2, $2
-; N32-NEXT:    sld.b $w0, $w0[$2]
+; N32-NEXT:    lsa $1, $2, $1, 2
 ; N32-NEXT:    jr $ra
-; N32-NEXT:    st.w $w0, 0($1)
+; N32-NEXT:    sw $4, 0($1)
 ;
 ; N64-LABEL: insert_v4i32_vidx:
 ; N64:       # %bb.0:
 ; N64-NEXT:    lui $1, %hi(%neg(%gp_rel(insert_v4i32_vidx)))
 ; N64-NEXT:    daddu $1, $1, $25
 ; N64-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(insert_v4i32_vidx)))
 ; N64-NEXT:    ld $2, %got_disp(i32)($1)
 ; N64-NEXT:    lwu $2, 0($2)
 ; N64-NEXT:    ld $1, %got_disp(v4i32)($1)
-; N64-NEXT:    ld.w $w0, 0($1)
-; N64-NEXT:    dsll $2, $2, 2
-; N64-NEXT:    sld.b $w0, $w0[$2]
-; N64-NEXT:    insert.w $w0[0], $4
-; N64-NEXT:    dneg $2, $2
-; N64-NEXT:    sld.b $w0, $w0[$2]
+; N64-NEXT:    dlsa $1, $2, $1, 2
 ; N64-NEXT:    jr $ra
-; N64-NEXT:    st.w $w0, 0($1)
+; N64-NEXT:    sw $4, 0($1)
   %1 = load <4 x i32>, ptr @v4i32
   %2 = load i32, ptr @i32
   %3 = insertelement <4 x i32> %1, i32 %a, i32 %2
   store <4 x i32> %3, ptr @v4i32
   ret void
 }
 
 ; TODO: This code could be a lot better but it works. The legalizer splits
 ; 64-bit inserts into two 32-bit inserts because there is no i64 type on
 ; MIPS32. The obvious optimisation is to perform both insert.w's at once while
 ; the vector is rotated.
 define void @insert_v2i64_vidx(i64 signext %a) nounwind {
 ; O32-LABEL: insert_v2i64_vidx:
 ; O32:       # %bb.0:
 ; O32-NEXT:    lui $2, %hi(_gp_disp)
 ; O32-NEXT:    addiu $2, $2, %lo(_gp_disp)
 ; O32-NEXT:    addu $1, $2, $25
 ; O32-NEXT:    lw $2, %got(i32)($1)
 ; O32-NEXT:    lw $2, 0($2)
-; O32-NEXT:    addu $2, $2, $2
 ; O32-NEXT:    lw $1, %got(v2i64)($1)
-; O32-NEXT:    ld.w $w0, 0($1)
-; O32-NEXT:    sll $3, $2, 2
-; O32-NEXT:    sld.b $w0, $w0[$3]
-; O32-NEXT:    insert.w $w0[0], $4
-; O32-NEXT:    neg $3, $3
-; O32-NEXT:    sld.b $w0, $w0[$3]
-; O32-NEXT:    addiu $2, $2, 1
-; O32-NEXT:    sll $2, $2, 2
-; O32-NEXT:    sld.b $w0, $w0[$2]
-; O32-NEXT:    insert.w $w0[0], $5
-; O32-NEXT:    neg $2, $2
-; O32-NEXT:    sld.b $w0, $w0[$2]
+; O32-NEXT:    lsa $1, $2, $1, 3
+; O32-NEXT:    sw $5, 4($1)
 ; O32-NEXT:    jr $ra
-; O32-NEXT:    st.w $w0, 0($1)
+; O32-NEXT:    sw $4, 0($1)
 ;
 ; N32-LABEL: insert_v2i64_vidx:
 ; N32:       # %bb.0:
 ; N32-NEXT:    lui $1, %hi(%neg(%gp_rel(insert_v2i64_vidx)))
 ; N32-NEXT:    addu $1, $1, $25
 ; N32-NEXT:    addiu $1, $1, %lo(%neg(%gp_rel(insert_v2i64_vidx)))
 ; N32-NEXT:    lw $2, %got_disp(i32)($1)
 ; N32-NEXT:    lw $2, 0($2)
 ; N32-NEXT:    lw $1, %got_disp(v2i64)($1)
-; N32-NEXT:    ld.d $w0, 0($1)
-; N32-NEXT:    sll $2, $2, 3
-; N32-NEXT:    sld.b $w0, $w0[$2]
-; N32-NEXT:    insert.d $w0[0], $4
-; N32-NEXT:    neg $2, $2
-; N32-NEXT:    sld.b $w0, $w0[$2]
+; N32-NEXT:    lsa $1, $2, $1, 3
 ; N32-NEXT:    jr $ra
-; N32-NEXT:    st.d $w0, 0($1)
+; N32-NEXT:    sd $4, 0($1)
 ;
 ; N64-LABEL: insert_v2i64_vidx:
 ; N64:       # %bb.0:
 ; N64-NEXT:    lui $1, %hi(%neg(%gp_rel(insert_v2i64_vidx)))
 ; N64-NEXT:    daddu $1, $1, $25
 ; N64-NEXT:    daddiu $1, $1, %lo(%neg(%gp_rel(insert_v2i64_vidx)))
 ; N64-NEXT:    ld $2, %got_disp(i32)($1)
 ; N64-NEXT:    lwu $2, 0($2)
 ; N64-NEXT:    ld $1, %got_disp(v2i64)($1)
-; N64-NEXT:    ld.d $w0, 0($1)
-; N64-NEXT:    dsll $2, $2, 3
-; N64-NEXT:    sld.b $w0, $w0[$2]
-; N64-NEXT:    insert.d $w0[0], $4
-; N64-NEXT:    dneg $2, $2
-; N64-NEXT:    sld.b $w0, $w0[$2]
+; N64-NEXT:    dlsa $1, $2, $1, 3
 ; N64-NEXT:    jr $ra
-; N64-NEXT:    st.d $w0, 0($1)
+; N64-NEXT:    sd $4, 0($1)
   %1 = load <2 x i64>, ptr @v2i64
   %2 = load i32, ptr @i32
   %3 = insertelement <2 x i64> %1, i64 %a, i32 %2
   store <2 x i64> %3, ptr @v2i64
   ret void
 }
 
 ; TODO: What code should be emitted?

llvm/test/CodeGen/Mips/msa/basic_operations_float.ll

define void @insert_v4f32(float %a) nounwind {
 
   %1 = load <4 x float>, ptr @v4f32
   ; ALL-DAG: ld.w [[R1:\$w[0-9]+]],
 
   %2 = insertelement <4 x float> %1, float %a, i32 1
   ; float argument passed in $f12
   ; ALL-DAG: insve.w [[R1]][1], $w12[0]
 
-  store <4 x float> %2, ptr @v4f32
+  store volatile <4 x float> %2, ptr @v4f32
   ; ALL-DAG: st.w [[R1]]
 
   ret void
 }
 
 define void @insert_v2f64(double %a) nounwind {
   ; ALL-LABEL: insert_v2f64:
 
   %1 = load <2 x double>, ptr @v2f64
   ; ALL-DAG: ld.d [[R1:\$w[0-9]+]],
 
   %2 = insertelement <2 x double> %1, double %a, i32 1
   ; double argument passed in $f12
   ; ALL-DAG: insve.d [[R1]][1], $w12[0]
 
-  store <2 x double> %2, ptr @v2f64
+  store volatile <2 x double> %2, ptr @v2f64
   ; ALL-DAG: st.d [[R1]]
 
   ret void
 }
 
 define void @insert_v4f32_vidx(float %a) nounwind {
   ; ALL-LABEL: insert_v4f32_vidx:
 
define void @insert_v4f32_vidx(float %a) nounwind {
   %3 = insertelement <4 x float> %1, float %a, i32 %2
   ; float argument passed in $f12
   ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[PTR_I]], 2
   ; ALL-DAG: sld.b [[R1]], [[R1]][[[BIDX]]]
   ; ALL-DAG: insve.w [[R1]][0], $w12[0]
   ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
   ; ALL-DAG: sld.b [[R1]], [[R1]][[[NIDX]]]
 
-  store <4 x float> %3, ptr @v4f32
+  store volatile <4 x float> %3, ptr @v4f32
   ; ALL-DAG: st.w [[R1]]
 
   ret void
 }
 
 define void @insert_v2f64_vidx(double %a) nounwind {
   ; ALL-LABEL: insert_v2f64_vidx:
 
define void @insert_v2f64_vidx(double %a) nounwind {
   %3 = insertelement <2 x double> %1, double %a, i32 %2
   ; double argument passed in $f12
   ; ALL-DAG: sll [[BIDX:\$[0-9]+]], [[PTR_I]], 3
   ; ALL-DAG: sld.b [[R1]], [[R1]][[[BIDX]]]
   ; ALL-DAG: insve.d [[R1]][0], $w12[0]
   ; ALL-DAG: neg [[NIDX:\$[0-9]+]], [[BIDX]]
   ; ALL-DAG: sld.b [[R1]], [[R1]][[[NIDX]]]
 
-  store <2 x double> %3, ptr @v2f64
+  store volatile <2 x double> %3, ptr @v2f64
   ; ALL-DAG: st.d [[R1]]
 
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
 ; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
 
 ; FIXME: This codegen needs to be improved. These tests previously asserted
 ; type legalizing the i64 type on RV32.
 
 define <4 x i64> @insertelt_v4i64(<4 x i64> %a, i64 %y) {
 ; RV32-LABEL: insertelt_v4i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
 ; RV32-NEXT:    vslide1down.vx v10, v8, a0
 ; RV32-NEXT:    vslide1down.vx v10, v10, a1
 ; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
 ; RV32-NEXT:    vslideup.vi v8, v10, 3
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: insertelt_v4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
 ; RV64-NEXT:    vmv.s.x v10, a0
 ; RV64-NEXT:    vslideup.vi v8, v10, 3
 ; RV64-NEXT:    ret
   %b = insertelement <4 x i64> %a, i64 %y, i32 3
   ret <4 x i64> %b
 }
 
 define void @insertelt_v4i64_store(ptr %x, i64 %y) {
 ; RV32-LABEL: insertelt_v4i64_store:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
-; RV32-NEXT:    vle64.v v8, (a0)
-; RV32-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
-; RV32-NEXT:    vslide1down.vx v10, v8, a1
-; RV32-NEXT:    vslide1down.vx v10, v10, a2
-; RV32-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
-; RV32-NEXT:    vslideup.vi v8, v10, 3
-; RV32-NEXT:    vse64.v v8, (a0)
+; RV32-NEXT:    sw a2, 28(a0)
+; RV32-NEXT:    sw a1, 24(a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: insertelt_v4i64_store:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
-; RV64-NEXT:    vle64.v v8, (a0)
-; RV64-NEXT:    vmv.s.x v10, a1
-; RV64-NEXT:    vslideup.vi v8, v10, 3
-; RV64-NEXT:    vse64.v v8, (a0)
+; RV64-NEXT:    sd a1, 24(a0)
 ; RV64-NEXT:    ret
   %a = load <4 x i64>, ptr %x
   %b = insertelement <4 x i64> %a, i64 %y, i32 3
   store <4 x i64> %b, ptr %x
   ret void
 }
 
 ; This uses a non-power of 2 type so that it isn't an MVT.

 ; RV64-NEXT:    ret
   %b = insertelement <3 x i64> %a, i64 %y, i32 2
   ret <3 x i64> %b
 }
 
 define void @insertelt_v3i64_store(ptr %x, i64 %y) {
 ; RV32-LABEL: insertelt_v3i64_store:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 3, e64, m2, ta, ma
-; RV32-NEXT:    vle64.v v8, (a0)
-; RV32-NEXT:    vsetivli zero, 2, e32, m2, ta, ma
-; RV32-NEXT:    vslide1down.vx v10, v8, a1
-; RV32-NEXT:    vslide1down.vx v10, v10, a2
-; RV32-NEXT:    vsetivli zero, 3, e64, m2, tu, ma
-; RV32-NEXT:    vslideup.vi v8, v10, 2
-; RV32-NEXT:    vse64.v v8, (a0)
+; RV32-NEXT:    sw a2, 20(a0)
+; RV32-NEXT:    sw a1, 16(a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: insertelt_v3i64_store:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 3, e64, m2, ta, ma
-; RV64-NEXT:    vle64.v v8, (a0)
-; RV64-NEXT:    vmv.s.x v10, a1
-; RV64-NEXT:    vsetvli zero, zero, e64, m2, tu, ma
-; RV64-NEXT:    vslideup.vi v8, v10, 2
-; RV64-NEXT:    vse64.v v8, (a0)
+; RV64-NEXT:    sd a1, 16(a0)
 ; RV64-NEXT:    ret
   %a = load <3 x i64>, ptr %x, align 8
   %b = insertelement <3 x i64> %a, i64 %y, i32 2
   store <3 x i64> %b, ptr %x
   ret void
 }
 
 define <16 x i8> @insertelt_v16i8(<16 x i8> %a, i8 %y) {
 ; CHECK-LABEL: insertelt_v16i8:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 15, e8, m1, tu, ma
 ; CHECK-NEXT:    vmv.s.x v9, a0
 ; CHECK-NEXT:    vslideup.vi v8, v9, 14
 ; CHECK-NEXT:    ret
   %b = insertelement <16 x i8> %a, i8 %y, i32 14
   ret <16 x i8> %b
 }
 
 define void @insertelt_v16i8_store(ptr %x, i8 %y) {
 ; CHECK-LABEL: insertelt_v16i8_store:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT:    vle8.v v8, (a0)
-; CHECK-NEXT:    vmv.s.x v9, a1
-; CHECK-NEXT:    vsetivli zero, 15, e8, m1, tu, ma
-; CHECK-NEXT:    vslideup.vi v8, v9, 14
-; CHECK-NEXT:    vsetivli zero, 16, e8, m1, ta, ma
-; CHECK-NEXT:    vse8.v v8, (a0)
+; CHECK-NEXT:    sb a1, 14(a0)
 ; CHECK-NEXT:    ret
   %a = load <16 x i8>, ptr %x
   %b = insertelement <16 x i8> %a, i8 %y, i32 14
   store <16 x i8> %b, ptr %x
   ret void
 }
 
 define <32 x i16> @insertelt_v32i16(<32 x i16> %a, i16 %y, i32 %idx) {

 ; RV64-NEXT:    ret
   %b = insertelement <32 x i16> %a, i16 %y, i32 %idx
   ret <32 x i16> %b
 }
 
 define void @insertelt_v32i16_store(ptr %x, i16 %y, i32 %idx) {
 ; RV32-LABEL: insertelt_v32i16_store:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    li a3, 32
-; RV32-NEXT:    vsetvli zero, a3, e16, m4, ta, ma
-; RV32-NEXT:    vle16.v v8, (a0)
-; RV32-NEXT:    vmv.s.x v12, a1
-; RV32-NEXT:    addi a1, a2, 1
-; RV32-NEXT:    vsetvli zero, a1, e16, m4, tu, ma
-; RV32-NEXT:    vslideup.vx v8, v12, a2
-; RV32-NEXT:    vsetvli zero, a3, e16, m4, ta, ma
-; RV32-NEXT:    vse16.v v8, (a0)
+; RV32-NEXT:    slli a2, a2, 1
+; RV32-NEXT:    add a0, a0, a2
+; RV32-NEXT:    sh a1, 0(a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: insertelt_v32i16_store:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    li a3, 32
-; RV64-NEXT:    vsetvli zero, a3, e16, m4, ta, ma
-; RV64-NEXT:    vle16.v v8, (a0)
-; RV64-NEXT:    vmv.s.x v12, a1
 ; RV64-NEXT:    slli a2, a2, 32
-; RV64-NEXT:    srli a2, a2, 32
-; RV64-NEXT:    addi a1, a2, 1
-; RV64-NEXT:    vsetvli zero, a1, e16, m4, tu, ma
-; RV64-NEXT:    vslideup.vx v8, v12, a2
-; RV64-NEXT:    vsetvli zero, a3, e16, m4, ta, ma
-; RV64-NEXT:    vse16.v v8, (a0)
+; RV64-NEXT:    srli a2, a2, 31
+; RV64-NEXT:    add a0, a0, a2
+; RV64-NEXT:    sh a1, 0(a0)
 ; RV64-NEXT:    ret
   %a = load <32 x i16>, ptr %x
   %b = insertelement <32 x i16> %a, i16 %y, i32 %idx
   store <32 x i16> %b, ptr %x
   ret void
 }
 
 define <8 x float> @insertelt_v8f32(<8 x float> %a, float %y, i32 %idx) {

 ; RV64-NEXT:    ret
   %b = insertelement <8 x float> %a, float %y, i32 %idx
   ret <8 x float> %b
 }
 
 define void @insertelt_v8f32_store(ptr %x, float %y, i32 %idx) {
 ; RV32-LABEL: insertelt_v8f32_store:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT:    vle32.v v8, (a0)
-; RV32-NEXT:    vfmv.s.f v10, fa0
-; RV32-NEXT:    addi a2, a1, 1
-; RV32-NEXT:    vsetvli zero, a2, e32, m2, tu, ma
-; RV32-NEXT:    vslideup.vx v8, v10, a1
-; RV32-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; RV32-NEXT:    vse32.v v8, (a0)
+; RV32-NEXT:    slli a1, a1, 2
+; RV32-NEXT:    add a0, a0, a1
+; RV32-NEXT:    fsw fa0, 0(a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: insertelt_v8f32_store:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; RV64-NEXT:    vle32.v v8, (a0)
-; RV64-NEXT:    vfmv.s.f v10, fa0
 ; RV64-NEXT:    slli a1, a1, 32
-; RV64-NEXT:    srli a1, a1, 32
-; RV64-NEXT:    addi a2, a1, 1
-; RV64-NEXT:    vsetvli zero, a2, e32, m2, tu, ma
-; RV64-NEXT:    vslideup.vx v8, v10, a1
-; RV64-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; RV64-NEXT:    vse32.v v8, (a0)
+; RV64-NEXT:    srli a1, a1, 30
+; RV64-NEXT:    add a0, a0, a1
+; RV64-NEXT:    fsw fa0, 0(a0)
 ; RV64-NEXT:    ret
   %a = load <8 x float>, ptr %x
   %b = insertelement <8 x float> %a, float %y, i32 %idx
   store <8 x float> %b, ptr %x
   ret void
 }
 
 define <8 x i64> @insertelt_v8i64_0(<8 x i64> %a, ptr %x) {
 ; CHECK-LABEL: insertelt_v8i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a0, -1
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m4, tu, ma
 ; CHECK-NEXT:    vmv.s.x v8, a0
 ; CHECK-NEXT:    ret
   %b = insertelement <8 x i64> %a, i64 -1, i32 0
   ret <8 x i64> %b
 }
 
 define void @insertelt_v8i64_0_store(ptr %x) {
-; CHECK-LABEL: insertelt_v8i64_0_store:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
-; CHECK-NEXT:    vle64.v v8, (a0)
-; CHECK-NEXT:    li a1, -1
-; CHECK-NEXT:    vsetvli zero, zero, e64, m4, tu, ma
-; CHECK-NEXT:    vmv.s.x v8, a1
-; CHECK-NEXT:    vse64.v v8, (a0)
-; CHECK-NEXT:    ret
+; RV32-LABEL: insertelt_v8i64_0_store:
+; RV32:       # %bb.0:
+; RV32-NEXT:    li a1, -1
+; RV32-NEXT:    sw a1, 4(a0)
+; RV32-NEXT:    sw a1, 0(a0)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: insertelt_v8i64_0_store:
+; RV64:       # %bb.0:
+; RV64-NEXT:    li a1, -1
+; RV64-NEXT:    sd a1, 0(a0)
+; RV64-NEXT:    ret
   %a = load <8 x i64>, ptr %x
   %b = insertelement <8 x i64> %a, i64 -1, i32 0
   store <8 x i64> %b, ptr %x
   ret void
 }
 
 define <8 x i64> @insertelt_v8i64(<8 x i64> %a, i32 %idx) {
 ; RV32-LABEL: insertelt_v8i64:

 ; RV64-NEXT:    ret
   %b = insertelement <8 x i64> %a, i64 -1, i32 %idx
   ret <8 x i64> %b
 }
 
 define void @insertelt_v8i64_store(ptr %x, i32 %idx) {
 ; RV32-LABEL: insertelt_v8i64_store:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT:    vle64.v v8, (a0)
-; RV32-NEXT:    li a2, -1
-; RV32-NEXT:    vmv.s.x v12, a2
-; RV32-NEXT:    addi a2, a1, 1
-; RV32-NEXT:    vsetvli zero, a2, e64, m4, tu, ma
-; RV32-NEXT:    vslideup.vx v8, v12, a1
-; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT:    vse64.v v8, (a0)
+; RV32-NEXT:    slli a1, a1, 3
+; RV32-NEXT:    add a0, a0, a1
+; RV32-NEXT:    li a1, -1
+; RV32-NEXT:    sw a1, 4(a0)
+; RV32-NEXT:    sw a1, 0(a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: insertelt_v8i64_store:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
-; RV64-NEXT:    vle64.v v8, (a0)
-; RV64-NEXT:    li a2, -1
-; RV64-NEXT:    vmv.s.x v12, a2
 ; RV64-NEXT:    slli a1, a1, 32
-; RV64-NEXT:    srli a1, a1, 32
-; RV64-NEXT:    addi a2, a1, 1
-; RV64-NEXT:    vsetvli zero, a2, e64, m4, tu, ma
-; RV64-NEXT:    vslideup.vx v8, v12, a1
-; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
+; RV64-NEXT:    srli a1, a1, 29
+; RV64-NEXT:    add a0, a0, a1
+; RV64-NEXT:    li a1, -1
+; RV64-NEXT:    sd a1, 0(a0)
 ; RV64-NEXT:    ret
   %a = load <8 x i64>, ptr %x
   %b = insertelement <8 x i64> %a, i64 -1, i32 %idx
   store <8 x i64> %b, ptr %x
   ret void
 }
 
 define <8 x i64> @insertelt_c6_v8i64_0(<8 x i64> %a, ptr %x) {
 ; CHECK-LABEL: insertelt_c6_v8i64_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a0, 6
 ; CHECK-NEXT:    vsetivli zero, 8, e64, m4, tu, ma
 ; CHECK-NEXT:    vmv.s.x v8, a0
 ; CHECK-NEXT:    ret
   %b = insertelement <8 x i64> %a, i64 6, i32 0
   ret <8 x i64> %b
 }
 
 define void @insertelt_c6_v8i64_0_store(ptr %x) {
-; CHECK-LABEL: insertelt_c6_v8i64_0_store:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
-; CHECK-NEXT:    vle64.v v8, (a0)
-; CHECK-NEXT:    li a1, 6
-; CHECK-NEXT:    vsetvli zero, zero, e64, m4, tu, ma
-; CHECK-NEXT:    vmv.s.x v8, a1
-; CHECK-NEXT:    vse64.v v8, (a0)
-; CHECK-NEXT:    ret
+; RV32-LABEL: insertelt_c6_v8i64_0_store:
+; RV32:       # %bb.0:
+; RV32-NEXT:    sw zero, 4(a0)
+; RV32-NEXT:    li a1, 6
+; RV32-NEXT:    sw a1, 0(a0)
+; RV32-NEXT:    ret
+;
+; RV64-LABEL: insertelt_c6_v8i64_0_store:
+; RV64:       # %bb.0:
+; RV64-NEXT:    li a1, 6
+; RV64-NEXT:    sd a1, 0(a0)
+; RV64-NEXT:    ret
   %a = load <8 x i64>, ptr %x
   %b = insertelement <8 x i64> %a, i64 6, i32 0
   store <8 x i64> %b, ptr %x
   ret void
 }
 
 define <8 x i64> @insertelt_c6_v8i64(<8 x i64> %a, i32 %idx) {
 ; RV32-LABEL: insertelt_c6_v8i64:

 ; RV64-NEXT:    ret
   %b = insertelement <8 x i64> %a, i64 6, i32 %idx
   ret <8 x i64> %b
 }
 
 define void @insertelt_c6_v8i64_store(ptr %x, i32 %idx) {
 ; RV32-LABEL: insertelt_c6_v8i64_store:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT:    vle64.v v8, (a0)
-; RV32-NEXT:    li a2, 6
-; RV32-NEXT:    vmv.s.x v12, a2
-; RV32-NEXT:    addi a2, a1, 1
-; RV32-NEXT:    vsetvli zero, a2, e64, m4, tu, ma
-; RV32-NEXT:    vslideup.vx v8, v12, a1
-; RV32-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
-; RV32-NEXT:    vse64.v v8, (a0)
+; RV32-NEXT:    slli a1, a1, 3
+; RV32-NEXT:    add a0, a0, a1
+; RV32-NEXT:    sw zero, 4(a0)
+; RV32-NEXT:    li a1, 6
+; RV32-NEXT:    sw a1, 0(a0)
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: insertelt_c6_v8i64_store:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
-; RV64-NEXT:    vle64.v v8, (a0)
-; RV64-NEXT:    li a2, 6
-; RV64-NEXT:    vmv.s.x v12, a2
 ; RV64-NEXT:    slli a1, a1, 32
-; RV64-NEXT:    srli a1, a1, 32
-; RV64-NEXT:    addi a2, a1, 1
-; RV64-NEXT:    vsetvli zero, a2, e64, m4, tu, ma
-; RV64-NEXT:    vslideup.vx v8, v12, a1
-; RV64-NEXT:    vsetivli zero, 8, e64, m4, ta, ma
-; RV64-NEXT:    vse64.v v8, (a0)
+; RV64-NEXT:    srli a1, a1, 29
+; RV64-NEXT:    add a0, a0, a1
+; RV64-NEXT:    li a1, 6
+; RV64-NEXT:    sd a1, 0(a0)
 ; RV64-NEXT:    ret
   %a = load <8 x i64>, ptr %x
   %b = insertelement <8 x i64> %a, i64 6, i32 %idx
   store <8 x i64> %b, ptr %x
   ret void
 }
 
 ; Test that using a insertelement at element 0 by a later operation doesn't

llvm/test/CodeGen/X86/pr47874.ll

 }
 
 define void @c(ptr %arg, ptr %arg1, i32 %arg2) {
 ; SSE2-LABEL: c:
 ; SSE2:       ## %bb.0: ## %bb
 ; SSE2-NEXT:    testl %edx, %edx
 ; SSE2-NEXT:    jle LBB2_3
 ; SSE2-NEXT:  ## %bb.1: ## %bb4
-; SSE2-NEXT:    movd %edx, %xmm0
-; SSE2-NEXT:    movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
+; SSE2-NEXT:    movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
 ; SSE2-NEXT:    movl %edx, %eax
 ; SSE2-NEXT:    .p2align 4, 0x90
 ; SSE2-NEXT:  LBB2_2: ## %bb8
 ; SSE2-NEXT:    ## =>This Inner Loop Header: Depth=1
 ; SSE2-NEXT:    ## InlineAsm Start
 ; SSE2-NEXT:    ## InlineAsm End
-; SSE2-NEXT:    movaps (%rdi), %xmm0
-; SSE2-NEXT:    addss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload
-; SSE2-NEXT:    movaps %xmm0, (%rdi)
+; SSE2-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-NEXT:    addss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 4-byte Folded Reload
+; SSE2-NEXT:    movss %xmm0, (%rdi)
 ; SSE2-NEXT:    addq $16, %rdi
 ; SSE2-NEXT:    decq %rax
 ; SSE2-NEXT:    jne LBB2_2
 ; SSE2-NEXT:  LBB2_3: ## %bb7
 ; SSE2-NEXT:    retq
 ;
 ; AVX-LABEL: c:
 ; AVX:       ## %bb.0: ## %bb
 ; AVX-NEXT:    testl %edx, %edx
 ; AVX-NEXT:    jle LBB2_3
 ; AVX-NEXT:  ## %bb.1: ## %bb4
-; AVX-NEXT:    vmovd %edx, %xmm0
-; AVX-NEXT:    vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
+; AVX-NEXT:    movl %edx, {{[-0-9]+}}(%r{{[sb]}}p) ## 4-byte Spill
 ; AVX-NEXT:    movl %edx, %eax
 ; AVX-NEXT:    .p2align 4, 0x90
 ; AVX-NEXT:  LBB2_2: ## %bb8
 ; AVX-NEXT:    ## =>This Inner Loop Header: Depth=1
 ; AVX-NEXT:    ## InlineAsm Start
 ; AVX-NEXT:    ## InlineAsm End
-; AVX-NEXT:    vmovaps (%rdi), %xmm0
-; AVX-NEXT:    vaddss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 ## 16-byte Folded Reload
-; AVX-NEXT:    vmovaps %xmm0, (%rdi)
+; AVX-NEXT:    vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 4-byte Reload
+; AVX-NEXT:    ## xmm0 = mem[0],zero,zero,zero
+; AVX-NEXT:    vaddss (%rdi), %xmm0, %xmm0
+; AVX-NEXT:    vmovss %xmm0, (%rdi)
 ; AVX-NEXT:    addq $16, %rdi
 ; AVX-NEXT:    decq %rax
 ; AVX-NEXT:    jne LBB2_2
 ; AVX-NEXT:  LBB2_3: ## %bb7
 ; AVX-NEXT:    retq
 bb:
   %i = icmp sgt i32 %arg2, 0
   br i1 %i, label %bb4, label %bb7

 }
 
 define void @d(ptr %arg, ptr %arg1, i64 %arg2) {
 ; SSE2-LABEL: d:
 ; SSE2:       ## %bb.0: ## %bb
 ; SSE2-NEXT:    testq %rdx, %rdx
 ; SSE2-NEXT:    jle LBB3_3
 ; SSE2-NEXT:  ## %bb.1: ## %bb3
-; SSE2-NEXT:    movq %rdx, %xmm0
-; SSE2-NEXT:    movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
+; SSE2-NEXT:    movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
 ; SSE2-NEXT:    .p2align 4, 0x90
 ; SSE2-NEXT:  LBB3_2: ## %bb6
 ; SSE2-NEXT:    ## =>This Inner Loop Header: Depth=1
 ; SSE2-NEXT:    ## InlineAsm Start
 ; SSE2-NEXT:    ## InlineAsm End
-; SSE2-NEXT:    movapd (%rdi), %xmm0
-; SSE2-NEXT:    addsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 16-byte Folded Reload
-; SSE2-NEXT:    movapd %xmm0, (%rdi)
+; SSE2-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; SSE2-NEXT:    addsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 8-byte Folded Reload
+; SSE2-NEXT:    movsd %xmm0, (%rdi)
 ; SSE2-NEXT:    addq $16, %rdi
 ; SSE2-NEXT:    decq %rdx
 ; SSE2-NEXT:    jne LBB3_2
 ; SSE2-NEXT:  LBB3_3: ## %bb5
 ; SSE2-NEXT:    retq
 ;
 ; AVX-LABEL: d:
 ; AVX:       ## %bb.0: ## %bb
 ; AVX-NEXT:    testq %rdx, %rdx
 ; AVX-NEXT:    jle LBB3_3
 ; AVX-NEXT:  ## %bb.1: ## %bb3
-; AVX-NEXT:    vmovq %rdx, %xmm0
-; AVX-NEXT:    vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) ## 16-byte Spill
+; AVX-NEXT:    movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) ## 8-byte Spill
 ; AVX-NEXT:    .p2align 4, 0x90
 ; AVX-NEXT:  LBB3_2: ## %bb6
 ; AVX-NEXT:    ## =>This Inner Loop Header: Depth=1
 ; AVX-NEXT:    ## InlineAsm Start
 ; AVX-NEXT:    ## InlineAsm End
-; AVX-NEXT:    vmovapd (%rdi), %xmm0
-; AVX-NEXT:    vaddsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm0 ## 16-byte Folded Reload
-; AVX-NEXT:    vmovapd %xmm0, (%rdi)
+; AVX-NEXT:    vmovsd {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 ## 8-byte Reload
+; AVX-NEXT:    ## xmm0 = mem[0],zero
+; AVX-NEXT:    vaddsd (%rdi), %xmm0, %xmm0
+; AVX-NEXT:    vmovsd %xmm0, (%rdi)
 ; AVX-NEXT:    addq $16, %rdi
 ; AVX-NEXT:    decq %rdx
 ; AVX-NEXT:    jne LBB3_2
 ; AVX-NEXT:  LBB3_3: ## %bb5
 ; AVX-NEXT:    retq
 bb:
   %i = icmp sgt i64 %arg2, 0
   br i1 %i, label %bb3, label %bb5

llvm/test/CodeGen/X86/pr59980.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-apple-macosx10.15 | FileCheck %s
 
 %0 = type <{ half }>
 %1 = type <{ <16 x half> }>
 
 define void @foo(ptr %0, ptr %1, ptr %2) #0 {
 ; CHECK-LABEL: foo:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    pushq %rbp
-; CHECK-NEXT:    movq %rsp, %rbp
-; CHECK-NEXT:    andq $-32, %rsp
-; CHECK-NEXT:    subq $64, %rsp
 ; CHECK-NEXT:    movl (%rdx), %eax
-; CHECK-NEXT:    andl $15, %eax
 ; CHECK-NEXT:    vpinsrw $0, (%rdi), %xmm0, %xmm0
-; CHECK-NEXT:    vmovups (%rsi), %ymm1
-; CHECK-NEXT:    vmovaps %ymm1, (%rsp)
-; CHECK-NEXT:    vpextrw $0, %xmm0, (%rsp,%rax,2)
-; CHECK-NEXT:    vmovaps (%rsp), %ymm0
-; CHECK-NEXT:    vmovups %ymm0, (%rsi)
-; CHECK-NEXT:    movq %rbp, %rsp
-; CHECK-NEXT:    popq %rbp
-; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    vpextrw $0, %xmm0, (%rsi,%rax,2)
 ; CHECK-NEXT:    retq
   %4 = bitcast ptr %2 to ptr
   %5 = load i64, ptr %4, align 8
   %6 = getelementptr inbounds %0, ptr %0, i64 0, i32 0
   %7 = load half, ptr %6, align 2
   %8 = getelementptr inbounds %1, ptr %1, i64 0, i32 0
   %9 = load <16 x half>, ptr %8, align 16
   %10 = trunc i64 %5 to i32
   %11 = insertelement <16 x half> %9, half %7, i32 %10
   store <16 x half> %11, ptr %8, align 16
   ret void
 }
 
 attributes #0 = { nounwind "target-features"="+f16c" }

llvm/test/CodeGen/X86/vec_insert-mmx.ll

 @g0 = external global i16
 @g1 = external global <4 x i16>
 
 ; PR2562
 define void @t3() {
 ; X86-LABEL: t3:
 ; X86:       ## %bb.0:
 ; X86-NEXT:    movl L_g0$non_lazy_ptr, %eax
+; X86-NEXT:    movzwl (%eax), %eax
 ; X86-NEXT:    movl L_g1$non_lazy_ptr, %ecx
-; X86-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero
-; X86-NEXT:    pinsrw $0, (%eax), %xmm0
-; X86-NEXT:    movq %xmm0, (%ecx)
+; X86-NEXT:    movw %ax, (%ecx)
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: t3:
 ; X64:       ## %bb.0:
 ; X64-NEXT:    movq _g0@GOTPCREL(%rip), %rax
+; X64-NEXT:    movzwl (%rax), %eax
 ; X64-NEXT:    movq _g1@GOTPCREL(%rip), %rcx
-; X64-NEXT:    movq {{.*#+}} xmm0 = mem[0],zero
-; X64-NEXT:    pinsrw $0, (%rax), %xmm0
-; X64-NEXT:    movq %xmm0, (%rcx)
+; X64-NEXT:    movw %ax, (%rcx)
 ; X64-NEXT:    retq
   load i16, ptr @g0
   load <4 x i16>, ptr @g1
   insertelement <4 x i16> %2, i16 %1, i32 0
   store <4 x i16> %3, ptr @g1
   ret void
 }