[AArch64] Complete the list of extensions supported by .arch and .arch_extension

[mstorsjo]

Summary

This brings the list of extensions supported here up to date
with what is supported by current git versions of binutils.

Also add a comment to AArch64TargetParser to remind people to
consider adding new ones to the list supported in assembly.

In the case of the "rdma" extension, there's a slight surprise:
LLVM knows of the extension under the name "rdm", while binutils
has it named "rdma". However, binutils appears to accept any
abbreviated prefix of an arch extension, so it does accept the
form "rdm" too even if it formally considers it called "rdma".

Thus common use of it might end up calling it "rdm" and having
that working with binutils. (If such cases are common I guess
we could consider adding "rdm" as an alias here too?)

[tmatheson]

I would suggest using "rdm" which is:

• consistent with both clang and AArch64TargetParser
• consistent with the actual feature name in the Arm ARM, which is FEAT_RDM. "ARMv8.1-RDMA" is the legacy feature name.
• accepted by binutils

Otherwise LGTM

[mstorsjo]

In D151981#4390386, @tmatheson wrote:

I would suggest using "rdm" which is:

• consistent with both clang and AArch64TargetParser
• consistent with the actual feature name in the Arm ARM, which is FEAT_RDM. "ARMv8.1-RDMA" is the legacy feature name.
• accepted by binutils

Ok, those are good arguments. Although, as binutils still documents it as rdma, do you think it'd make sense to support both namings for it? I'd hate to not support the naming that they advertise. I guess it'd be as simple as having two entries in this table.

[tmatheson]

In D151981#4390422, @mstorsjo wrote:

Ok, those are good arguments. Although, as binutils still documents it as rdma, do you think it'd make sense to support both namings for it? I'd hate to not support the naming that they advertise. I guess it'd be as simple as having two entries in this table.

Yeah, if it's as simple as that then I can't see any harm in accepting both.

Function Multi Versioning also uses "+rdm".

[mstorsjo]

Updated to support both "rdm" and "rdma"; added a comment in the table about it, and testing both forms in the test file.

[tmatheson]

LGTM, thanks.

[DavidSpickett]

Thanks for the update!

If anyone has time to make the backend use the list from the target parser (or the backend itself) that would be even better.

[mstorsjo]

In D151981#4390609, @DavidSpickett wrote:

If anyone has time to make the backend use the list from the target parser (or the backend itself) that would be even better.

Yep, that'd be ideal. The target parser has a much larger set of extensions though, and some of them use different spellings between binutils and llvm, so for the .arch and .arch_extension cases in asm, I've aligned with binutils here - e.g. compnum doesn't seem to have a direct counterpart in targetparser (or is that fcma?).

[mstorsjo]

Added a release note

llvm/docs/ReleaseNotes.rst

 ----------------------------------------
 
 Changes to the AArch64 Backend
 ------------------------------
 
 * Added Assembly Support for the 2022 A-profile extensions FEAT_GCS (Guarded
   Control Stacks), FEAT_CHK (Check Feature Status), and FEAT_ATS1A.
 * Support for preserve_all calling convention is added.
+* Added support for missing arch extensions in the assembly directives
+  ``.arch <level>+<ext>`` and ``.arch_extension``.
 
 Changes to the AMDGPU Backend
 -----------------------------
 * More fine-grained synchronization around barriers for newer architectures
   (gfx90a+, gfx10+). The AMDGPU backend now omits previously automatically
   generated waitcnt instructions before barriers, allowing for more precise
   control. Users must now use memory fences to implement fine-grained
   synchronization strategies around barriers. Refer to `AMDGPU memory model

llvm/include/llvm/TargetParser/AArch64TargetParser.h

CPUFeatures CPUFeature;      // Function Multi Versioning (FMV) bitfield value
                                // set in __aarch64_cpu_features
   StringRef DependentFeatures; // FMV enabled features string,
                                // e.g. "+dotprod,+fp-armv8,+neon"
   unsigned FmvPriority;        // FMV feature priority
   static constexpr unsigned MaxFMVPriority =
       1000; // Maximum priority for FMV feature
 };
 
+// NOTE: If adding a new extension here, consider adding it to ExtensionMap
+// in AArch64AsmParser too, if supported as an extension name by binutils.
 // clang-format off
 inline constexpr ExtensionInfo Extensions[] = {
     {"aes", AArch64::AEK_AES, "+aes", "-aes", FEAT_AES, "+fp-armv8,+neon", 150},
     {"b16b16", AArch64::AEK_B16B16, "+b16b16", "-b16b16", FEAT_MAX, "", 0},
     {"bf16", AArch64::AEK_BF16, "+bf16", "-bf16", FEAT_BF16, "+bf16", 280},
     {"brbe", AArch64::AEK_BRBE, "+brbe", "-brbe", FEAT_MAX, "", 0},
     {"bti", AArch64::AEK_NONE, {}, {}, FEAT_BTI, "+bti", 510},
     {"crc", AArch64::AEK_CRC, "+crc", "-crc", FEAT_CRC, "+crc", 110},

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

const FeatureBitset Features;
     {"mec", {AArch64::FeatureMEC}},
     {"the", {AArch64::FeatureTHE}},
     {"d128", {AArch64::FeatureD128}},
     {"lse128", {AArch64::FeatureLSE128}},
     {"ite", {AArch64::FeatureITE}},
     {"cssc", {AArch64::FeatureCSSC}},
     {"rcpc3", {AArch64::FeatureRCPC3}},
     {"gcs", {AArch64::FeatureGCS}},
-    // FIXME: Unsupported extensions
-    {"lor", {}},
-    {"rdma", {}},
-    {"profile", {}},
+    {"bf16", {AArch64::FeatureBF16}},
+    {"compnum", {AArch64::FeatureComplxNum}},
+    {"dotprod", {AArch64::FeatureDotProd}},
+    {"f32mm", {AArch64::FeatureMatMulFP32}},
+    {"f64mm", {AArch64::FeatureMatMulFP64}},
+    {"fp16", {AArch64::FeatureFullFP16}},
+    {"fp16fml", {AArch64::FeatureFP16FML}},
+    {"i8mm", {AArch64::FeatureMatMulInt8}},
+    {"lor", {AArch64::FeatureLOR}},
+    {"profile", {AArch64::FeatureSPE}},
+    // "rdma" is the name documented by binutils for the feature, but
+    // binutils also accepts incomplete prefixes of features, so "rdm"
+    // works too. Support both spellings here.
+    {"rdm", {AArch64::FeatureRDM}},
+    {"rdma", {AArch64::FeatureRDM}},
+    {"sb", {AArch64::FeatureSB}},
+    {"ssbs", {AArch64::FeatureSSBS}},
+    {"tme", {AArch64::FeatureTME}},
 };
 
 static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {
   if (FBS[AArch64::HasV8_0aOps])
     Str += "ARMv8a";
   if (FBS[AArch64::HasV8_1aOps])
     Str += "ARMv8.1a";
   else if (FBS[AArch64::HasV8_2aOps])

llvm/test/MC/AArch64/directive-arch_extension.s

 
 .arch_extension cssc
 umax x0, x1, x2
 // CHECK: umax x0, x1, x2
 
 .arch_extension gcs
 gcspushm x0
 // CHECK: gcspushm x0
+
+.arch_extension bf16
+bfdot v0.2s, v0.4h, v0.4h
+// CHECK: bfdot v0.2s, v0.4h, v0.4h
+
+.arch_extension compnum
+fcmla v1.2d, v2.2d, v3.2d, #0
+// CHECK: fcmla v1.2d, v2.2d, v3.2d, #0
+
+.arch_extension dotprod
+udot v0.4s, v0.16b, v0.16b
+// CHECK: udot v0.4s, v0.16b, v0.16b
+
+.arch_extension f32mm
+fmmla z0.s, z1.s, z2.s
+// CHECK: fmmla z0.s, z1.s, z2.s
+
+.arch_extension f64mm
+fmmla z0.d, z1.d, z2.d
+// CHECK: fmmla z0.d, z1.d, z2.d
+
+.arch_extension fp16
+fadd v0.8h, v0.8h, v0.8h
+// CHECK: fadd v0.8h, v0.8h, v0.8h
+
+.arch_extension fp16fml
+fmlal v0.2s, v1.2h, v2.2h
+// CHECK: fmlal v0.2s, v1.2h, v2.2h
+
+.arch_extension i8mm
+usdot v0.4s, v0.16b, v0.16b
+// CHECK: usdot v0.4s, v0.16b, v0.16b
+
+.arch_extension lor
+stllr x0, [x0]
+// CHECK: stllr x0, [x0]
+
+.arch_extension profile
+msr PMBLIMITR_EL1, x0
+// CHECK: msr PMBLIMITR_EL1, x0
+
+.arch_extension rdm
+.arch_extension rdma
+sqrdmlah v0.8h, v0.8h, v0.8h
+// CHECK: sqrdmlah v0.8h, v0.8h, v0.8h
+
+.arch_extension sb
+sb
+// CHECK: sb
+
+.arch_extension ssbs
+msr SSBS, #1
+// CHECK: msr SSBS, #1
+
+.arch_extension tme
+tstart x0
+// CHECK: tstart x0