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Differential D149710

[RISCV] Add sifive-x280 processor with all of its extensions
ClosedPublic

Authored by michaelmaitland on May 2 2023, 5:44 PM.

Details

Reviewers
craig.topper
kito-cheng
reames
• pcwang-thead
Commits
rG839469436afc: [RISCV] Add sifive-x280 processor with all of its extensions
rGa11dfd0fe6b1: [RISCV] Add sifive-x280 processor with all of its extensions
rG55e196e7718c: [RISCV] Add sifive-x280 processor with all of its extensions
Summary

Add sifive-x280 processor that uses the SiFive7 scheduler model.

Diff Detail

Unit TestsFailed

TimeTest
870 msx64 debian > Clang.Misc::target-invalid-cpu-note.c

Event Timeline

michaelmaitland created this revision.May 2 2023, 5:44 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 2 2023, 5:44 PM
Herald added subscribers: jobnoorman, luke, VincentWu and 28 others. · View Herald Transcript
michaelmaitland requested review of this revision.May 2 2023, 5:44 PM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptMay 2 2023, 5:44 PM
Herald added subscribers: llvm-commits, cfe-commits, eopXD, MaskRay. · View Herald Transcript
michaelmaitland mentioned this in D149495: [RISCV] Add support for V extension in SiFive7.May 2 2023, 5:45 PM
michaelmaitland added a child revision: D149495: [RISCV] Add support for V extension in SiFive7.May 2 2023, 5:52 PM
michaelmaitland removed a child revision: D149495: [RISCV] Add support for V extension in SiFive7.
michaelmaitland added a child revision: D149496: [RISCV][llvm-mca] Add mca tests for riscv lmul instruments.
reames accepted this revision.May 2 2023, 6:10 PM

Mechanically, this looks fine.

This revision is now accepted and ready to land.May 2 2023, 6:10 PM
craig.topper accepted this revision.May 2 2023, 9:16 PM

LGTM

Harbormaster completed remote builds in B229577: Diff 518922.May 3 2023, 9:32 AM
This revision was landed with ongoing or failed builds.May 5 2023, 7:55 AM
Closed by commit rG55e196e7718c: [RISCV] Add sifive-x280 processor with all of its extensions (authored by michaelmaitland). · Explain Why
This revision was automatically updated to reflect the committed changes.
michaelmaitland added a commit: rG55e196e7718c: [RISCV] Add sifive-x280 processor with all of its extensions.
michaelmaitland added a comment.May 5 2023, 8:19 AM

I had to revert this commit because it failed tests that did not fail during build through phabricator nor local check-all.

michaelmaitland added a reverting change: rGd6bd4ea35437: Revert "[RISCV] Add sifive-x280 processor with all of its extensions".May 5 2023, 8:20 AM
michaelmaitland added a commit: rGa11dfd0fe6b1: [RISCV] Add sifive-x280 processor with all of its extensions.May 5 2023, 8:48 AM
michaelmaitland added a reverting change: rG6e7ca6839def: Revert "[RISCV] Add sifive-x280 processor with all of its extensions".May 5 2023, 9:03 AM
michaelmaitland added a commit: rG839469436afc: [RISCV] Add sifive-x280 processor with all of its extensions.May 5 2023, 10:02 AM

Revision Contents

PathSize
clang/
test/
Driver/
14 lines
llvm/
docs/
1 line
lib/
Target/
RISCV/
16 lines

Diff 518922

clang/test/Driver/riscv-cpus.c

Show First 20 Lines • Show All 161 Lines • ▼ Show 20 Lines
// MTUNE-E31-MCPU-E76: "-target-cpu" "sifive-e31" // MTUNE-E31-MCPU-E76: "-target-cpu" "sifive-e31"
// MTUNE-E31-MCPU-E76-NOT: "-target-feature" "+f" // MTUNE-E31-MCPU-E76-NOT: "-target-feature" "+f"
// MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+m" // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+m"
// MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+a" // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+a"
// MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+c" // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+c"
// MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei" // MTUNE-E31-MCPU-E76-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
// MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76" // MTUNE-E31-MCPU-E76-SAME: "-tune-cpu" "sifive-e76"
// mcpu with default march include experimental extensions
// RUN: %clang -target riscv64 -### -c %s 2>&1 -menable-experimental-extensions -mcpu=sifive-x280 | FileCheck -check-prefix=MCPU-SIFIVE-X280 %s
// MCPU-SIFIVE-X280: "-nostdsysteminc" "-target-cpu" "sifive-x280"
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+c" "-target-feature" "+v"
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei"
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zfh"
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+experimental-zvfh"
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl128b"
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl256b" "-target-feature" "+zvl32b"
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature" "+zvl64b"
// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
// Check failed cases // Check failed cases
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s
// FAIL-MCPU-NAME: error: unsupported argument 'generic-rv321' to option '-mcpu=' // FAIL-MCPU-NAME: error: unsupported argument 'generic-rv321' to option '-mcpu='
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv32 -march=rv64i | FileCheck -check-prefix=MISMATCH-ARCH %s
// MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64 // MISMATCH-ARCH: cpu 'generic-rv32' does not support rv64

llvm/docs/ReleaseNotes.rst

Show First 20 Lines • Show All 165 Lines • ▼ Show 20 Lines* Changed the ShadowCallStack register from ``x18`` (``s2``) to ``x3``
(``gp``). Note this breaks the existing non-standard ABI for ShadowCallStack (``gp``). Note this breaks the existing non-standard ABI for ShadowCallStack
on RISC-V, but conforms with the new "platform register" defined in the on RISC-V, but conforms with the new "platform register" defined in the
RISC-V psABI (for more details see the RISC-V psABI (for more details see the
`psABI discussion <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/370>`_). `psABI discussion <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/370>`_).
* Added support for Zfa extension version 0.2. * Added support for Zfa extension version 0.2.
* Updated support experimental vector crypto extensions to version 0.5.1 of * Updated support experimental vector crypto extensions to version 0.5.1 of
the specification. the specification.
* Removed N extension (User-Level Interrupts) CSR names in the assembler. * Removed N extension (User-Level Interrupts) CSR names in the assembler.
* Add sifive-x280 processor.
Changes to the WebAssembly Backend Changes to the WebAssembly Backend
---------------------------------- ----------------------------------
* ... * ...
Changes to the Windows Target Changes to the Windows Target
----------------------------- -----------------------------
▲ Show 20 Lines • Show All 126 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVProcessors.td

Show First 20 Lines • Show All 160 Lines • ▼ Show 20 Linesdef SIFIVE_U74 : RISCVProcessorModel<"sifive-u74",
FeatureStdExtZifencei, FeatureStdExtZifencei,
FeatureStdExtM, FeatureStdExtM,
FeatureStdExtA, FeatureStdExtA,
FeatureStdExtF, FeatureStdExtF,
FeatureStdExtD, FeatureStdExtD,
FeatureStdExtC], FeatureStdExtC],
[TuneSiFive7]>; [TuneSiFive7]>;
def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", SiFive7Model,
[Feature64Bit,
FeatureStdExtZifencei,
FeatureStdExtM,
FeatureStdExtA,
FeatureStdExtF,
FeatureStdExtD,
FeatureStdExtC,
FeatureStdExtV,
FeatureStdExtZvl512b,
FeatureStdExtZfh,
FeatureStdExtZvfh,
FeatureStdExtZba,
FeatureStdExtZbb],
[TuneSiFive7]>;
def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base", def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
SyntacoreSCR1Model, SyntacoreSCR1Model,
[Feature32Bit, [Feature32Bit,
FeatureStdExtZicsr, FeatureStdExtZicsr,
FeatureStdExtZifencei, FeatureStdExtZifencei,
FeatureStdExtC], FeatureStdExtC],
[TuneNoDefaultUnroll]>; [TuneNoDefaultUnroll]>;
def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max", def SYNTACORE_SCR1_MAX : RISCVProcessorModel<"syntacore-scr1-max",
SyntacoreSCR1Model, SyntacoreSCR1Model,
[Feature32Bit, [Feature32Bit,
FeatureStdExtZicsr, FeatureStdExtZicsr,
FeatureStdExtZifencei, FeatureStdExtZifencei,
FeatureStdExtM, FeatureStdExtM,
FeatureStdExtC], FeatureStdExtC],
[TuneNoDefaultUnroll]>; [TuneNoDefaultUnroll]>;