[RISCV] Remove the uret instruction.

[craig.topper]

Summary

This was part of the N extension which did not make it into
version 1.12 of the privilege specification.

[jrtc27]

llvm/test/CodeGen/RISCV/interrupt-attr.ll

1057

Can you fix this whitespace up while you're touching this?

[craig.topper]

Fix whitespace in test

[craig.topper]

Just realized there's some clang code that needs to go away too.

llvm/lib/Target/RISCV/RISCVISelLowering.h

 //===-- RISCVISelLowering.h - RISC-V DAG Lowering Interface -----*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 
 namespace llvm {
 class RISCVSubtarget;
 struct RISCVRegisterInfo;
 namespace RISCVISD {
 enum NodeType : unsigned {
   FIRST_NUMBER = ISD::BUILTIN_OP_END,
   RET_GLUE,
-  URET_GLUE,
   SRET_GLUE,
   MRET_GLUE,
   CALL,
   /// Select with condition operator - This selects between a true value and
   /// a false value (ops #3 and #4) based on the boolean result of comparing
   /// the lhs and rhs (ops #0 and #1) of a conditional expression with the
   /// condition code in op #2, a XLenVT constant from the ISD::CondCode enum.
   /// The lhs and rhs are XLenVT integers. The true and false values can be

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISC-V DAG Lowering Implementation  -------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (Func.hasFnAttribute("interrupt")) {
     if (!Func.getReturnType()->isVoidTy())
       report_fatal_error(
           "Functions with the interrupt attribute must have void return type!");
 
     MachineFunction &MF = DAG.getMachineFunction();
     StringRef Kind =
       MF.getFunction().getFnAttribute("interrupt").getValueAsString();
 
-    if (Kind == "user")
-      RetOpc = RISCVISD::URET_GLUE;
-    else if (Kind == "supervisor")
+    if (Kind == "supervisor")
       RetOpc = RISCVISD::SRET_GLUE;
     else
       RetOpc = RISCVISD::MRET_GLUE;
   }
 
   return DAG.getNode(RetOpc, DL, MVT::Other, RetOps);
 }
 

 #define NODE_NAME_CASE(NODE)                                                   \
   case RISCVISD::NODE:                                                         \
     return "RISCVISD::" #NODE;
   // clang-format off
   switch ((RISCVISD::NodeType)Opcode) {
   case RISCVISD::FIRST_NUMBER:
     break;
   NODE_NAME_CASE(RET_GLUE)
-  NODE_NAME_CASE(URET_GLUE)
   NODE_NAME_CASE(SRET_GLUE)
   NODE_NAME_CASE(MRET_GLUE)
   NODE_NAME_CASE(CALL)
   NODE_NAME_CASE(SELECT_CC)
   NODE_NAME_CASE(BR_CC)
   NODE_NAME_CASE(BuildPairF64)
   NODE_NAME_CASE(SplitF64)
   NODE_NAME_CASE(TAIL)

llvm/lib/Target/RISCV/RISCVInstrInfo.td

def callseq_end   : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd,
                            [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
 
 // Target-dependent nodes.
 def riscv_call      : SDNode<"RISCVISD::CALL", SDT_RISCVCall,
                              [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
                               SDNPVariadic]>;
 def riscv_ret_glue  : SDNode<"RISCVISD::RET_GLUE", SDTNone,
                              [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
-def riscv_uret_glue : SDNode<"RISCVISD::URET_GLUE", SDTNone,
-                             [SDNPHasChain, SDNPOptInGlue]>;
 def riscv_sret_glue : SDNode<"RISCVISD::SRET_GLUE", SDTNone,
                              [SDNPHasChain, SDNPOptInGlue]>;
 def riscv_mret_glue : SDNode<"RISCVISD::MRET_GLUE", SDTNone,
                              [SDNPHasChain, SDNPOptInGlue]>;
 def riscv_selectcc  : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC>;
 def riscv_brcc      : SDNode<"RISCVISD::BR_CC", SDT_RISCVBrCC,
                              [SDNPHasChain]>;
 def riscv_tail      : SDNode<"RISCVISD::TAIL", SDT_RISCVCall,

 } // IsSignExtendingOpW = 1
 } // Predicates = [IsRV64]
 
 //===----------------------------------------------------------------------===//
 // Privileged instructions
 //===----------------------------------------------------------------------===//
 
 let isBarrier = 1, isReturn = 1, isTerminator = 1 in {
-def URET : Priv<"uret", 0b0000000>, Sched<[]> {
-  let rd = 0;
-  let rs1 = 0;
-  let rs2 = 0b00010;
-}
-
 def SRET : Priv<"sret", 0b0001000>, Sched<[]> {
   let rd = 0;
   let rs1 = 0;
   let rs2 = 0b00010;
 }
 
 def MRET : Priv<"mret", 0b0011000>, Sched<[]> {
   let rd = 0;

 def PseudoCALL : Pseudo<(outs), (ins call_symbol:$func), []>,
                  Sched<[WriteIALU, WriteJalr, ReadJalr]> {
   let AsmString = "call\t$func";
 }
 
 def : Pat<(riscv_call tglobaladdr:$func), (PseudoCALL tglobaladdr:$func)>;
 def : Pat<(riscv_call texternalsym:$func), (PseudoCALL texternalsym:$func)>;
 
-def : Pat<(riscv_uret_glue), (URET X0, X0)>;
 def : Pat<(riscv_sret_glue), (SRET X0, X0)>;
 def : Pat<(riscv_mret_glue), (MRET X0, X0)>;
 
 let isCall = 1, Defs = [X1] in
 def PseudoCALLIndirect : Pseudo<(outs), (ins GPRJALR:$rs1),
                                 [(riscv_call GPRJALR:$rs1)]>,
                          PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
 

llvm/test/CodeGen/RISCV/interrupt-attr.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32-unknown-elf -o - %s \
 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV32
 ; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f -o - %s \
 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV32-F
 ; RUN: llc -mtriple riscv32-unknown-elf -mattr=+f,+d -o - %s \
 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV32-FD
 ;
 ; RUN: llc -mtriple riscv64-unknown-elf -o - %s \
 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64
 ; RUN: llc -mtriple riscv64-unknown-elf -mattr=+f -o - %s \
 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64-F
 ; RUN: llc -mtriple riscv64-unknown-elf -mattr=+f,+d -o - %s \
 ; RUN: 2>&1 | FileCheck %s -check-prefix CHECK -check-prefix CHECK-RV64-FD
 
 ;
-; Checking for special return instructions (uret, sret, mret).
+; Checking for special return instructions (sret, mret).
 ;
-define void @foo_user() #0 {
-; CHECK-LABEL: foo_user:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    uret
-  ret void
-}
-
-define void @foo_supervisor() #1 {
+define void @foo_supervisor() #0 {
 ; CHECK-LABEL: foo_supervisor:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    sret
   ret void
 }
 
-define void @foo_machine() #2 {
+define void @foo_machine() #1 {
 ; CHECK-LABEL: foo_machine:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    mret
   ret void
 }
 
 ;
 ; Checking all Caller saved registers (arguments and temps)
 ; and FP registers are all saved when the handler calls another function.
 ;
 ; extern int otherfoo();
 ;
 ; __attribute__((interrupt)) void foo_with_call() {
 ;   otherfoo();
 ; }
 ;
 
 declare i32 @otherfoo(...)
-define void @foo_with_call() #2 {
+define void @foo_with_call() #1 {
 ;
 ; CHECK-RV32-LABEL: foo_with_call:
 ; CHECK-RV32:       # %bb.0:
 ; CHECK-RV32-NEXT:    addi sp, sp, -64
 ; CHECK-RV32-NEXT:    sw ra, 60(sp) # 4-byte Folded Spill
 ; CHECK-RV32-NEXT:    sw t0, 56(sp) # 4-byte Folded Spill
 ; CHECK-RV32-NEXT:    sw t1, 52(sp) # 4-byte Folded Spill
 ; CHECK-RV32-NEXT:    sw t2, 48(sp) # 4-byte Folded Spill

 ; CHECK-RV64-FD-NEXT:    mret
   %call = call i32 @otherfoo()
   ret void
 }
 
 ;
 ; Additionally check frame pointer and return address are properly saved.
 ;
-define void @foo_fp_with_call() #3 {
+define void @foo_fp_with_call() #2 {
 ;
 ; CHECK-RV32-LABEL: foo_fp_with_call:
 ; CHECK-RV32:       # %bb.0:
 ; CHECK-RV32-NEXT:    addi sp, sp, -80
 ; CHECK-RV32-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill
 ; CHECK-RV32-NEXT:    sw t0, 72(sp) # 4-byte Folded Spill
 ; CHECK-RV32-NEXT:    sw t1, 68(sp) # 4-byte Folded Spill
 ; CHECK-RV32-NEXT:    sw t2, 64(sp) # 4-byte Folded Spill

 ; CHECK-RV64-FD-NEXT:    fld fs10, 16(sp) # 8-byte Folded Reload
 ; CHECK-RV64-FD-NEXT:    fld fs11, 8(sp) # 8-byte Folded Reload
 ; CHECK-RV64-FD-NEXT:    addi sp, sp, 400
 ; CHECK-RV64-FD-NEXT:    mret
   %call = call i32 @otherfoo()
   ret void
 }
 
-attributes #0 = { nounwind "interrupt"="user" }
-attributes #1 = { nounwind "interrupt"="supervisor" }
-attributes #2 = { nounwind  "interrupt"="machine" }
-attributes #3 = { nounwind "interrupt"="machine" "frame-pointer"="all" }
+attributes #0 = { nounwind "interrupt"="supervisor" }
+attributes #1 = { nounwind  "interrupt"="machine" }
+attributes #2 = { nounwind "interrupt"="machine" "frame-pointer"="all" }

llvm/test/MC/RISCV/priv-valid.s

 # RUN: llvm-mc %s -triple=riscv32 -mattr=+svinval -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
 # RUN: llvm-mc %s -triple=riscv64 -mattr=+svinval -riscv-no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+svinval < %s \
 # RUN:     | llvm-objdump --mattr=+svinval -M no-aliases -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 # RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+svinval < %s \
 # RUN:     | llvm-objdump --mattr=+svinval -M no-aliases -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 
-# CHECK-INST: uret
-# CHECK: encoding: [0x73,0x00,0x20,0x00]
-uret
-
 # CHECK-INST: sret
 # CHECK: encoding: [0x73,0x00,0x20,0x10]
 sret
 
 # CHECK-INST: mret
 # CHECK: encoding: [0x73,0x00,0x20,0x30]
 mret