[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)

[liaolucy]

Summary

The result of sub + setcc is 0 or 1 for all bits.
The sra instruction get the same result.

[craig.topper]

This is not correct for the add cases

A correct transform would be

fold (add (setcc x, 0, setlt), -1) -> (xor (sra x, xlen - 1), -1)
fold (add (setcc 0, x, setgt), -1) -> (xor (sra x, xlen - 1), -1)

But I'm not sure that's profitable.

Alive2: https://alive2.llvm.org/ce/z/JQRoji

[liaolucy]

delete the add cases

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9138

You can delete the setgt code. It will never exist in that form. Prior to LegalizeDAG we keep constants on the RHS of setcc. LegalizeDAG won't have any reason to change it.

The only case that should have 0 on the left hand side is (setcc 0, x, setlt) which we get from legalizing (setcc x, 0, setgt).

[liaolucy]

Address comments, thanks

[craig.topper]

LGTM with that comment addressed.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

9135

Move VT and DL inside the ifs since they aren't used until getNode.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static SDValue combineSubOfBoolean(SDNode *N, SelectionDAG &DAG) {
   return DAG.getNode(ISD::ADD, DL, VT, NewLHS, NewRHS);
 }
 
 static SDValue performSUBCombine(SDNode *N, SelectionDAG &DAG,
                                  const RISCVSubtarget &Subtarget) {
   if (SDValue V = combineSubOfBoolean(N, DAG))
     return V;
 
-  // fold (sub x, (select lhs, rhs, cc, 0, y)) ->
-  //      (select lhs, rhs, cc, x, (sub x, y))
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
+  // fold (sub 0, (setcc x, 0, setlt)) -> (sra x, xlen - 1)
+  if (isNullConstant(N0) && N1.getOpcode() == ISD::SETCC && N1.hasOneUse() &&
+      isNullConstant(N1.getOperand(1))) {
+    ISD::CondCode CCVal = cast<CondCodeSDNode>(N1.getOperand(2))->get();
+    if (CCVal == ISD::SETLT) {
+      EVT VT = N->getValueType(0);
+      SDLoc DL(N);
+      unsigned ShAmt = N0.getValueSizeInBits() - 1;
+      return DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0),
+                         DAG.getConstant(ShAmt, DL, VT));
+    }
+  }
+
+  // fold (sub x, (select lhs, rhs, cc, 0, y)) ->
+  //      (select lhs, rhs, cc, x, (sub x, y))
   return combineSelectAndUse(N, N1, N0, DAG, /*AllOnes*/ false, Subtarget);
 }
 
 // Apply DeMorgan's law to (and/or (xor X, 1), (xor Y, 1)) if X and Y are 0/1.
 // Legalizing setcc can introduce xors like this. Doing this transform reduces
 // the number of xors and may allow the xor to fold into a branch condition.
 static SDValue combineDeMorganOfBoolean(SDNode *N, SelectionDAG &DAG) {
   SDValue N0 = N->getOperand(0);

llvm/test/CodeGen/RISCV/alu64.ll

 ; RV32I-NEXT:    j .LBB11_3
 ; RV32I-NEXT:  .LBB11_2:
 ; RV32I-NEXT:    sll a1, a1, a2
 ; RV32I-NEXT:    not a2, a2
 ; RV32I-NEXT:    srli a0, a0, 1
 ; RV32I-NEXT:    srl a0, a0, a2
 ; RV32I-NEXT:    or a1, a1, a0
 ; RV32I-NEXT:  .LBB11_3:
-; RV32I-NEXT:    slti a0, a4, 0
-; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    srai a0, a4, 31
 ; RV32I-NEXT:    and a0, a0, a3
 ; RV32I-NEXT:    ret
   %1 = shl i64 %a, %b
   ret i64 %1
 }
 
 define i64 @slt(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: slt:

 ; RV32I-NEXT:    j .LBB15_3
 ; RV32I-NEXT:  .LBB15_2:
 ; RV32I-NEXT:    srl a0, a0, a2
 ; RV32I-NEXT:    not a2, a2
 ; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    sll a1, a1, a2
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:  .LBB15_3:
-; RV32I-NEXT:    slti a1, a4, 0
-; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    srai a1, a4, 31
 ; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    ret
   %1 = lshr i64 %a, %b
   ret i64 %1
 }
 
 define i64 @sra(i64 %a, i64 %b) nounwind {
 ; RV64I-LABEL: sra:

llvm/test/CodeGen/RISCV/bittest.ll

 ; Make sure we use (andi (srl X, Y), 1) or bext.
 define i1 @bittest_constant_by_var_shr_i64(i64 %b) nounwind {
 ; RV32-LABEL: bittest_constant_by_var_shr_i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    lui a1, 301408
 ; RV32-NEXT:    addi a1, a1, 722
 ; RV32-NEXT:    srl a1, a1, a0
 ; RV32-NEXT:    addi a0, a0, -32
-; RV32-NEXT:    slti a0, a0, 0
+; RV32-NEXT:    srli a0, a0, 31
 ; RV32-NEXT:    and a0, a0, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64I-LABEL: bittest_constant_by_var_shr_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 301408
 ; RV64I-NEXT:    addiw a1, a1, 722
 ; RV64I-NEXT:    srl a0, a1, a0

 ; Make sure we use (andi (srl X, Y), 1) or bext.
 define i1 @bittest_constant_by_var_shl_i64(i64 %b) nounwind {
 ; RV32-LABEL: bittest_constant_by_var_shl_i64:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    lui a1, 301408
 ; RV32-NEXT:    addi a1, a1, 722
 ; RV32-NEXT:    srl a1, a1, a0
 ; RV32-NEXT:    addi a0, a0, -32
-; RV32-NEXT:    slti a0, a0, 0
+; RV32-NEXT:    srli a0, a0, 31
 ; RV32-NEXT:    and a0, a0, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64I-LABEL: bittest_constant_by_var_shl_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 301408
 ; RV64I-NEXT:    addiw a1, a1, 722
 ; RV64I-NEXT:    srl a0, a1, a0

llvm/test/CodeGen/RISCV/fpclamptosat.ll

 ; RV32IF-NEXT:    bgez a1, .LBB27_9
 ; RV32IF-NEXT:  # %bb.1: # %entry
 ; RV32IF-NEXT:    bgeu a0, a4, .LBB27_10
 ; RV32IF-NEXT:  .LBB27_2: # %entry
 ; RV32IF-NEXT:    beqz a1, .LBB27_4
 ; RV32IF-NEXT:  .LBB27_3: # %entry
 ; RV32IF-NEXT:    mv a0, a3
 ; RV32IF-NEXT:  .LBB27_4: # %entry
-; RV32IF-NEXT:    slti a3, a1, 0
-; RV32IF-NEXT:    neg a3, a3
+; RV32IF-NEXT:    srai a3, a1, 31
 ; RV32IF-NEXT:    and a1, a3, a1
 ; RV32IF-NEXT:    mv a3, a0
 ; RV32IF-NEXT:    bltz a1, .LBB27_11
 ; RV32IF-NEXT:  # %bb.5: # %entry
 ; RV32IF-NEXT:    bgeu a2, a0, .LBB27_12
 ; RV32IF-NEXT:  .LBB27_6: # %entry
 ; RV32IF-NEXT:    li a2, -1
 ; RV32IF-NEXT:    beq a1, a2, .LBB27_8

 ; RV32-NEXT:    bgez a1, .LBB33_9
 ; RV32-NEXT:  # %bb.1: # %entry
 ; RV32-NEXT:    bgeu a0, a4, .LBB33_10
 ; RV32-NEXT:  .LBB33_2: # %entry
 ; RV32-NEXT:    beqz a1, .LBB33_4
 ; RV32-NEXT:  .LBB33_3: # %entry
 ; RV32-NEXT:    mv a0, a3
 ; RV32-NEXT:  .LBB33_4: # %entry
-; RV32-NEXT:    slti a3, a1, 0
-; RV32-NEXT:    neg a3, a3
+; RV32-NEXT:    srai a3, a1, 31
 ; RV32-NEXT:    and a1, a3, a1
 ; RV32-NEXT:    mv a3, a0
 ; RV32-NEXT:    bltz a1, .LBB33_11
 ; RV32-NEXT:  # %bb.5: # %entry
 ; RV32-NEXT:    bgeu a2, a0, .LBB33_12
 ; RV32-NEXT:  .LBB33_6: # %entry
 ; RV32-NEXT:    li a2, -1
 ; RV32-NEXT:    beq a1, a2, .LBB33_8

 ; RV64IF-NEXT:    bgez a1, .LBB45_9
 ; RV64IF-NEXT:  # %bb.1: # %entry
 ; RV64IF-NEXT:    bgeu a0, a4, .LBB45_10
 ; RV64IF-NEXT:  .LBB45_2: # %entry
 ; RV64IF-NEXT:    beqz a1, .LBB45_4
 ; RV64IF-NEXT:  .LBB45_3: # %entry
 ; RV64IF-NEXT:    mv a0, a3
 ; RV64IF-NEXT:  .LBB45_4: # %entry
-; RV64IF-NEXT:    slti a3, a1, 0
-; RV64IF-NEXT:    neg a3, a3
+; RV64IF-NEXT:    srai a3, a1, 63
 ; RV64IF-NEXT:    and a1, a3, a1
 ; RV64IF-NEXT:    slli a4, a2, 63
 ; RV64IF-NEXT:    mv a3, a0
 ; RV64IF-NEXT:    bltz a1, .LBB45_11
 ; RV64IF-NEXT:  # %bb.5: # %entry
 ; RV64IF-NEXT:    bgeu a4, a0, .LBB45_12
 ; RV64IF-NEXT:  .LBB45_6: # %entry
 ; RV64IF-NEXT:    beq a1, a2, .LBB45_8

 ; RV64-NEXT:    bgez a1, .LBB51_9
 ; RV64-NEXT:  # %bb.1: # %entry
 ; RV64-NEXT:    bgeu a0, a4, .LBB51_10
 ; RV64-NEXT:  .LBB51_2: # %entry
 ; RV64-NEXT:    beqz a1, .LBB51_4
 ; RV64-NEXT:  .LBB51_3: # %entry
 ; RV64-NEXT:    mv a0, a3
 ; RV64-NEXT:  .LBB51_4: # %entry
-; RV64-NEXT:    slti a3, a1, 0
-; RV64-NEXT:    neg a3, a3
+; RV64-NEXT:    srai a3, a1, 63
 ; RV64-NEXT:    and a1, a3, a1
 ; RV64-NEXT:    slli a4, a2, 63
 ; RV64-NEXT:    mv a3, a0
 ; RV64-NEXT:    bltz a1, .LBB51_11
 ; RV64-NEXT:  # %bb.5: # %entry
 ; RV64-NEXT:    bgeu a4, a0, .LBB51_12
 ; RV64-NEXT:  .LBB51_6: # %entry
 ; RV64-NEXT:    beq a1, a2, .LBB51_8

llvm/test/CodeGen/RISCV/rotl-rotr.ll

; RV64XTHEADBB-NEXT:    ret
   %c = shl i32 %x, %z
   %d = or i32 %b, %c
   ret i32 %d
 }
 
 define i64 @rotl_64(i64 %x, i64 %y) nounwind {
 ; RV32I-LABEL: rotl_64:
 ; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a5, a2, -32
 ; RV32I-NEXT:    sll a4, a0, a2
-; RV32I-NEXT:    addi a3, a2, -32
-; RV32I-NEXT:    slti a5, a3, 0
-; RV32I-NEXT:    neg a5, a5
-; RV32I-NEXT:    bltz a3, .LBB2_2
+; RV32I-NEXT:    bltz a5, .LBB2_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a3, a4
 ; RV32I-NEXT:    j .LBB2_3
 ; RV32I-NEXT:  .LBB2_2:
 ; RV32I-NEXT:    sll a3, a1, a2
 ; RV32I-NEXT:    not a6, a2
 ; RV32I-NEXT:    srli a7, a0, 1
 ; RV32I-NEXT:    srl a6, a7, a6
 ; RV32I-NEXT:    or a3, a3, a6
 ; RV32I-NEXT:  .LBB2_3:
+; RV32I-NEXT:    srai a5, a5, 31
 ; RV32I-NEXT:    and a4, a5, a4
 ; RV32I-NEXT:    neg a7, a2
 ; RV32I-NEXT:    li a5, 32
-; RV32I-NEXT:    sub a6, a5, a2
-; RV32I-NEXT:    srl a5, a1, a7
-; RV32I-NEXT:    bltz a6, .LBB2_5
+; RV32I-NEXT:    sub a5, a5, a2
+; RV32I-NEXT:    srl a6, a1, a7
+; RV32I-NEXT:    bltz a5, .LBB2_5
 ; RV32I-NEXT:  # %bb.4:
-; RV32I-NEXT:    mv a0, a5
+; RV32I-NEXT:    mv a0, a6
 ; RV32I-NEXT:    j .LBB2_6
 ; RV32I-NEXT:  .LBB2_5:
 ; RV32I-NEXT:    srl a0, a0, a7
 ; RV32I-NEXT:    li a7, 64
 ; RV32I-NEXT:    sub a2, a7, a2
 ; RV32I-NEXT:    not a2, a2
 ; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    sll a1, a1, a2
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:  .LBB2_6:
-; RV32I-NEXT:    slti a1, a6, 0
-; RV32I-NEXT:    neg a1, a1
-; RV32I-NEXT:    and a1, a1, a5
+; RV32I-NEXT:    srai a5, a5, 31
+; RV32I-NEXT:    and a1, a5, a6
 ; RV32I-NEXT:    or a1, a3, a1
 ; RV32I-NEXT:    or a0, a4, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: rotl_64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    negw a2, a1
 ; RV64I-NEXT:    sll a1, a0, a1
 ; RV64I-NEXT:    srl a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: rotl_64:
 ; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    addi a5, a2, -32
 ; RV32ZBB-NEXT:    sll a4, a0, a2
-; RV32ZBB-NEXT:    addi a3, a2, -32
-; RV32ZBB-NEXT:    slti a5, a3, 0
-; RV32ZBB-NEXT:    neg a5, a5
-; RV32ZBB-NEXT:    bltz a3, .LBB2_2
+; RV32ZBB-NEXT:    bltz a5, .LBB2_2
 ; RV32ZBB-NEXT:  # %bb.1:
 ; RV32ZBB-NEXT:    mv a3, a4
 ; RV32ZBB-NEXT:    j .LBB2_3
 ; RV32ZBB-NEXT:  .LBB2_2:
 ; RV32ZBB-NEXT:    sll a3, a1, a2
 ; RV32ZBB-NEXT:    not a6, a2
 ; RV32ZBB-NEXT:    srli a7, a0, 1
 ; RV32ZBB-NEXT:    srl a6, a7, a6
 ; RV32ZBB-NEXT:    or a3, a3, a6
 ; RV32ZBB-NEXT:  .LBB2_3:
+; RV32ZBB-NEXT:    srai a5, a5, 31
 ; RV32ZBB-NEXT:    and a4, a5, a4
 ; RV32ZBB-NEXT:    neg a7, a2
 ; RV32ZBB-NEXT:    li a5, 32
-; RV32ZBB-NEXT:    sub a6, a5, a2
-; RV32ZBB-NEXT:    srl a5, a1, a7
-; RV32ZBB-NEXT:    bltz a6, .LBB2_5
+; RV32ZBB-NEXT:    sub a5, a5, a2
+; RV32ZBB-NEXT:    srl a6, a1, a7
+; RV32ZBB-NEXT:    bltz a5, .LBB2_5
 ; RV32ZBB-NEXT:  # %bb.4:
-; RV32ZBB-NEXT:    mv a0, a5
+; RV32ZBB-NEXT:    mv a0, a6
 ; RV32ZBB-NEXT:    j .LBB2_6
 ; RV32ZBB-NEXT:  .LBB2_5:
 ; RV32ZBB-NEXT:    srl a0, a0, a7
 ; RV32ZBB-NEXT:    li a7, 64
 ; RV32ZBB-NEXT:    sub a2, a7, a2
 ; RV32ZBB-NEXT:    not a2, a2
 ; RV32ZBB-NEXT:    slli a1, a1, 1
 ; RV32ZBB-NEXT:    sll a1, a1, a2
 ; RV32ZBB-NEXT:    or a0, a0, a1
 ; RV32ZBB-NEXT:  .LBB2_6:
-; RV32ZBB-NEXT:    slti a1, a6, 0
-; RV32ZBB-NEXT:    neg a1, a1
-; RV32ZBB-NEXT:    and a1, a1, a5
+; RV32ZBB-NEXT:    srai a5, a5, 31
+; RV32ZBB-NEXT:    and a1, a5, a6
 ; RV32ZBB-NEXT:    or a1, a3, a1
 ; RV32ZBB-NEXT:    or a0, a4, a0
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rotl_64:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    rol a0, a0, a1
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV32XTHEADBB-LABEL: rotl_64:
 ; RV32XTHEADBB:       # %bb.0:
+; RV32XTHEADBB-NEXT:    addi a5, a2, -32
 ; RV32XTHEADBB-NEXT:    sll a4, a0, a2
-; RV32XTHEADBB-NEXT:    addi a3, a2, -32
-; RV32XTHEADBB-NEXT:    slti a5, a3, 0
-; RV32XTHEADBB-NEXT:    neg a5, a5
-; RV32XTHEADBB-NEXT:    bltz a3, .LBB2_2
+; RV32XTHEADBB-NEXT:    bltz a5, .LBB2_2
 ; RV32XTHEADBB-NEXT:  # %bb.1:
 ; RV32XTHEADBB-NEXT:    mv a3, a4
 ; RV32XTHEADBB-NEXT:    j .LBB2_3
 ; RV32XTHEADBB-NEXT:  .LBB2_2:
 ; RV32XTHEADBB-NEXT:    sll a3, a1, a2
 ; RV32XTHEADBB-NEXT:    not a6, a2
 ; RV32XTHEADBB-NEXT:    srli a7, a0, 1
 ; RV32XTHEADBB-NEXT:    srl a6, a7, a6
 ; RV32XTHEADBB-NEXT:    or a3, a3, a6
 ; RV32XTHEADBB-NEXT:  .LBB2_3:
+; RV32XTHEADBB-NEXT:    srai a5, a5, 31
 ; RV32XTHEADBB-NEXT:    and a4, a5, a4
 ; RV32XTHEADBB-NEXT:    neg a7, a2
 ; RV32XTHEADBB-NEXT:    li a5, 32
-; RV32XTHEADBB-NEXT:    sub a6, a5, a2
-; RV32XTHEADBB-NEXT:    srl a5, a1, a7
-; RV32XTHEADBB-NEXT:    bltz a6, .LBB2_5
+; RV32XTHEADBB-NEXT:    sub a5, a5, a2
+; RV32XTHEADBB-NEXT:    srl a6, a1, a7
+; RV32XTHEADBB-NEXT:    bltz a5, .LBB2_5
 ; RV32XTHEADBB-NEXT:  # %bb.4:
-; RV32XTHEADBB-NEXT:    mv a0, a5
+; RV32XTHEADBB-NEXT:    mv a0, a6
 ; RV32XTHEADBB-NEXT:    j .LBB2_6
 ; RV32XTHEADBB-NEXT:  .LBB2_5:
 ; RV32XTHEADBB-NEXT:    srl a0, a0, a7
 ; RV32XTHEADBB-NEXT:    li a7, 64
 ; RV32XTHEADBB-NEXT:    sub a2, a7, a2
 ; RV32XTHEADBB-NEXT:    not a2, a2
 ; RV32XTHEADBB-NEXT:    slli a1, a1, 1
 ; RV32XTHEADBB-NEXT:    sll a1, a1, a2
 ; RV32XTHEADBB-NEXT:    or a0, a0, a1
 ; RV32XTHEADBB-NEXT:  .LBB2_6:
-; RV32XTHEADBB-NEXT:    slti a1, a6, 0
-; RV32XTHEADBB-NEXT:    neg a1, a1
-; RV32XTHEADBB-NEXT:    and a1, a1, a5
+; RV32XTHEADBB-NEXT:    srai a5, a5, 31
+; RV32XTHEADBB-NEXT:    and a1, a5, a6
 ; RV32XTHEADBB-NEXT:    or a1, a3, a1
 ; RV32XTHEADBB-NEXT:    or a0, a4, a0
 ; RV32XTHEADBB-NEXT:    ret
 ;
 ; RV64XTHEADBB-LABEL: rotl_64:
 ; RV64XTHEADBB:       # %bb.0:
 ; RV64XTHEADBB-NEXT:    sll a2, a0, a1
 ; RV64XTHEADBB-NEXT:    neg a1, a1
 ; RV64XTHEADBB-NEXT:    srl a0, a0, a1
 ; RV64XTHEADBB-NEXT:    or a0, a2, a0
 ; RV64XTHEADBB-NEXT:    ret
   %z = sub i64 64, %y
   %b = shl i64 %x, %y
   %c = lshr i64 %x, %z
   %d = or i64 %b, %c
   ret i64 %d
 }
 
 define i64 @rotr_64(i64 %x, i64 %y) nounwind {
 ; RV32I-LABEL: rotr_64:
 ; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a5, a2, -32
 ; RV32I-NEXT:    srl a4, a1, a2
-; RV32I-NEXT:    addi a3, a2, -32
-; RV32I-NEXT:    slti a5, a3, 0
-; RV32I-NEXT:    neg a5, a5
-; RV32I-NEXT:    bltz a3, .LBB3_2
+; RV32I-NEXT:    bltz a5, .LBB3_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a3, a4
 ; RV32I-NEXT:    j .LBB3_3
 ; RV32I-NEXT:  .LBB3_2:
 ; RV32I-NEXT:    srl a3, a0, a2
 ; RV32I-NEXT:    not a6, a2
 ; RV32I-NEXT:    slli a7, a1, 1
 ; RV32I-NEXT:    sll a6, a7, a6
 ; RV32I-NEXT:    or a3, a3, a6
 ; RV32I-NEXT:  .LBB3_3:
+; RV32I-NEXT:    srai a5, a5, 31
 ; RV32I-NEXT:    and a4, a5, a4
 ; RV32I-NEXT:    neg a7, a2
 ; RV32I-NEXT:    li a5, 32
-; RV32I-NEXT:    sub a6, a5, a2
-; RV32I-NEXT:    sll a5, a0, a7
-; RV32I-NEXT:    bltz a6, .LBB3_5
+; RV32I-NEXT:    sub a5, a5, a2
+; RV32I-NEXT:    sll a6, a0, a7
+; RV32I-NEXT:    bltz a5, .LBB3_5
 ; RV32I-NEXT:  # %bb.4:
-; RV32I-NEXT:    mv a1, a5
+; RV32I-NEXT:    mv a1, a6
 ; RV32I-NEXT:    j .LBB3_6
 ; RV32I-NEXT:  .LBB3_5:
 ; RV32I-NEXT:    sll a1, a1, a7
 ; RV32I-NEXT:    li a7, 64
 ; RV32I-NEXT:    sub a2, a7, a2
 ; RV32I-NEXT:    not a2, a2
 ; RV32I-NEXT:    srli a0, a0, 1
 ; RV32I-NEXT:    srl a0, a0, a2
 ; RV32I-NEXT:    or a1, a1, a0
 ; RV32I-NEXT:  .LBB3_6:
-; RV32I-NEXT:    slti a0, a6, 0
-; RV32I-NEXT:    neg a0, a0
-; RV32I-NEXT:    and a0, a0, a5
+; RV32I-NEXT:    srai a5, a5, 31
+; RV32I-NEXT:    and a0, a5, a6
 ; RV32I-NEXT:    or a0, a3, a0
 ; RV32I-NEXT:    or a1, a4, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: rotr_64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    negw a2, a1
 ; RV64I-NEXT:    srl a1, a0, a1
 ; RV64I-NEXT:    sll a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: rotr_64:
 ; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    addi a5, a2, -32
 ; RV32ZBB-NEXT:    srl a4, a1, a2
-; RV32ZBB-NEXT:    addi a3, a2, -32
-; RV32ZBB-NEXT:    slti a5, a3, 0
-; RV32ZBB-NEXT:    neg a5, a5
-; RV32ZBB-NEXT:    bltz a3, .LBB3_2
+; RV32ZBB-NEXT:    bltz a5, .LBB3_2
 ; RV32ZBB-NEXT:  # %bb.1:
 ; RV32ZBB-NEXT:    mv a3, a4
 ; RV32ZBB-NEXT:    j .LBB3_3
 ; RV32ZBB-NEXT:  .LBB3_2:
 ; RV32ZBB-NEXT:    srl a3, a0, a2
 ; RV32ZBB-NEXT:    not a6, a2
 ; RV32ZBB-NEXT:    slli a7, a1, 1
 ; RV32ZBB-NEXT:    sll a6, a7, a6
 ; RV32ZBB-NEXT:    or a3, a3, a6
 ; RV32ZBB-NEXT:  .LBB3_3:
+; RV32ZBB-NEXT:    srai a5, a5, 31
 ; RV32ZBB-NEXT:    and a4, a5, a4
 ; RV32ZBB-NEXT:    neg a7, a2
 ; RV32ZBB-NEXT:    li a5, 32
-; RV32ZBB-NEXT:    sub a6, a5, a2
-; RV32ZBB-NEXT:    sll a5, a0, a7
-; RV32ZBB-NEXT:    bltz a6, .LBB3_5
+; RV32ZBB-NEXT:    sub a5, a5, a2
+; RV32ZBB-NEXT:    sll a6, a0, a7
+; RV32ZBB-NEXT:    bltz a5, .LBB3_5
 ; RV32ZBB-NEXT:  # %bb.4:
-; RV32ZBB-NEXT:    mv a1, a5
+; RV32ZBB-NEXT:    mv a1, a6
 ; RV32ZBB-NEXT:    j .LBB3_6
 ; RV32ZBB-NEXT:  .LBB3_5:
 ; RV32ZBB-NEXT:    sll a1, a1, a7
 ; RV32ZBB-NEXT:    li a7, 64
 ; RV32ZBB-NEXT:    sub a2, a7, a2
 ; RV32ZBB-NEXT:    not a2, a2
 ; RV32ZBB-NEXT:    srli a0, a0, 1
 ; RV32ZBB-NEXT:    srl a0, a0, a2
 ; RV32ZBB-NEXT:    or a1, a1, a0
 ; RV32ZBB-NEXT:  .LBB3_6:
-; RV32ZBB-NEXT:    slti a0, a6, 0
-; RV32ZBB-NEXT:    neg a0, a0
-; RV32ZBB-NEXT:    and a0, a0, a5
+; RV32ZBB-NEXT:    srai a5, a5, 31
+; RV32ZBB-NEXT:    and a0, a5, a6
 ; RV32ZBB-NEXT:    or a0, a3, a0
 ; RV32ZBB-NEXT:    or a1, a4, a1
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rotr_64:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    ror a0, a0, a1
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV32XTHEADBB-LABEL: rotr_64:
 ; RV32XTHEADBB:       # %bb.0:
+; RV32XTHEADBB-NEXT:    addi a5, a2, -32
 ; RV32XTHEADBB-NEXT:    srl a4, a1, a2
-; RV32XTHEADBB-NEXT:    addi a3, a2, -32
-; RV32XTHEADBB-NEXT:    slti a5, a3, 0
-; RV32XTHEADBB-NEXT:    neg a5, a5
-; RV32XTHEADBB-NEXT:    bltz a3, .LBB3_2
+; RV32XTHEADBB-NEXT:    bltz a5, .LBB3_2
 ; RV32XTHEADBB-NEXT:  # %bb.1:
 ; RV32XTHEADBB-NEXT:    mv a3, a4
 ; RV32XTHEADBB-NEXT:    j .LBB3_3
 ; RV32XTHEADBB-NEXT:  .LBB3_2:
 ; RV32XTHEADBB-NEXT:    srl a3, a0, a2
 ; RV32XTHEADBB-NEXT:    not a6, a2
 ; RV32XTHEADBB-NEXT:    slli a7, a1, 1
 ; RV32XTHEADBB-NEXT:    sll a6, a7, a6
 ; RV32XTHEADBB-NEXT:    or a3, a3, a6
 ; RV32XTHEADBB-NEXT:  .LBB3_3:
+; RV32XTHEADBB-NEXT:    srai a5, a5, 31
 ; RV32XTHEADBB-NEXT:    and a4, a5, a4
 ; RV32XTHEADBB-NEXT:    neg a7, a2
 ; RV32XTHEADBB-NEXT:    li a5, 32
-; RV32XTHEADBB-NEXT:    sub a6, a5, a2
-; RV32XTHEADBB-NEXT:    sll a5, a0, a7
-; RV32XTHEADBB-NEXT:    bltz a6, .LBB3_5
+; RV32XTHEADBB-NEXT:    sub a5, a5, a2
+; RV32XTHEADBB-NEXT:    sll a6, a0, a7
+; RV32XTHEADBB-NEXT:    bltz a5, .LBB3_5
 ; RV32XTHEADBB-NEXT:  # %bb.4:
-; RV32XTHEADBB-NEXT:    mv a1, a5
+; RV32XTHEADBB-NEXT:    mv a1, a6
 ; RV32XTHEADBB-NEXT:    j .LBB3_6
 ; RV32XTHEADBB-NEXT:  .LBB3_5:
 ; RV32XTHEADBB-NEXT:    sll a1, a1, a7
 ; RV32XTHEADBB-NEXT:    li a7, 64
 ; RV32XTHEADBB-NEXT:    sub a2, a7, a2
 ; RV32XTHEADBB-NEXT:    not a2, a2
 ; RV32XTHEADBB-NEXT:    srli a0, a0, 1
 ; RV32XTHEADBB-NEXT:    srl a0, a0, a2
 ; RV32XTHEADBB-NEXT:    or a1, a1, a0
 ; RV32XTHEADBB-NEXT:  .LBB3_6:
-; RV32XTHEADBB-NEXT:    slti a0, a6, 0
-; RV32XTHEADBB-NEXT:    neg a0, a0
-; RV32XTHEADBB-NEXT:    and a0, a0, a5
+; RV32XTHEADBB-NEXT:    srai a5, a5, 31
+; RV32XTHEADBB-NEXT:    and a0, a5, a6
 ; RV32XTHEADBB-NEXT:    or a0, a3, a0
 ; RV32XTHEADBB-NEXT:    or a1, a4, a1
 ; RV32XTHEADBB-NEXT:    ret
 ;
 ; RV64XTHEADBB-LABEL: rotr_64:
 ; RV64XTHEADBB:       # %bb.0:
 ; RV64XTHEADBB-NEXT:    srl a2, a0, a1
 ; RV64XTHEADBB-NEXT:    neg a1, a1

 ; RV32I-NEXT:    j .LBB10_3
 ; RV32I-NEXT:  .LBB10_2:
 ; RV32I-NEXT:    sll a3, a1, a2
 ; RV32I-NEXT:    not a6, a2
 ; RV32I-NEXT:    srli a7, a0, 1
 ; RV32I-NEXT:    srl a6, a7, a6
 ; RV32I-NEXT:    or a3, a3, a6
 ; RV32I-NEXT:  .LBB10_3:
-; RV32I-NEXT:    slti a5, a5, 0
-; RV32I-NEXT:    neg a5, a5
-; RV32I-NEXT:    and a4, a5, a4
-; RV32I-NEXT:    neg a6, a2
-; RV32I-NEXT:    srl a2, a1, a6
-; RV32I-NEXT:    andi a5, a6, 63
-; RV32I-NEXT:    addi a7, a5, -32
-; RV32I-NEXT:    slti t0, a7, 0
-; RV32I-NEXT:    neg t0, t0
-; RV32I-NEXT:    and a2, t0, a2
-; RV32I-NEXT:    bltz a7, .LBB10_5
+; RV32I-NEXT:    srai t0, a5, 31
+; RV32I-NEXT:    neg a5, a2
+; RV32I-NEXT:    andi a7, a5, 63
+; RV32I-NEXT:    addi a6, a7, -32
+; RV32I-NEXT:    and a2, t0, a4
+; RV32I-NEXT:    bltz a6, .LBB10_5
 ; RV32I-NEXT:  # %bb.4:
-; RV32I-NEXT:    srl a0, a1, a5
+; RV32I-NEXT:    srl a0, a1, a7
 ; RV32I-NEXT:    j .LBB10_6
 ; RV32I-NEXT:  .LBB10_5:
-; RV32I-NEXT:    srl a0, a0, a6
-; RV32I-NEXT:    not a5, a5
-; RV32I-NEXT:    slli a1, a1, 1
-; RV32I-NEXT:    sll a1, a1, a5
-; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    srl a0, a0, a5
+; RV32I-NEXT:    not a4, a7
+; RV32I-NEXT:    slli a7, a1, 1
+; RV32I-NEXT:    sll a4, a7, a4
+; RV32I-NEXT:    or a0, a0, a4
 ; RV32I-NEXT:  .LBB10_6:
-; RV32I-NEXT:    or a0, a4, a0
-; RV32I-NEXT:    or a1, a3, a2
+; RV32I-NEXT:    srl a1, a1, a5
+; RV32I-NEXT:    srai a4, a6, 31
+; RV32I-NEXT:    and a1, a4, a1
+; RV32I-NEXT:    or a1, a3, a1
+; RV32I-NEXT:    or a0, a2, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: rotl_64_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    negw a2, a1
 ; RV64I-NEXT:    sll a1, a0, a1
 ; RV64I-NEXT:    srl a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0

 ; RV32ZBB-NEXT:    j .LBB10_3
 ; RV32ZBB-NEXT:  .LBB10_2:
 ; RV32ZBB-NEXT:    sll a3, a1, a2
 ; RV32ZBB-NEXT:    not a6, a2
 ; RV32ZBB-NEXT:    srli a7, a0, 1
 ; RV32ZBB-NEXT:    srl a6, a7, a6
 ; RV32ZBB-NEXT:    or a3, a3, a6
 ; RV32ZBB-NEXT:  .LBB10_3:
-; RV32ZBB-NEXT:    slti a5, a5, 0
-; RV32ZBB-NEXT:    neg a5, a5
-; RV32ZBB-NEXT:    and a4, a5, a4
-; RV32ZBB-NEXT:    neg a6, a2
-; RV32ZBB-NEXT:    srl a2, a1, a6
-; RV32ZBB-NEXT:    andi a5, a6, 63
-; RV32ZBB-NEXT:    addi a7, a5, -32
-; RV32ZBB-NEXT:    slti t0, a7, 0
-; RV32ZBB-NEXT:    neg t0, t0
-; RV32ZBB-NEXT:    and a2, t0, a2
-; RV32ZBB-NEXT:    bltz a7, .LBB10_5
+; RV32ZBB-NEXT:    srai t0, a5, 31
+; RV32ZBB-NEXT:    neg a5, a2
+; RV32ZBB-NEXT:    andi a7, a5, 63
+; RV32ZBB-NEXT:    addi a6, a7, -32
+; RV32ZBB-NEXT:    and a2, t0, a4
+; RV32ZBB-NEXT:    bltz a6, .LBB10_5
 ; RV32ZBB-NEXT:  # %bb.4:
-; RV32ZBB-NEXT:    srl a0, a1, a5
+; RV32ZBB-NEXT:    srl a0, a1, a7
 ; RV32ZBB-NEXT:    j .LBB10_6
 ; RV32ZBB-NEXT:  .LBB10_5:
-; RV32ZBB-NEXT:    srl a0, a0, a6
-; RV32ZBB-NEXT:    not a5, a5
-; RV32ZBB-NEXT:    slli a1, a1, 1
-; RV32ZBB-NEXT:    sll a1, a1, a5
-; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    srl a0, a0, a5
+; RV32ZBB-NEXT:    not a4, a7
+; RV32ZBB-NEXT:    slli a7, a1, 1
+; RV32ZBB-NEXT:    sll a4, a7, a4
+; RV32ZBB-NEXT:    or a0, a0, a4
 ; RV32ZBB-NEXT:  .LBB10_6:
-; RV32ZBB-NEXT:    or a0, a4, a0
-; RV32ZBB-NEXT:    or a1, a3, a2
+; RV32ZBB-NEXT:    srl a1, a1, a5
+; RV32ZBB-NEXT:    srai a4, a6, 31
+; RV32ZBB-NEXT:    and a1, a4, a1
+; RV32ZBB-NEXT:    or a1, a3, a1
+; RV32ZBB-NEXT:    or a0, a2, a0
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rotl_64_mask:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    rol a0, a0, a1
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV32XTHEADBB-LABEL: rotl_64_mask:
 ; RV32XTHEADBB:       # %bb.0:
 ; RV32XTHEADBB-NEXT:    addi a5, a2, -32
 ; RV32XTHEADBB-NEXT:    sll a4, a0, a2
 ; RV32XTHEADBB-NEXT:    bltz a5, .LBB10_2
 ; RV32XTHEADBB-NEXT:  # %bb.1:
 ; RV32XTHEADBB-NEXT:    mv a3, a4
 ; RV32XTHEADBB-NEXT:    j .LBB10_3
 ; RV32XTHEADBB-NEXT:  .LBB10_2:
 ; RV32XTHEADBB-NEXT:    sll a3, a1, a2
 ; RV32XTHEADBB-NEXT:    not a6, a2
 ; RV32XTHEADBB-NEXT:    srli a7, a0, 1
 ; RV32XTHEADBB-NEXT:    srl a6, a7, a6
 ; RV32XTHEADBB-NEXT:    or a3, a3, a6
 ; RV32XTHEADBB-NEXT:  .LBB10_3:
-; RV32XTHEADBB-NEXT:    slti a5, a5, 0
-; RV32XTHEADBB-NEXT:    neg a5, a5
-; RV32XTHEADBB-NEXT:    and a4, a5, a4
-; RV32XTHEADBB-NEXT:    neg a6, a2
-; RV32XTHEADBB-NEXT:    srl a2, a1, a6
-; RV32XTHEADBB-NEXT:    andi a5, a6, 63
-; RV32XTHEADBB-NEXT:    addi a7, a5, -32
-; RV32XTHEADBB-NEXT:    slti t0, a7, 0
-; RV32XTHEADBB-NEXT:    neg t0, t0
-; RV32XTHEADBB-NEXT:    and a2, t0, a2
-; RV32XTHEADBB-NEXT:    bltz a7, .LBB10_5
+; RV32XTHEADBB-NEXT:    srai t0, a5, 31
+; RV32XTHEADBB-NEXT:    neg a5, a2
+; RV32XTHEADBB-NEXT:    andi a7, a5, 63
+; RV32XTHEADBB-NEXT:    addi a6, a7, -32
+; RV32XTHEADBB-NEXT:    and a2, t0, a4
+; RV32XTHEADBB-NEXT:    bltz a6, .LBB10_5
 ; RV32XTHEADBB-NEXT:  # %bb.4:
-; RV32XTHEADBB-NEXT:    srl a0, a1, a5
+; RV32XTHEADBB-NEXT:    srl a0, a1, a7
 ; RV32XTHEADBB-NEXT:    j .LBB10_6
 ; RV32XTHEADBB-NEXT:  .LBB10_5:
-; RV32XTHEADBB-NEXT:    srl a0, a0, a6
-; RV32XTHEADBB-NEXT:    not a5, a5
-; RV32XTHEADBB-NEXT:    slli a1, a1, 1
-; RV32XTHEADBB-NEXT:    sll a1, a1, a5
-; RV32XTHEADBB-NEXT:    or a0, a0, a1
+; RV32XTHEADBB-NEXT:    srl a0, a0, a5
+; RV32XTHEADBB-NEXT:    not a4, a7
+; RV32XTHEADBB-NEXT:    slli a7, a1, 1
+; RV32XTHEADBB-NEXT:    sll a4, a7, a4
+; RV32XTHEADBB-NEXT:    or a0, a0, a4
 ; RV32XTHEADBB-NEXT:  .LBB10_6:
-; RV32XTHEADBB-NEXT:    or a0, a4, a0
-; RV32XTHEADBB-NEXT:    or a1, a3, a2
+; RV32XTHEADBB-NEXT:    srl a1, a1, a5
+; RV32XTHEADBB-NEXT:    srai a4, a6, 31
+; RV32XTHEADBB-NEXT:    and a1, a4, a1
+; RV32XTHEADBB-NEXT:    or a1, a3, a1
+; RV32XTHEADBB-NEXT:    or a0, a2, a0
 ; RV32XTHEADBB-NEXT:    ret
 ;
 ; RV64XTHEADBB-LABEL: rotl_64_mask:
 ; RV64XTHEADBB:       # %bb.0:
 ; RV64XTHEADBB-NEXT:    sll a2, a0, a1
 ; RV64XTHEADBB-NEXT:    neg a1, a1
 ; RV64XTHEADBB-NEXT:    srl a0, a0, a1
 ; RV64XTHEADBB-NEXT:    or a0, a2, a0

 ; RV32I-NEXT:    j .LBB11_3
 ; RV32I-NEXT:  .LBB11_2:
 ; RV32I-NEXT:    sll a5, a1, a2
 ; RV32I-NEXT:    srli a6, a0, 1
 ; RV32I-NEXT:    not a3, a3
 ; RV32I-NEXT:    srl a3, a6, a3
 ; RV32I-NEXT:    or a3, a5, a3
 ; RV32I-NEXT:  .LBB11_3:
-; RV32I-NEXT:    sll a5, a0, a2
-; RV32I-NEXT:    slti a4, a4, 0
-; RV32I-NEXT:    neg a4, a4
-; RV32I-NEXT:    and a4, a4, a5
-; RV32I-NEXT:    neg a6, a2
-; RV32I-NEXT:    srl a2, a1, a6
-; RV32I-NEXT:    andi a5, a6, 63
-; RV32I-NEXT:    addi a7, a5, -32
-; RV32I-NEXT:    slti t0, a7, 0
-; RV32I-NEXT:    neg t0, t0
-; RV32I-NEXT:    and a2, t0, a2
-; RV32I-NEXT:    bltz a7, .LBB11_5
+; RV32I-NEXT:    sll a7, a0, a2
+; RV32I-NEXT:    srai t0, a4, 31
+; RV32I-NEXT:    neg a4, a2
+; RV32I-NEXT:    andi a6, a4, 63
+; RV32I-NEXT:    addi a5, a6, -32
+; RV32I-NEXT:    and a2, t0, a7
+; RV32I-NEXT:    bltz a5, .LBB11_5
 ; RV32I-NEXT:  # %bb.4:
-; RV32I-NEXT:    srl a0, a1, a5
+; RV32I-NEXT:    srl a0, a1, a6
 ; RV32I-NEXT:    j .LBB11_6
 ; RV32I-NEXT:  .LBB11_5:
-; RV32I-NEXT:    srl a0, a0, a6
-; RV32I-NEXT:    not a5, a5
-; RV32I-NEXT:    slli a1, a1, 1
-; RV32I-NEXT:    sll a1, a1, a5
-; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    srl a0, a0, a4
+; RV32I-NEXT:    not a6, a6
+; RV32I-NEXT:    slli a7, a1, 1
+; RV32I-NEXT:    sll a6, a7, a6
+; RV32I-NEXT:    or a0, a0, a6
 ; RV32I-NEXT:  .LBB11_6:
-; RV32I-NEXT:    or a0, a4, a0
-; RV32I-NEXT:    or a1, a3, a2
+; RV32I-NEXT:    srl a1, a1, a4
+; RV32I-NEXT:    srai a5, a5, 31
+; RV32I-NEXT:    and a1, a5, a1
+; RV32I-NEXT:    or a1, a3, a1
+; RV32I-NEXT:    or a0, a2, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: rotl_64_mask_and_127_and_63:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sll a2, a0, a1
 ; RV64I-NEXT:    negw a1, a1
 ; RV64I-NEXT:    srl a0, a0, a1
 ; RV64I-NEXT:    or a0, a2, a0

 ; RV32ZBB-NEXT:    j .LBB11_3
 ; RV32ZBB-NEXT:  .LBB11_2:
 ; RV32ZBB-NEXT:    sll a5, a1, a2
 ; RV32ZBB-NEXT:    srli a6, a0, 1
 ; RV32ZBB-NEXT:    not a3, a3
 ; RV32ZBB-NEXT:    srl a3, a6, a3
 ; RV32ZBB-NEXT:    or a3, a5, a3
 ; RV32ZBB-NEXT:  .LBB11_3:
-; RV32ZBB-NEXT:    sll a5, a0, a2
-; RV32ZBB-NEXT:    slti a4, a4, 0
-; RV32ZBB-NEXT:    neg a4, a4
-; RV32ZBB-NEXT:    and a4, a4, a5
-; RV32ZBB-NEXT:    neg a6, a2
-; RV32ZBB-NEXT:    srl a2, a1, a6
-; RV32ZBB-NEXT:    andi a5, a6, 63
-; RV32ZBB-NEXT:    addi a7, a5, -32
-; RV32ZBB-NEXT:    slti t0, a7, 0
-; RV32ZBB-NEXT:    neg t0, t0
-; RV32ZBB-NEXT:    and a2, t0, a2
-; RV32ZBB-NEXT:    bltz a7, .LBB11_5
+; RV32ZBB-NEXT:    sll a7, a0, a2
+; RV32ZBB-NEXT:    srai t0, a4, 31
+; RV32ZBB-NEXT:    neg a4, a2
+; RV32ZBB-NEXT:    andi a6, a4, 63
+; RV32ZBB-NEXT:    addi a5, a6, -32
+; RV32ZBB-NEXT:    and a2, t0, a7
+; RV32ZBB-NEXT:    bltz a5, .LBB11_5
 ; RV32ZBB-NEXT:  # %bb.4:
-; RV32ZBB-NEXT:    srl a0, a1, a5
+; RV32ZBB-NEXT:    srl a0, a1, a6
 ; RV32ZBB-NEXT:    j .LBB11_6
 ; RV32ZBB-NEXT:  .LBB11_5:
-; RV32ZBB-NEXT:    srl a0, a0, a6
-; RV32ZBB-NEXT:    not a5, a5
-; RV32ZBB-NEXT:    slli a1, a1, 1
-; RV32ZBB-NEXT:    sll a1, a1, a5
-; RV32ZBB-NEXT:    or a0, a0, a1
+; RV32ZBB-NEXT:    srl a0, a0, a4
+; RV32ZBB-NEXT:    not a6, a6
+; RV32ZBB-NEXT:    slli a7, a1, 1
+; RV32ZBB-NEXT:    sll a6, a7, a6
+; RV32ZBB-NEXT:    or a0, a0, a6
 ; RV32ZBB-NEXT:  .LBB11_6:
-; RV32ZBB-NEXT:    or a0, a4, a0
-; RV32ZBB-NEXT:    or a1, a3, a2
+; RV32ZBB-NEXT:    srl a1, a1, a4
+; RV32ZBB-NEXT:    srai a5, a5, 31
+; RV32ZBB-NEXT:    and a1, a5, a1
+; RV32ZBB-NEXT:    or a1, a3, a1
+; RV32ZBB-NEXT:    or a0, a2, a0
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rotl_64_mask_and_127_and_63:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    rol a0, a0, a1
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV32XTHEADBB-LABEL: rotl_64_mask_and_127_and_63:
 ; RV32XTHEADBB:       # %bb.0:
 ; RV32XTHEADBB-NEXT:    andi a3, a2, 127
 ; RV32XTHEADBB-NEXT:    addi a4, a3, -32
 ; RV32XTHEADBB-NEXT:    bltz a4, .LBB11_2
 ; RV32XTHEADBB-NEXT:  # %bb.1:
 ; RV32XTHEADBB-NEXT:    sll a3, a0, a3
 ; RV32XTHEADBB-NEXT:    j .LBB11_3
 ; RV32XTHEADBB-NEXT:  .LBB11_2:
 ; RV32XTHEADBB-NEXT:    sll a5, a1, a2
 ; RV32XTHEADBB-NEXT:    srli a6, a0, 1
 ; RV32XTHEADBB-NEXT:    not a3, a3
 ; RV32XTHEADBB-NEXT:    srl a3, a6, a3
 ; RV32XTHEADBB-NEXT:    or a3, a5, a3
 ; RV32XTHEADBB-NEXT:  .LBB11_3:
-; RV32XTHEADBB-NEXT:    sll a5, a0, a2
-; RV32XTHEADBB-NEXT:    slti a4, a4, 0
-; RV32XTHEADBB-NEXT:    neg a4, a4
-; RV32XTHEADBB-NEXT:    and a4, a4, a5
-; RV32XTHEADBB-NEXT:    neg a6, a2
-; RV32XTHEADBB-NEXT:    srl a2, a1, a6
-; RV32XTHEADBB-NEXT:    andi a5, a6, 63
-; RV32XTHEADBB-NEXT:    addi a7, a5, -32
-; RV32XTHEADBB-NEXT:    slti t0, a7, 0
-; RV32XTHEADBB-NEXT:    neg t0, t0
-; RV32XTHEADBB-NEXT:    and a2, t0, a2
-; RV32XTHEADBB-NEXT:    bltz a7, .LBB11_5
+; RV32XTHEADBB-NEXT:    sll a7, a0, a2
+; RV32XTHEADBB-NEXT:    srai t0, a4, 31
+; RV32XTHEADBB-NEXT:    neg a4, a2
+; RV32XTHEADBB-NEXT:    andi a6, a4, 63
+; RV32XTHEADBB-NEXT:    addi a5, a6, -32
+; RV32XTHEADBB-NEXT:    and a2, t0, a7
+; RV32XTHEADBB-NEXT:    bltz a5, .LBB11_5
 ; RV32XTHEADBB-NEXT:  # %bb.4:
-; RV32XTHEADBB-NEXT:    srl a0, a1, a5
+; RV32XTHEADBB-NEXT:    srl a0, a1, a6
 ; RV32XTHEADBB-NEXT:    j .LBB11_6
 ; RV32XTHEADBB-NEXT:  .LBB11_5:
-; RV32XTHEADBB-NEXT:    srl a0, a0, a6
-; RV32XTHEADBB-NEXT:    not a5, a5
-; RV32XTHEADBB-NEXT:    slli a1, a1, 1
-; RV32XTHEADBB-NEXT:    sll a1, a1, a5
-; RV32XTHEADBB-NEXT:    or a0, a0, a1
+; RV32XTHEADBB-NEXT:    srl a0, a0, a4
+; RV32XTHEADBB-NEXT:    not a6, a6
+; RV32XTHEADBB-NEXT:    slli a7, a1, 1
+; RV32XTHEADBB-NEXT:    sll a6, a7, a6
+; RV32XTHEADBB-NEXT:    or a0, a0, a6
 ; RV32XTHEADBB-NEXT:  .LBB11_6:
-; RV32XTHEADBB-NEXT:    or a0, a4, a0
-; RV32XTHEADBB-NEXT:    or a1, a3, a2
+; RV32XTHEADBB-NEXT:    srl a1, a1, a4
+; RV32XTHEADBB-NEXT:    srai a5, a5, 31
+; RV32XTHEADBB-NEXT:    and a1, a5, a1
+; RV32XTHEADBB-NEXT:    or a1, a3, a1
+; RV32XTHEADBB-NEXT:    or a0, a2, a0
 ; RV32XTHEADBB-NEXT:    ret
 ;
 ; RV64XTHEADBB-LABEL: rotl_64_mask_and_127_and_63:
 ; RV64XTHEADBB:       # %bb.0:
 ; RV64XTHEADBB-NEXT:    sll a2, a0, a1
 ; RV64XTHEADBB-NEXT:    neg a1, a1
 ; RV64XTHEADBB-NEXT:    srl a0, a0, a1
 ; RV64XTHEADBB-NEXT:    or a0, a2, a0
; RV64XTHEADBB-NEXT:    ret
   %e = lshr i64 %x, %d
   %f = or i64 %b, %e
   ret i64 %f
 }
 
 define i64 @rotr_64_mask(i64 %x, i64 %y) nounwind {
 ; RV32I-LABEL: rotr_64_mask:
 ; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a5, a2, -32
 ; RV32I-NEXT:    srl a4, a1, a2
-; RV32I-NEXT:    addi a3, a2, -32
-; RV32I-NEXT:    slti a5, a3, 0
-; RV32I-NEXT:    neg a5, a5
-; RV32I-NEXT:    bltz a3, .LBB13_2
+; RV32I-NEXT:    bltz a5, .LBB13_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a3, a4
 ; RV32I-NEXT:    j .LBB13_3
 ; RV32I-NEXT:  .LBB13_2:
 ; RV32I-NEXT:    srl a3, a0, a2
 ; RV32I-NEXT:    not a6, a2
 ; RV32I-NEXT:    slli a7, a1, 1
 ; RV32I-NEXT:    sll a6, a7, a6
 ; RV32I-NEXT:    or a3, a3, a6
 ; RV32I-NEXT:  .LBB13_3:
-; RV32I-NEXT:    neg a6, a2
-; RV32I-NEXT:    andi t0, a6, 63
-; RV32I-NEXT:    addi a7, t0, -32
-; RV32I-NEXT:    and a2, a5, a4
-; RV32I-NEXT:    bltz a7, .LBB13_5
+; RV32I-NEXT:    srai t0, a5, 31
+; RV32I-NEXT:    neg a5, a2
+; RV32I-NEXT:    andi a7, a5, 63
+; RV32I-NEXT:    addi a6, a7, -32
+; RV32I-NEXT:    and a2, t0, a4
+; RV32I-NEXT:    bltz a6, .LBB13_5
 ; RV32I-NEXT:  # %bb.4:
-; RV32I-NEXT:    sll a1, a0, t0
+; RV32I-NEXT:    sll a1, a0, a7
 ; RV32I-NEXT:    j .LBB13_6
 ; RV32I-NEXT:  .LBB13_5:
-; RV32I-NEXT:    sll a1, a1, a6
-; RV32I-NEXT:    not a4, t0
-; RV32I-NEXT:    srli a5, a0, 1
-; RV32I-NEXT:    srl a4, a5, a4
+; RV32I-NEXT:    sll a1, a1, a5
+; RV32I-NEXT:    not a4, a7
+; RV32I-NEXT:    srli a7, a0, 1
+; RV32I-NEXT:    srl a4, a7, a4
 ; RV32I-NEXT:    or a1, a1, a4
 ; RV32I-NEXT:  .LBB13_6:
-; RV32I-NEXT:    sll a0, a0, a6
-; RV32I-NEXT:    slti a4, a7, 0
-; RV32I-NEXT:    neg a4, a4
+; RV32I-NEXT:    sll a0, a0, a5
+; RV32I-NEXT:    srai a4, a6, 31
 ; RV32I-NEXT:    and a0, a4, a0
 ; RV32I-NEXT:    or a0, a3, a0
 ; RV32I-NEXT:    or a1, a2, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: rotr_64_mask:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    negw a2, a1
 ; RV64I-NEXT:    srl a1, a0, a1
 ; RV64I-NEXT:    sll a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: rotr_64_mask:
 ; RV32ZBB:       # %bb.0:
+; RV32ZBB-NEXT:    addi a5, a2, -32
 ; RV32ZBB-NEXT:    srl a4, a1, a2
-; RV32ZBB-NEXT:    addi a3, a2, -32
-; RV32ZBB-NEXT:    slti a5, a3, 0
-; RV32ZBB-NEXT:    neg a5, a5
-; RV32ZBB-NEXT:    bltz a3, .LBB13_2
+; RV32ZBB-NEXT:    bltz a5, .LBB13_2
 ; RV32ZBB-NEXT:  # %bb.1:
 ; RV32ZBB-NEXT:    mv a3, a4
 ; RV32ZBB-NEXT:    j .LBB13_3
 ; RV32ZBB-NEXT:  .LBB13_2:
 ; RV32ZBB-NEXT:    srl a3, a0, a2
 ; RV32ZBB-NEXT:    not a6, a2
 ; RV32ZBB-NEXT:    slli a7, a1, 1
 ; RV32ZBB-NEXT:    sll a6, a7, a6
 ; RV32ZBB-NEXT:    or a3, a3, a6
 ; RV32ZBB-NEXT:  .LBB13_3:
-; RV32ZBB-NEXT:    neg a6, a2
-; RV32ZBB-NEXT:    andi t0, a6, 63
-; RV32ZBB-NEXT:    addi a7, t0, -32
-; RV32ZBB-NEXT:    and a2, a5, a4
-; RV32ZBB-NEXT:    bltz a7, .LBB13_5
+; RV32ZBB-NEXT:    srai t0, a5, 31
+; RV32ZBB-NEXT:    neg a5, a2
+; RV32ZBB-NEXT:    andi a7, a5, 63
+; RV32ZBB-NEXT:    addi a6, a7, -32
+; RV32ZBB-NEXT:    and a2, t0, a4
+; RV32ZBB-NEXT:    bltz a6, .LBB13_5
 ; RV32ZBB-NEXT:  # %bb.4:
-; RV32ZBB-NEXT:    sll a1, a0, t0
+; RV32ZBB-NEXT:    sll a1, a0, a7
 ; RV32ZBB-NEXT:    j .LBB13_6
 ; RV32ZBB-NEXT:  .LBB13_5:
-; RV32ZBB-NEXT:    sll a1, a1, a6
-; RV32ZBB-NEXT:    not a4, t0
-; RV32ZBB-NEXT:    srli a5, a0, 1
-; RV32ZBB-NEXT:    srl a4, a5, a4
+; RV32ZBB-NEXT:    sll a1, a1, a5
+; RV32ZBB-NEXT:    not a4, a7
+; RV32ZBB-NEXT:    srli a7, a0, 1
+; RV32ZBB-NEXT:    srl a4, a7, a4
 ; RV32ZBB-NEXT:    or a1, a1, a4
 ; RV32ZBB-NEXT:  .LBB13_6:
-; RV32ZBB-NEXT:    sll a0, a0, a6
-; RV32ZBB-NEXT:    slti a4, a7, 0
-; RV32ZBB-NEXT:    neg a4, a4
+; RV32ZBB-NEXT:    sll a0, a0, a5
+; RV32ZBB-NEXT:    srai a4, a6, 31
 ; RV32ZBB-NEXT:    and a0, a4, a0
 ; RV32ZBB-NEXT:    or a0, a3, a0
 ; RV32ZBB-NEXT:    or a1, a2, a1
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rotr_64_mask:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    ror a0, a0, a1
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV32XTHEADBB-LABEL: rotr_64_mask:
 ; RV32XTHEADBB:       # %bb.0:
+; RV32XTHEADBB-NEXT:    addi a5, a2, -32
 ; RV32XTHEADBB-NEXT:    srl a4, a1, a2
-; RV32XTHEADBB-NEXT:    addi a3, a2, -32
-; RV32XTHEADBB-NEXT:    slti a5, a3, 0
-; RV32XTHEADBB-NEXT:    neg a5, a5
-; RV32XTHEADBB-NEXT:    bltz a3, .LBB13_2
+; RV32XTHEADBB-NEXT:    bltz a5, .LBB13_2
 ; RV32XTHEADBB-NEXT:  # %bb.1:
 ; RV32XTHEADBB-NEXT:    mv a3, a4
 ; RV32XTHEADBB-NEXT:    j .LBB13_3
 ; RV32XTHEADBB-NEXT:  .LBB13_2:
 ; RV32XTHEADBB-NEXT:    srl a3, a0, a2
 ; RV32XTHEADBB-NEXT:    not a6, a2
 ; RV32XTHEADBB-NEXT:    slli a7, a1, 1
 ; RV32XTHEADBB-NEXT:    sll a6, a7, a6
 ; RV32XTHEADBB-NEXT:    or a3, a3, a6
 ; RV32XTHEADBB-NEXT:  .LBB13_3:
-; RV32XTHEADBB-NEXT:    neg a6, a2
-; RV32XTHEADBB-NEXT:    andi t0, a6, 63
-; RV32XTHEADBB-NEXT:    addi a7, t0, -32
-; RV32XTHEADBB-NEXT:    and a2, a5, a4
-; RV32XTHEADBB-NEXT:    bltz a7, .LBB13_5
+; RV32XTHEADBB-NEXT:    srai t0, a5, 31
+; RV32XTHEADBB-NEXT:    neg a5, a2
+; RV32XTHEADBB-NEXT:    andi a7, a5, 63
+; RV32XTHEADBB-NEXT:    addi a6, a7, -32
+; RV32XTHEADBB-NEXT:    and a2, t0, a4
+; RV32XTHEADBB-NEXT:    bltz a6, .LBB13_5
 ; RV32XTHEADBB-NEXT:  # %bb.4:
-; RV32XTHEADBB-NEXT:    sll a1, a0, t0
+; RV32XTHEADBB-NEXT:    sll a1, a0, a7
 ; RV32XTHEADBB-NEXT:    j .LBB13_6
 ; RV32XTHEADBB-NEXT:  .LBB13_5:
-; RV32XTHEADBB-NEXT:    sll a1, a1, a6
-; RV32XTHEADBB-NEXT:    not a4, t0
-; RV32XTHEADBB-NEXT:    srli a5, a0, 1
-; RV32XTHEADBB-NEXT:    srl a4, a5, a4
+; RV32XTHEADBB-NEXT:    sll a1, a1, a5
+; RV32XTHEADBB-NEXT:    not a4, a7
+; RV32XTHEADBB-NEXT:    srli a7, a0, 1
+; RV32XTHEADBB-NEXT:    srl a4, a7, a4
 ; RV32XTHEADBB-NEXT:    or a1, a1, a4
 ; RV32XTHEADBB-NEXT:  .LBB13_6:
-; RV32XTHEADBB-NEXT:    sll a0, a0, a6
-; RV32XTHEADBB-NEXT:    slti a4, a7, 0
-; RV32XTHEADBB-NEXT:    neg a4, a4
+; RV32XTHEADBB-NEXT:    sll a0, a0, a5
+; RV32XTHEADBB-NEXT:    srai a4, a6, 31
 ; RV32XTHEADBB-NEXT:    and a0, a4, a0
 ; RV32XTHEADBB-NEXT:    or a0, a3, a0
 ; RV32XTHEADBB-NEXT:    or a1, a2, a1
 ; RV32XTHEADBB-NEXT:    ret
 ;
 ; RV64XTHEADBB-LABEL: rotr_64_mask:
 ; RV64XTHEADBB:       # %bb.0:
 ; RV64XTHEADBB-NEXT:    srl a2, a0, a1
 ; RV64XTHEADBB-NEXT:    neg a1, a1
 ; RV64XTHEADBB-NEXT:    sll a0, a0, a1
 ; RV64XTHEADBB-NEXT:    or a0, a2, a0
 ; RV64XTHEADBB-NEXT:    ret
   %z = sub i64 0, %y
   %and = and i64 %z, 63
   %b = lshr i64 %x, %y
   %c = shl i64 %x, %and
   %d = or i64 %b, %c
   ret i64 %d
 }
 
 define i64 @rotr_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {
 ; RV32I-LABEL: rotr_64_mask_and_127_and_63:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    srl a4, a1, a2
 ; RV32I-NEXT:    andi a3, a2, 127
-; RV32I-NEXT:    addi a6, a3, -32
-; RV32I-NEXT:    slti a5, a6, 0
-; RV32I-NEXT:    neg a5, a5
-; RV32I-NEXT:    bltz a6, .LBB14_2
+; RV32I-NEXT:    addi a4, a3, -32
+; RV32I-NEXT:    bltz a4, .LBB14_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    srl a3, a1, a3
 ; RV32I-NEXT:    j .LBB14_3
 ; RV32I-NEXT:  .LBB14_2:
-; RV32I-NEXT:    srl a6, a0, a2
-; RV32I-NEXT:    slli a7, a1, 1
+; RV32I-NEXT:    srl a5, a0, a2
+; RV32I-NEXT:    slli a6, a1, 1
 ; RV32I-NEXT:    not a3, a3
-; RV32I-NEXT:    sll a3, a7, a3
-; RV32I-NEXT:    or a3, a6, a3
+; RV32I-NEXT:    sll a3, a6, a3
+; RV32I-NEXT:    or a3, a5, a3
 ; RV32I-NEXT:  .LBB14_3:
-; RV32I-NEXT:    neg a6, a2
-; RV32I-NEXT:    andi t0, a6, 63
-; RV32I-NEXT:    addi a7, t0, -32
-; RV32I-NEXT:    and a2, a5, a4
-; RV32I-NEXT:    bltz a7, .LBB14_5
+; RV32I-NEXT:    srl a7, a1, a2
+; RV32I-NEXT:    srai t0, a4, 31
+; RV32I-NEXT:    neg a4, a2
+; RV32I-NEXT:    andi a6, a4, 63
+; RV32I-NEXT:    addi a5, a6, -32
+; RV32I-NEXT:    and a2, t0, a7
+; RV32I-NEXT:    bltz a5, .LBB14_5
 ; RV32I-NEXT:  # %bb.4:
-; RV32I-NEXT:    sll a1, a0, t0
+; RV32I-NEXT:    sll a1, a0, a6
 ; RV32I-NEXT:    j .LBB14_6
 ; RV32I-NEXT:  .LBB14_5:
-; RV32I-NEXT:    sll a1, a1, a6
-; RV32I-NEXT:    not a4, t0
-; RV32I-NEXT:    srli a5, a0, 1
-; RV32I-NEXT:    srl a4, a5, a4
-; RV32I-NEXT:    or a1, a1, a4
+; RV32I-NEXT:    sll a1, a1, a4
+; RV32I-NEXT:    not a6, a6
+; RV32I-NEXT:    srli a7, a0, 1
+; RV32I-NEXT:    srl a6, a7, a6
+; RV32I-NEXT:    or a1, a1, a6
 ; RV32I-NEXT:  .LBB14_6:
-; RV32I-NEXT:    sll a0, a0, a6
-; RV32I-NEXT:    slti a4, a7, 0
-; RV32I-NEXT:    neg a4, a4
-; RV32I-NEXT:    and a0, a4, a0
+; RV32I-NEXT:    sll a0, a0, a4
+; RV32I-NEXT:    srai a5, a5, 31
+; RV32I-NEXT:    and a0, a5, a0
 ; RV32I-NEXT:    or a0, a3, a0
 ; RV32I-NEXT:    or a1, a2, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: rotr_64_mask_and_127_and_63:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srl a2, a0, a1
 ; RV64I-NEXT:    negw a1, a1
 ; RV64I-NEXT:    sll a0, a0, a1
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: rotr_64_mask_and_127_and_63:
 ; RV32ZBB:       # %bb.0:
-; RV32ZBB-NEXT:    srl a4, a1, a2
 ; RV32ZBB-NEXT:    andi a3, a2, 127
-; RV32ZBB-NEXT:    addi a6, a3, -32
-; RV32ZBB-NEXT:    slti a5, a6, 0
-; RV32ZBB-NEXT:    neg a5, a5
-; RV32ZBB-NEXT:    bltz a6, .LBB14_2
+; RV32ZBB-NEXT:    addi a4, a3, -32
+; RV32ZBB-NEXT:    bltz a4, .LBB14_2
 ; RV32ZBB-NEXT:  # %bb.1:
 ; RV32ZBB-NEXT:    srl a3, a1, a3
 ; RV32ZBB-NEXT:    j .LBB14_3
 ; RV32ZBB-NEXT:  .LBB14_2:
-; RV32ZBB-NEXT:    srl a6, a0, a2
-; RV32ZBB-NEXT:    slli a7, a1, 1
+; RV32ZBB-NEXT:    srl a5, a0, a2
+; RV32ZBB-NEXT:    slli a6, a1, 1
 ; RV32ZBB-NEXT:    not a3, a3
-; RV32ZBB-NEXT:    sll a3, a7, a3
-; RV32ZBB-NEXT:    or a3, a6, a3
+; RV32ZBB-NEXT:    sll a3, a6, a3
+; RV32ZBB-NEXT:    or a3, a5, a3
 ; RV32ZBB-NEXT:  .LBB14_3:
-; RV32ZBB-NEXT:    neg a6, a2
-; RV32ZBB-NEXT:    andi t0, a6, 63
-; RV32ZBB-NEXT:    addi a7, t0, -32
-; RV32ZBB-NEXT:    and a2, a5, a4
-; RV32ZBB-NEXT:    bltz a7, .LBB14_5
+; RV32ZBB-NEXT:    srl a7, a1, a2
+; RV32ZBB-NEXT:    srai t0, a4, 31
+; RV32ZBB-NEXT:    neg a4, a2
+; RV32ZBB-NEXT:    andi a6, a4, 63
+; RV32ZBB-NEXT:    addi a5, a6, -32
+; RV32ZBB-NEXT:    and a2, t0, a7
+; RV32ZBB-NEXT:    bltz a5, .LBB14_5
 ; RV32ZBB-NEXT:  # %bb.4:
-; RV32ZBB-NEXT:    sll a1, a0, t0
+; RV32ZBB-NEXT:    sll a1, a0, a6
 ; RV32ZBB-NEXT:    j .LBB14_6
 ; RV32ZBB-NEXT:  .LBB14_5:
-; RV32ZBB-NEXT:    sll a1, a1, a6
-; RV32ZBB-NEXT:    not a4, t0
-; RV32ZBB-NEXT:    srli a5, a0, 1
-; RV32ZBB-NEXT:    srl a4, a5, a4
-; RV32ZBB-NEXT:    or a1, a1, a4
+; RV32ZBB-NEXT:    sll a1, a1, a4
+; RV32ZBB-NEXT:    not a6, a6
+; RV32ZBB-NEXT:    srli a7, a0, 1
+; RV32ZBB-NEXT:    srl a6, a7, a6
+; RV32ZBB-NEXT:    or a1, a1, a6
 ; RV32ZBB-NEXT:  .LBB14_6:
-; RV32ZBB-NEXT:    sll a0, a0, a6
-; RV32ZBB-NEXT:    slti a4, a7, 0
-; RV32ZBB-NEXT:    neg a4, a4
-; RV32ZBB-NEXT:    and a0, a4, a0
+; RV32ZBB-NEXT:    sll a0, a0, a4
+; RV32ZBB-NEXT:    srai a5, a5, 31
+; RV32ZBB-NEXT:    and a0, a5, a0
 ; RV32ZBB-NEXT:    or a0, a3, a0
 ; RV32ZBB-NEXT:    or a1, a2, a1
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rotr_64_mask_and_127_and_63:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    ror a0, a0, a1
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV32XTHEADBB-LABEL: rotr_64_mask_and_127_and_63:
 ; RV32XTHEADBB:       # %bb.0:
-; RV32XTHEADBB-NEXT:    srl a4, a1, a2
 ; RV32XTHEADBB-NEXT:    andi a3, a2, 127
-; RV32XTHEADBB-NEXT:    addi a6, a3, -32
-; RV32XTHEADBB-NEXT:    slti a5, a6, 0
-; RV32XTHEADBB-NEXT:    neg a5, a5
-; RV32XTHEADBB-NEXT:    bltz a6, .LBB14_2
+; RV32XTHEADBB-NEXT:    addi a4, a3, -32
+; RV32XTHEADBB-NEXT:    bltz a4, .LBB14_2
 ; RV32XTHEADBB-NEXT:  # %bb.1:
 ; RV32XTHEADBB-NEXT:    srl a3, a1, a3
 ; RV32XTHEADBB-NEXT:    j .LBB14_3
 ; RV32XTHEADBB-NEXT:  .LBB14_2:
-; RV32XTHEADBB-NEXT:    srl a6, a0, a2
-; RV32XTHEADBB-NEXT:    slli a7, a1, 1
+; RV32XTHEADBB-NEXT:    srl a5, a0, a2
+; RV32XTHEADBB-NEXT:    slli a6, a1, 1
 ; RV32XTHEADBB-NEXT:    not a3, a3
-; RV32XTHEADBB-NEXT:    sll a3, a7, a3
-; RV32XTHEADBB-NEXT:    or a3, a6, a3
+; RV32XTHEADBB-NEXT:    sll a3, a6, a3
+; RV32XTHEADBB-NEXT:    or a3, a5, a3
 ; RV32XTHEADBB-NEXT:  .LBB14_3:
-; RV32XTHEADBB-NEXT:    neg a6, a2
-; RV32XTHEADBB-NEXT:    andi t0, a6, 63
-; RV32XTHEADBB-NEXT:    addi a7, t0, -32
-; RV32XTHEADBB-NEXT:    and a2, a5, a4
-; RV32XTHEADBB-NEXT:    bltz a7, .LBB14_5
+; RV32XTHEADBB-NEXT:    srl a7, a1, a2
+; RV32XTHEADBB-NEXT:    srai t0, a4, 31
+; RV32XTHEADBB-NEXT:    neg a4, a2
+; RV32XTHEADBB-NEXT:    andi a6, a4, 63
+; RV32XTHEADBB-NEXT:    addi a5, a6, -32
+; RV32XTHEADBB-NEXT:    and a2, t0, a7
+; RV32XTHEADBB-NEXT:    bltz a5, .LBB14_5
 ; RV32XTHEADBB-NEXT:  # %bb.4:
-; RV32XTHEADBB-NEXT:    sll a1, a0, t0
+; RV32XTHEADBB-NEXT:    sll a1, a0, a6
 ; RV32XTHEADBB-NEXT:    j .LBB14_6
 ; RV32XTHEADBB-NEXT:  .LBB14_5:
-; RV32XTHEADBB-NEXT:    sll a1, a1, a6
-; RV32XTHEADBB-NEXT:    not a4, t0
-; RV32XTHEADBB-NEXT:    srli a5, a0, 1
-; RV32XTHEADBB-NEXT:    srl a4, a5, a4
-; RV32XTHEADBB-NEXT:    or a1, a1, a4
+; RV32XTHEADBB-NEXT:    sll a1, a1, a4
+; RV32XTHEADBB-NEXT:    not a6, a6
+; RV32XTHEADBB-NEXT:    srli a7, a0, 1
+; RV32XTHEADBB-NEXT:    srl a6, a7, a6
+; RV32XTHEADBB-NEXT:    or a1, a1, a6
 ; RV32XTHEADBB-NEXT:  .LBB14_6:
-; RV32XTHEADBB-NEXT:    sll a0, a0, a6
-; RV32XTHEADBB-NEXT:    slti a4, a7, 0
-; RV32XTHEADBB-NEXT:    neg a4, a4
-; RV32XTHEADBB-NEXT:    and a0, a4, a0
+; RV32XTHEADBB-NEXT:    sll a0, a0, a4
+; RV32XTHEADBB-NEXT:    srai a5, a5, 31
+; RV32XTHEADBB-NEXT:    and a0, a5, a0
 ; RV32XTHEADBB-NEXT:    or a0, a3, a0
 ; RV32XTHEADBB-NEXT:    or a1, a2, a1
 ; RV32XTHEADBB-NEXT:    ret
 ;
 ; RV64XTHEADBB-LABEL: rotr_64_mask_and_127_and_63:
 ; RV64XTHEADBB:       # %bb.0:
 ; RV64XTHEADBB-NEXT:    srl a2, a0, a1
 ; RV64XTHEADBB-NEXT:    neg a1, a1

 ; RV32I-NEXT:  .LBB17_6:
 ; RV32I-NEXT:    sll a3, a3, a4
 ; RV32I-NEXT:    srli a7, a2, 1
 ; RV32I-NEXT:    not a6, a6
 ; RV32I-NEXT:    srl a6, a7, a6
 ; RV32I-NEXT:    or a3, a3, a6
 ; RV32I-NEXT:  .LBB17_7:
 ; RV32I-NEXT:    sll a2, a2, a4
-; RV32I-NEXT:    slti a0, a0, 0
-; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    srai a0, a0, 31
 ; RV32I-NEXT:    and a0, a0, a2
 ; RV32I-NEXT:    add a0, a1, a0
 ; RV32I-NEXT:    sltu a1, a0, a1
 ; RV32I-NEXT:    add a3, a5, a3
 ; RV32I-NEXT:    add a1, a3, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: rotl_64_mask_shared:

 ; RV32ZBB-NEXT:  .LBB17_6:
 ; RV32ZBB-NEXT:    sll a3, a3, a4
 ; RV32ZBB-NEXT:    srli a7, a2, 1
 ; RV32ZBB-NEXT:    not a6, a6
 ; RV32ZBB-NEXT:    srl a6, a7, a6
 ; RV32ZBB-NEXT:    or a3, a3, a6
 ; RV32ZBB-NEXT:  .LBB17_7:
 ; RV32ZBB-NEXT:    sll a2, a2, a4
-; RV32ZBB-NEXT:    slti a0, a0, 0
-; RV32ZBB-NEXT:    neg a0, a0
+; RV32ZBB-NEXT:    srai a0, a0, 31
 ; RV32ZBB-NEXT:    and a0, a0, a2
 ; RV32ZBB-NEXT:    add a0, a1, a0
 ; RV32ZBB-NEXT:    sltu a1, a0, a1
 ; RV32ZBB-NEXT:    add a3, a5, a3
 ; RV32ZBB-NEXT:    add a1, a3, a1
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rotl_64_mask_shared:

 ; RV32XTHEADBB-NEXT:  .LBB17_6:
 ; RV32XTHEADBB-NEXT:    sll a3, a3, a4
 ; RV32XTHEADBB-NEXT:    srli a7, a2, 1
 ; RV32XTHEADBB-NEXT:    not a6, a6
 ; RV32XTHEADBB-NEXT:    srl a6, a7, a6
 ; RV32XTHEADBB-NEXT:    or a3, a3, a6
 ; RV32XTHEADBB-NEXT:  .LBB17_7:
 ; RV32XTHEADBB-NEXT:    sll a2, a2, a4
-; RV32XTHEADBB-NEXT:    slti a0, a0, 0
-; RV32XTHEADBB-NEXT:    neg a0, a0
+; RV32XTHEADBB-NEXT:    srai a0, a0, 31
 ; RV32XTHEADBB-NEXT:    and a0, a0, a2
 ; RV32XTHEADBB-NEXT:    add a0, a1, a0
 ; RV32XTHEADBB-NEXT:    sltu a1, a0, a1
 ; RV32XTHEADBB-NEXT:    add a3, a5, a3
 ; RV32XTHEADBB-NEXT:    add a1, a3, a1
 ; RV32XTHEADBB-NEXT:    ret
 ;
 ; RV64XTHEADBB-LABEL: rotl_64_mask_shared:

 ; RV32I-NEXT:  .LBB19_6:
 ; RV32I-NEXT:    sll a3, a3, a4
 ; RV32I-NEXT:    srli a7, a2, 1
 ; RV32I-NEXT:    not a5, a5
 ; RV32I-NEXT:    srl a5, a7, a5
 ; RV32I-NEXT:    or a3, a3, a5
 ; RV32I-NEXT:  .LBB19_7:
 ; RV32I-NEXT:    sll a2, a2, a4
-; RV32I-NEXT:    slti a0, a0, 0
-; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    srai a0, a0, 31
 ; RV32I-NEXT:    and a0, a0, a2
 ; RV32I-NEXT:    add a0, a6, a0
 ; RV32I-NEXT:    sltu a2, a0, a6
 ; RV32I-NEXT:    add a1, a1, a3
 ; RV32I-NEXT:    add a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: rotr_64_mask_shared:

 ; RV32ZBB-NEXT:  .LBB19_6:
 ; RV32ZBB-NEXT:    sll a3, a3, a4
 ; RV32ZBB-NEXT:    srli a7, a2, 1
 ; RV32ZBB-NEXT:    not a5, a5
 ; RV32ZBB-NEXT:    srl a5, a7, a5
 ; RV32ZBB-NEXT:    or a3, a3, a5
 ; RV32ZBB-NEXT:  .LBB19_7:
 ; RV32ZBB-NEXT:    sll a2, a2, a4
-; RV32ZBB-NEXT:    slti a0, a0, 0
-; RV32ZBB-NEXT:    neg a0, a0
+; RV32ZBB-NEXT:    srai a0, a0, 31
 ; RV32ZBB-NEXT:    and a0, a0, a2
 ; RV32ZBB-NEXT:    add a0, a6, a0
 ; RV32ZBB-NEXT:    sltu a2, a0, a6
 ; RV32ZBB-NEXT:    add a1, a1, a3
 ; RV32ZBB-NEXT:    add a1, a1, a2
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rotr_64_mask_shared:

 ; RV32XTHEADBB-NEXT:  .LBB19_6:
 ; RV32XTHEADBB-NEXT:    sll a3, a3, a4
 ; RV32XTHEADBB-NEXT:    srli a7, a2, 1
 ; RV32XTHEADBB-NEXT:    not a5, a5
 ; RV32XTHEADBB-NEXT:    srl a5, a7, a5
 ; RV32XTHEADBB-NEXT:    or a3, a3, a5
 ; RV32XTHEADBB-NEXT:  .LBB19_7:
 ; RV32XTHEADBB-NEXT:    sll a2, a2, a4
-; RV32XTHEADBB-NEXT:    slti a0, a0, 0
-; RV32XTHEADBB-NEXT:    neg a0, a0
+; RV32XTHEADBB-NEXT:    srai a0, a0, 31
 ; RV32XTHEADBB-NEXT:    and a0, a0, a2
 ; RV32XTHEADBB-NEXT:    add a0, a6, a0
 ; RV32XTHEADBB-NEXT:    sltu a2, a0, a6
 ; RV32XTHEADBB-NEXT:    add a1, a1, a3
 ; RV32XTHEADBB-NEXT:    add a1, a1, a2
 ; RV32XTHEADBB-NEXT:    ret
 ;
 ; RV64XTHEADBB-LABEL: rotr_64_mask_shared:
; RV64XTHEADBB-NEXT:    ret
   %3 = add i64 %1, %2
   ret i64 %3
 }
 
 define i64 @rotl_64_zext(i64 %x, i32 %y) nounwind {
 ; RV32I-LABEL: rotl_64_zext:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    neg a4, a2
+; RV32I-NEXT:    addi a6, a2, -32
 ; RV32I-NEXT:    sll a5, a0, a2
-; RV32I-NEXT:    addi a3, a2, -32
-; RV32I-NEXT:    slti a6, a3, 0
-; RV32I-NEXT:    neg a6, a6
-; RV32I-NEXT:    bltz a3, .LBB24_2
+; RV32I-NEXT:    bltz a6, .LBB24_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    j .LBB24_3
 ; RV32I-NEXT:  .LBB24_2:
 ; RV32I-NEXT:    sll a3, a1, a2
 ; RV32I-NEXT:    not a7, a2
 ; RV32I-NEXT:    srli t0, a0, 1
 ; RV32I-NEXT:    srl a7, t0, a7
 ; RV32I-NEXT:    or a3, a3, a7
 ; RV32I-NEXT:  .LBB24_3:
+; RV32I-NEXT:    srai a6, a6, 31
 ; RV32I-NEXT:    and a5, a6, a5
 ; RV32I-NEXT:    li a6, 32
-; RV32I-NEXT:    sub a7, a6, a2
-; RV32I-NEXT:    srl a6, a1, a4
-; RV32I-NEXT:    bltz a7, .LBB24_5
+; RV32I-NEXT:    sub a6, a6, a2
+; RV32I-NEXT:    srl a7, a1, a4
+; RV32I-NEXT:    bltz a6, .LBB24_5
 ; RV32I-NEXT:  # %bb.4:
-; RV32I-NEXT:    mv a0, a6
+; RV32I-NEXT:    mv a0, a7
 ; RV32I-NEXT:    j .LBB24_6
 ; RV32I-NEXT:  .LBB24_5:
 ; RV32I-NEXT:    li t0, 64
 ; RV32I-NEXT:    sub a2, t0, a2
 ; RV32I-NEXT:    srl a0, a0, a4
 ; RV32I-NEXT:    not a2, a2
 ; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    sll a1, a1, a2
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:  .LBB24_6:
-; RV32I-NEXT:    slti a1, a7, 0
-; RV32I-NEXT:    neg a1, a1
-; RV32I-NEXT:    and a1, a1, a6
+; RV32I-NEXT:    srai a1, a6, 31
+; RV32I-NEXT:    and a1, a1, a7
 ; RV32I-NEXT:    or a1, a3, a1
 ; RV32I-NEXT:    or a0, a5, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: rotl_64_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    negw a2, a1
 ; RV64I-NEXT:    sll a1, a0, a1
 ; RV64I-NEXT:    srl a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: rotl_64_zext:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    neg a4, a2
+; RV32ZBB-NEXT:    addi a6, a2, -32
 ; RV32ZBB-NEXT:    sll a5, a0, a2
-; RV32ZBB-NEXT:    addi a3, a2, -32
-; RV32ZBB-NEXT:    slti a6, a3, 0
-; RV32ZBB-NEXT:    neg a6, a6
-; RV32ZBB-NEXT:    bltz a3, .LBB24_2
+; RV32ZBB-NEXT:    bltz a6, .LBB24_2
 ; RV32ZBB-NEXT:  # %bb.1:
 ; RV32ZBB-NEXT:    mv a3, a5
 ; RV32ZBB-NEXT:    j .LBB24_3
 ; RV32ZBB-NEXT:  .LBB24_2:
 ; RV32ZBB-NEXT:    sll a3, a1, a2
 ; RV32ZBB-NEXT:    not a7, a2
 ; RV32ZBB-NEXT:    srli t0, a0, 1
 ; RV32ZBB-NEXT:    srl a7, t0, a7
 ; RV32ZBB-NEXT:    or a3, a3, a7
 ; RV32ZBB-NEXT:  .LBB24_3:
+; RV32ZBB-NEXT:    srai a6, a6, 31
 ; RV32ZBB-NEXT:    and a5, a6, a5
 ; RV32ZBB-NEXT:    li a6, 32
-; RV32ZBB-NEXT:    sub a7, a6, a2
-; RV32ZBB-NEXT:    srl a6, a1, a4
-; RV32ZBB-NEXT:    bltz a7, .LBB24_5
+; RV32ZBB-NEXT:    sub a6, a6, a2
+; RV32ZBB-NEXT:    srl a7, a1, a4
+; RV32ZBB-NEXT:    bltz a6, .LBB24_5
 ; RV32ZBB-NEXT:  # %bb.4:
-; RV32ZBB-NEXT:    mv a0, a6
+; RV32ZBB-NEXT:    mv a0, a7
 ; RV32ZBB-NEXT:    j .LBB24_6
 ; RV32ZBB-NEXT:  .LBB24_5:
 ; RV32ZBB-NEXT:    li t0, 64
 ; RV32ZBB-NEXT:    sub a2, t0, a2
 ; RV32ZBB-NEXT:    srl a0, a0, a4
 ; RV32ZBB-NEXT:    not a2, a2
 ; RV32ZBB-NEXT:    slli a1, a1, 1
 ; RV32ZBB-NEXT:    sll a1, a1, a2
 ; RV32ZBB-NEXT:    or a0, a0, a1
 ; RV32ZBB-NEXT:  .LBB24_6:
-; RV32ZBB-NEXT:    slti a1, a7, 0
-; RV32ZBB-NEXT:    neg a1, a1
-; RV32ZBB-NEXT:    and a1, a1, a6
+; RV32ZBB-NEXT:    srai a1, a6, 31
+; RV32ZBB-NEXT:    and a1, a1, a7
 ; RV32ZBB-NEXT:    or a1, a3, a1
 ; RV32ZBB-NEXT:    or a0, a5, a0
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rotl_64_zext:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    rol a0, a0, a1
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV32XTHEADBB-LABEL: rotl_64_zext:
 ; RV32XTHEADBB:       # %bb.0:
 ; RV32XTHEADBB-NEXT:    neg a4, a2
+; RV32XTHEADBB-NEXT:    addi a6, a2, -32
 ; RV32XTHEADBB-NEXT:    sll a5, a0, a2
-; RV32XTHEADBB-NEXT:    addi a3, a2, -32
-; RV32XTHEADBB-NEXT:    slti a6, a3, 0
-; RV32XTHEADBB-NEXT:    neg a6, a6
-; RV32XTHEADBB-NEXT:    bltz a3, .LBB24_2
+; RV32XTHEADBB-NEXT:    bltz a6, .LBB24_2
 ; RV32XTHEADBB-NEXT:  # %bb.1:
 ; RV32XTHEADBB-NEXT:    mv a3, a5
 ; RV32XTHEADBB-NEXT:    j .LBB24_3
 ; RV32XTHEADBB-NEXT:  .LBB24_2:
 ; RV32XTHEADBB-NEXT:    sll a3, a1, a2
 ; RV32XTHEADBB-NEXT:    not a7, a2
 ; RV32XTHEADBB-NEXT:    srli t0, a0, 1
 ; RV32XTHEADBB-NEXT:    srl a7, t0, a7
 ; RV32XTHEADBB-NEXT:    or a3, a3, a7
 ; RV32XTHEADBB-NEXT:  .LBB24_3:
+; RV32XTHEADBB-NEXT:    srai a6, a6, 31
 ; RV32XTHEADBB-NEXT:    and a5, a6, a5
 ; RV32XTHEADBB-NEXT:    li a6, 32
-; RV32XTHEADBB-NEXT:    sub a7, a6, a2
-; RV32XTHEADBB-NEXT:    srl a6, a1, a4
-; RV32XTHEADBB-NEXT:    bltz a7, .LBB24_5
+; RV32XTHEADBB-NEXT:    sub a6, a6, a2
+; RV32XTHEADBB-NEXT:    srl a7, a1, a4
+; RV32XTHEADBB-NEXT:    bltz a6, .LBB24_5
 ; RV32XTHEADBB-NEXT:  # %bb.4:
-; RV32XTHEADBB-NEXT:    mv a0, a6
+; RV32XTHEADBB-NEXT:    mv a0, a7
 ; RV32XTHEADBB-NEXT:    j .LBB24_6
 ; RV32XTHEADBB-NEXT:  .LBB24_5:
 ; RV32XTHEADBB-NEXT:    li t0, 64
 ; RV32XTHEADBB-NEXT:    sub a2, t0, a2
 ; RV32XTHEADBB-NEXT:    srl a0, a0, a4
 ; RV32XTHEADBB-NEXT:    not a2, a2
 ; RV32XTHEADBB-NEXT:    slli a1, a1, 1
 ; RV32XTHEADBB-NEXT:    sll a1, a1, a2
 ; RV32XTHEADBB-NEXT:    or a0, a0, a1
 ; RV32XTHEADBB-NEXT:  .LBB24_6:
-; RV32XTHEADBB-NEXT:    slti a1, a7, 0
-; RV32XTHEADBB-NEXT:    neg a1, a1
-; RV32XTHEADBB-NEXT:    and a1, a1, a6
+; RV32XTHEADBB-NEXT:    srai a1, a6, 31
+; RV32XTHEADBB-NEXT:    and a1, a1, a7
 ; RV32XTHEADBB-NEXT:    or a1, a3, a1
 ; RV32XTHEADBB-NEXT:    or a0, a5, a0
 ; RV32XTHEADBB-NEXT:    ret
 ;
 ; RV64XTHEADBB-LABEL: rotl_64_zext:
 ; RV64XTHEADBB:       # %bb.0:
 ; RV64XTHEADBB-NEXT:    sll a2, a0, a1
 ; RV64XTHEADBB-NEXT:    neg a1, a1
 ; RV64XTHEADBB-NEXT:    srl a0, a0, a1
 ; RV64XTHEADBB-NEXT:    or a0, a2, a0
 ; RV64XTHEADBB-NEXT:    ret
   %z = sub i32 64, %y
   %zext = zext i32 %z to i64
   %zexty = zext i32 %y to i64
   %b = shl i64 %x, %zexty
   %c = lshr i64 %x, %zext
   %d = or i64 %b, %c
   ret i64 %d
 }
 
 define i64 @rotr_64_zext(i64 %x, i32 %y) nounwind {
 ; RV32I-LABEL: rotr_64_zext:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    neg a4, a2
+; RV32I-NEXT:    addi a6, a2, -32
 ; RV32I-NEXT:    srl a5, a1, a2
-; RV32I-NEXT:    addi a3, a2, -32
-; RV32I-NEXT:    slti a6, a3, 0
-; RV32I-NEXT:    neg a6, a6
-; RV32I-NEXT:    bltz a3, .LBB25_2
+; RV32I-NEXT:    bltz a6, .LBB25_2
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    mv a3, a5
 ; RV32I-NEXT:    j .LBB25_3
 ; RV32I-NEXT:  .LBB25_2:
 ; RV32I-NEXT:    srl a3, a0, a2
 ; RV32I-NEXT:    not a7, a2
 ; RV32I-NEXT:    slli t0, a1, 1
 ; RV32I-NEXT:    sll a7, t0, a7
 ; RV32I-NEXT:    or a3, a3, a7
 ; RV32I-NEXT:  .LBB25_3:
+; RV32I-NEXT:    srai a6, a6, 31
 ; RV32I-NEXT:    and a5, a6, a5
 ; RV32I-NEXT:    li a6, 32
-; RV32I-NEXT:    sub a7, a6, a2
-; RV32I-NEXT:    sll a6, a0, a4
-; RV32I-NEXT:    bltz a7, .LBB25_5
+; RV32I-NEXT:    sub a6, a6, a2
+; RV32I-NEXT:    sll a7, a0, a4
+; RV32I-NEXT:    bltz a6, .LBB25_5
 ; RV32I-NEXT:  # %bb.4:
-; RV32I-NEXT:    mv a1, a6
+; RV32I-NEXT:    mv a1, a7
 ; RV32I-NEXT:    j .LBB25_6
 ; RV32I-NEXT:  .LBB25_5:
 ; RV32I-NEXT:    li t0, 64
 ; RV32I-NEXT:    sub a2, t0, a2
 ; RV32I-NEXT:    sll a1, a1, a4
 ; RV32I-NEXT:    not a2, a2
 ; RV32I-NEXT:    srli a0, a0, 1
 ; RV32I-NEXT:    srl a0, a0, a2
 ; RV32I-NEXT:    or a1, a1, a0
 ; RV32I-NEXT:  .LBB25_6:
-; RV32I-NEXT:    slti a0, a7, 0
-; RV32I-NEXT:    neg a0, a0
-; RV32I-NEXT:    and a0, a0, a6
+; RV32I-NEXT:    srai a0, a6, 31
+; RV32I-NEXT:    and a0, a0, a7
 ; RV32I-NEXT:    or a0, a3, a0
 ; RV32I-NEXT:    or a1, a5, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: rotr_64_zext:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    negw a2, a1
 ; RV64I-NEXT:    srl a1, a0, a1
 ; RV64I-NEXT:    sll a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV32ZBB-LABEL: rotr_64_zext:
 ; RV32ZBB:       # %bb.0:
 ; RV32ZBB-NEXT:    neg a4, a2
+; RV32ZBB-NEXT:    addi a6, a2, -32
 ; RV32ZBB-NEXT:    srl a5, a1, a2
-; RV32ZBB-NEXT:    addi a3, a2, -32
-; RV32ZBB-NEXT:    slti a6, a3, 0
-; RV32ZBB-NEXT:    neg a6, a6
-; RV32ZBB-NEXT:    bltz a3, .LBB25_2
+; RV32ZBB-NEXT:    bltz a6, .LBB25_2
 ; RV32ZBB-NEXT:  # %bb.1:
 ; RV32ZBB-NEXT:    mv a3, a5
 ; RV32ZBB-NEXT:    j .LBB25_3
 ; RV32ZBB-NEXT:  .LBB25_2:
 ; RV32ZBB-NEXT:    srl a3, a0, a2
 ; RV32ZBB-NEXT:    not a7, a2
 ; RV32ZBB-NEXT:    slli t0, a1, 1
 ; RV32ZBB-NEXT:    sll a7, t0, a7
 ; RV32ZBB-NEXT:    or a3, a3, a7
 ; RV32ZBB-NEXT:  .LBB25_3:
+; RV32ZBB-NEXT:    srai a6, a6, 31
 ; RV32ZBB-NEXT:    and a5, a6, a5
 ; RV32ZBB-NEXT:    li a6, 32
-; RV32ZBB-NEXT:    sub a7, a6, a2
-; RV32ZBB-NEXT:    sll a6, a0, a4
-; RV32ZBB-NEXT:    bltz a7, .LBB25_5
+; RV32ZBB-NEXT:    sub a6, a6, a2
+; RV32ZBB-NEXT:    sll a7, a0, a4
+; RV32ZBB-NEXT:    bltz a6, .LBB25_5
 ; RV32ZBB-NEXT:  # %bb.4:
-; RV32ZBB-NEXT:    mv a1, a6
+; RV32ZBB-NEXT:    mv a1, a7
 ; RV32ZBB-NEXT:    j .LBB25_6
 ; RV32ZBB-NEXT:  .LBB25_5:
 ; RV32ZBB-NEXT:    li t0, 64
 ; RV32ZBB-NEXT:    sub a2, t0, a2
 ; RV32ZBB-NEXT:    sll a1, a1, a4
 ; RV32ZBB-NEXT:    not a2, a2
 ; RV32ZBB-NEXT:    srli a0, a0, 1
 ; RV32ZBB-NEXT:    srl a0, a0, a2
 ; RV32ZBB-NEXT:    or a1, a1, a0
 ; RV32ZBB-NEXT:  .LBB25_6:
-; RV32ZBB-NEXT:    slti a0, a7, 0
-; RV32ZBB-NEXT:    neg a0, a0
-; RV32ZBB-NEXT:    and a0, a0, a6
+; RV32ZBB-NEXT:    srai a0, a6, 31
+; RV32ZBB-NEXT:    and a0, a0, a7
 ; RV32ZBB-NEXT:    or a0, a3, a0
 ; RV32ZBB-NEXT:    or a1, a5, a1
 ; RV32ZBB-NEXT:    ret
 ;
 ; RV64ZBB-LABEL: rotr_64_zext:
 ; RV64ZBB:       # %bb.0:
 ; RV64ZBB-NEXT:    ror a0, a0, a1
 ; RV64ZBB-NEXT:    ret
 ;
 ; RV32XTHEADBB-LABEL: rotr_64_zext:
 ; RV32XTHEADBB:       # %bb.0:
 ; RV32XTHEADBB-NEXT:    neg a4, a2
+; RV32XTHEADBB-NEXT:    addi a6, a2, -32
 ; RV32XTHEADBB-NEXT:    srl a5, a1, a2
-; RV32XTHEADBB-NEXT:    addi a3, a2, -32
-; RV32XTHEADBB-NEXT:    slti a6, a3, 0
-; RV32XTHEADBB-NEXT:    neg a6, a6
-; RV32XTHEADBB-NEXT:    bltz a3, .LBB25_2
+; RV32XTHEADBB-NEXT:    bltz a6, .LBB25_2
 ; RV32XTHEADBB-NEXT:  # %bb.1:
 ; RV32XTHEADBB-NEXT:    mv a3, a5
 ; RV32XTHEADBB-NEXT:    j .LBB25_3
 ; RV32XTHEADBB-NEXT:  .LBB25_2:
 ; RV32XTHEADBB-NEXT:    srl a3, a0, a2
 ; RV32XTHEADBB-NEXT:    not a7, a2
 ; RV32XTHEADBB-NEXT:    slli t0, a1, 1
 ; RV32XTHEADBB-NEXT:    sll a7, t0, a7
 ; RV32XTHEADBB-NEXT:    or a3, a3, a7
 ; RV32XTHEADBB-NEXT:  .LBB25_3:
+; RV32XTHEADBB-NEXT:    srai a6, a6, 31
 ; RV32XTHEADBB-NEXT:    and a5, a6, a5
 ; RV32XTHEADBB-NEXT:    li a6, 32
-; RV32XTHEADBB-NEXT:    sub a7, a6, a2
-; RV32XTHEADBB-NEXT:    sll a6, a0, a4
-; RV32XTHEADBB-NEXT:    bltz a7, .LBB25_5
+; RV32XTHEADBB-NEXT:    sub a6, a6, a2
+; RV32XTHEADBB-NEXT:    sll a7, a0, a4
+; RV32XTHEADBB-NEXT:    bltz a6, .LBB25_5
 ; RV32XTHEADBB-NEXT:  # %bb.4:
-; RV32XTHEADBB-NEXT:    mv a1, a6
+; RV32XTHEADBB-NEXT:    mv a1, a7
 ; RV32XTHEADBB-NEXT:    j .LBB25_6
 ; RV32XTHEADBB-NEXT:  .LBB25_5:
 ; RV32XTHEADBB-NEXT:    li t0, 64
 ; RV32XTHEADBB-NEXT:    sub a2, t0, a2
 ; RV32XTHEADBB-NEXT:    sll a1, a1, a4
 ; RV32XTHEADBB-NEXT:    not a2, a2
 ; RV32XTHEADBB-NEXT:    srli a0, a0, 1
 ; RV32XTHEADBB-NEXT:    srl a0, a0, a2
 ; RV32XTHEADBB-NEXT:    or a1, a1, a0
 ; RV32XTHEADBB-NEXT:  .LBB25_6:
-; RV32XTHEADBB-NEXT:    slti a0, a7, 0
-; RV32XTHEADBB-NEXT:    neg a0, a0
-; RV32XTHEADBB-NEXT:    and a0, a0, a6
+; RV32XTHEADBB-NEXT:    srai a0, a6, 31
+; RV32XTHEADBB-NEXT:    and a0, a0, a7
 ; RV32XTHEADBB-NEXT:    or a0, a3, a0
 ; RV32XTHEADBB-NEXT:    or a1, a5, a1
 ; RV32XTHEADBB-NEXT:    ret
 ;
 ; RV64XTHEADBB-LABEL: rotr_64_zext:
 ; RV64XTHEADBB:       # %bb.0:
 ; RV64XTHEADBB-NEXT:    srl a2, a0, a1
 ; RV64XTHEADBB-NEXT:    neg a1, a1

llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll

 ; CHECK-NOV-NEXT:    bgez s1, .LBB45_18
 ; CHECK-NOV-NEXT:  .LBB45_4: # %entry
 ; CHECK-NOV-NEXT:    bgeu s0, a3, .LBB45_19
 ; CHECK-NOV-NEXT:  .LBB45_5: # %entry
 ; CHECK-NOV-NEXT:    beqz s1, .LBB45_7
 ; CHECK-NOV-NEXT:  .LBB45_6: # %entry
 ; CHECK-NOV-NEXT:    mv s0, a4
 ; CHECK-NOV-NEXT:  .LBB45_7: # %entry
-; CHECK-NOV-NEXT:    slti a6, a1, 0
-; CHECK-NOV-NEXT:    slti a3, s1, 0
-; CHECK-NOV-NEXT:    neg a4, a3
+; CHECK-NOV-NEXT:    srai a4, s1, 63
 ; CHECK-NOV-NEXT:    and a4, a4, s1
 ; CHECK-NOV-NEXT:    slli a3, a0, 63
 ; CHECK-NOV-NEXT:    mv a5, s0
 ; CHECK-NOV-NEXT:    bltz a4, .LBB45_20
 ; CHECK-NOV-NEXT:  # %bb.8: # %entry
-; CHECK-NOV-NEXT:    neg a6, a6
+; CHECK-NOV-NEXT:    srai a6, a1, 63
 ; CHECK-NOV-NEXT:    bgeu a3, s0, .LBB45_21
 ; CHECK-NOV-NEXT:  .LBB45_9: # %entry
 ; CHECK-NOV-NEXT:    and a1, a6, a1
 ; CHECK-NOV-NEXT:    bne a4, a0, .LBB45_22
 ; CHECK-NOV-NEXT:  .LBB45_10: # %entry
 ; CHECK-NOV-NEXT:    mv a4, a2
 ; CHECK-NOV-NEXT:    bltz a1, .LBB45_23
 ; CHECK-NOV-NEXT:  .LBB45_11: # %entry

 ; CHECK-NOV-NEXT:    mv a4, a3
 ; CHECK-NOV-NEXT:    bltu s0, a3, .LBB45_5
 ; CHECK-NOV-NEXT:  .LBB45_19: # %entry
 ; CHECK-NOV-NEXT:    mv s0, a3
 ; CHECK-NOV-NEXT:    bnez s1, .LBB45_6
 ; CHECK-NOV-NEXT:    j .LBB45_7
 ; CHECK-NOV-NEXT:  .LBB45_20: # %entry
 ; CHECK-NOV-NEXT:    mv a5, a3
-; CHECK-NOV-NEXT:    neg a6, a6
+; CHECK-NOV-NEXT:    srai a6, a1, 63
 ; CHECK-NOV-NEXT:    bltu a3, s0, .LBB45_9
 ; CHECK-NOV-NEXT:  .LBB45_21: # %entry
 ; CHECK-NOV-NEXT:    mv s0, a3
 ; CHECK-NOV-NEXT:    and a1, a6, a1
 ; CHECK-NOV-NEXT:    beq a4, a0, .LBB45_10
 ; CHECK-NOV-NEXT:  .LBB45_22: # %entry
 ; CHECK-NOV-NEXT:    mv s0, a5
 ; CHECK-NOV-NEXT:    mv a4, a2

 ; CHECK-V-NEXT:    bgez a1, .LBB45_18
 ; CHECK-V-NEXT:  .LBB45_4: # %entry
 ; CHECK-V-NEXT:    bgeu a0, a3, .LBB45_19
 ; CHECK-V-NEXT:  .LBB45_5: # %entry
 ; CHECK-V-NEXT:    beqz a1, .LBB45_7
 ; CHECK-V-NEXT:  .LBB45_6: # %entry
 ; CHECK-V-NEXT:    mv a0, a4
 ; CHECK-V-NEXT:  .LBB45_7: # %entry
-; CHECK-V-NEXT:    slti a3, s1, 0
-; CHECK-V-NEXT:    neg a4, a3
+; CHECK-V-NEXT:    srai a4, s1, 63
 ; CHECK-V-NEXT:    and a4, a4, s1
-; CHECK-V-NEXT:    slti a6, a1, 0
 ; CHECK-V-NEXT:    slli a3, a2, 63
 ; CHECK-V-NEXT:    mv a5, s0
 ; CHECK-V-NEXT:    bltz a4, .LBB45_20
 ; CHECK-V-NEXT:  # %bb.8: # %entry
-; CHECK-V-NEXT:    neg a6, a6
+; CHECK-V-NEXT:    srai a6, a1, 63
 ; CHECK-V-NEXT:    bgeu a3, s0, .LBB45_21
 ; CHECK-V-NEXT:  .LBB45_9: # %entry
 ; CHECK-V-NEXT:    and a1, a6, a1
 ; CHECK-V-NEXT:    bne a4, a2, .LBB45_22
 ; CHECK-V-NEXT:  .LBB45_10: # %entry
 ; CHECK-V-NEXT:    mv a4, a0
 ; CHECK-V-NEXT:    bltz a1, .LBB45_23
 ; CHECK-V-NEXT:  .LBB45_11: # %entry

 ; CHECK-V-NEXT:    mv a4, a3
 ; CHECK-V-NEXT:    bltu a0, a3, .LBB45_5
 ; CHECK-V-NEXT:  .LBB45_19: # %entry
 ; CHECK-V-NEXT:    mv a0, a3
 ; CHECK-V-NEXT:    bnez a1, .LBB45_6
 ; CHECK-V-NEXT:    j .LBB45_7
 ; CHECK-V-NEXT:  .LBB45_20: # %entry
 ; CHECK-V-NEXT:    mv a5, a3
-; CHECK-V-NEXT:    neg a6, a6
+; CHECK-V-NEXT:    srai a6, a1, 63
 ; CHECK-V-NEXT:    bltu a3, s0, .LBB45_9
 ; CHECK-V-NEXT:  .LBB45_21: # %entry
 ; CHECK-V-NEXT:    mv s0, a3
 ; CHECK-V-NEXT:    and a1, a6, a1
 ; CHECK-V-NEXT:    beq a4, a2, .LBB45_10
 ; CHECK-V-NEXT:  .LBB45_22: # %entry
 ; CHECK-V-NEXT:    mv s0, a5
 ; CHECK-V-NEXT:    mv a4, a0

 ; CHECK-NOV-NEXT:    bgez s1, .LBB48_18
 ; CHECK-NOV-NEXT:  .LBB48_4: # %entry
 ; CHECK-NOV-NEXT:    bgeu s0, a3, .LBB48_19
 ; CHECK-NOV-NEXT:  .LBB48_5: # %entry
 ; CHECK-NOV-NEXT:    beqz s1, .LBB48_7
 ; CHECK-NOV-NEXT:  .LBB48_6: # %entry
 ; CHECK-NOV-NEXT:    mv s0, a4
 ; CHECK-NOV-NEXT:  .LBB48_7: # %entry
-; CHECK-NOV-NEXT:    slti a6, a1, 0
-; CHECK-NOV-NEXT:    slti a3, s1, 0
-; CHECK-NOV-NEXT:    neg a4, a3
+; CHECK-NOV-NEXT:    srai a4, s1, 63
 ; CHECK-NOV-NEXT:    and a4, a4, s1
 ; CHECK-NOV-NEXT:    slli a3, a0, 63
 ; CHECK-NOV-NEXT:    mv a5, s0
 ; CHECK-NOV-NEXT:    bltz a4, .LBB48_20
 ; CHECK-NOV-NEXT:  # %bb.8: # %entry
-; CHECK-NOV-NEXT:    neg a6, a6
+; CHECK-NOV-NEXT:    srai a6, a1, 63
 ; CHECK-NOV-NEXT:    bgeu a3, s0, .LBB48_21
 ; CHECK-NOV-NEXT:  .LBB48_9: # %entry
 ; CHECK-NOV-NEXT:    and a1, a6, a1
 ; CHECK-NOV-NEXT:    bne a4, a0, .LBB48_22
 ; CHECK-NOV-NEXT:  .LBB48_10: # %entry
 ; CHECK-NOV-NEXT:    mv a4, a2
 ; CHECK-NOV-NEXT:    bltz a1, .LBB48_23
 ; CHECK-NOV-NEXT:  .LBB48_11: # %entry

 ; CHECK-NOV-NEXT:    mv a4, a3
 ; CHECK-NOV-NEXT:    bltu s0, a3, .LBB48_5
 ; CHECK-NOV-NEXT:  .LBB48_19: # %entry
 ; CHECK-NOV-NEXT:    mv s0, a3
 ; CHECK-NOV-NEXT:    bnez s1, .LBB48_6
 ; CHECK-NOV-NEXT:    j .LBB48_7
 ; CHECK-NOV-NEXT:  .LBB48_20: # %entry
 ; CHECK-NOV-NEXT:    mv a5, a3
-; CHECK-NOV-NEXT:    neg a6, a6
+; CHECK-NOV-NEXT:    srai a6, a1, 63
 ; CHECK-NOV-NEXT:    bltu a3, s0, .LBB48_9
 ; CHECK-NOV-NEXT:  .LBB48_21: # %entry
 ; CHECK-NOV-NEXT:    mv s0, a3
 ; CHECK-NOV-NEXT:    and a1, a6, a1
 ; CHECK-NOV-NEXT:    beq a4, a0, .LBB48_10
 ; CHECK-NOV-NEXT:  .LBB48_22: # %entry
 ; CHECK-NOV-NEXT:    mv s0, a5
 ; CHECK-NOV-NEXT:    mv a4, a2

 ; CHECK-V-NEXT:    bgez a1, .LBB48_18
 ; CHECK-V-NEXT:  .LBB48_4: # %entry
 ; CHECK-V-NEXT:    bgeu a0, a3, .LBB48_19
 ; CHECK-V-NEXT:  .LBB48_5: # %entry
 ; CHECK-V-NEXT:    beqz a1, .LBB48_7
 ; CHECK-V-NEXT:  .LBB48_6: # %entry
 ; CHECK-V-NEXT:    mv a0, a4
 ; CHECK-V-NEXT:  .LBB48_7: # %entry
-; CHECK-V-NEXT:    slti a3, s1, 0
-; CHECK-V-NEXT:    neg a4, a3
+; CHECK-V-NEXT:    srai a4, s1, 63
 ; CHECK-V-NEXT:    and a4, a4, s1
-; CHECK-V-NEXT:    slti a6, a1, 0
 ; CHECK-V-NEXT:    slli a3, a2, 63
 ; CHECK-V-NEXT:    mv a5, s0
 ; CHECK-V-NEXT:    bltz a4, .LBB48_20
 ; CHECK-V-NEXT:  # %bb.8: # %entry
-; CHECK-V-NEXT:    neg a6, a6
+; CHECK-V-NEXT:    srai a6, a1, 63
 ; CHECK-V-NEXT:    bgeu a3, s0, .LBB48_21
 ; CHECK-V-NEXT:  .LBB48_9: # %entry
 ; CHECK-V-NEXT:    and a1, a6, a1
 ; CHECK-V-NEXT:    bne a4, a2, .LBB48_22
 ; CHECK-V-NEXT:  .LBB48_10: # %entry
 ; CHECK-V-NEXT:    mv a4, a0
 ; CHECK-V-NEXT:    bltz a1, .LBB48_23
 ; CHECK-V-NEXT:  .LBB48_11: # %entry

 ; CHECK-V-NEXT:    mv a4, a3
 ; CHECK-V-NEXT:    bltu a0, a3, .LBB48_5
 ; CHECK-V-NEXT:  .LBB48_19: # %entry
 ; CHECK-V-NEXT:    mv a0, a3
 ; CHECK-V-NEXT:    bnez a1, .LBB48_6
 ; CHECK-V-NEXT:    j .LBB48_7
 ; CHECK-V-NEXT:  .LBB48_20: # %entry
 ; CHECK-V-NEXT:    mv a5, a3
-; CHECK-V-NEXT:    neg a6, a6
+; CHECK-V-NEXT:    srai a6, a1, 63
 ; CHECK-V-NEXT:    bltu a3, s0, .LBB48_9
 ; CHECK-V-NEXT:  .LBB48_21: # %entry
 ; CHECK-V-NEXT:    mv s0, a3
 ; CHECK-V-NEXT:    and a1, a6, a1
 ; CHECK-V-NEXT:    beq a4, a2, .LBB48_10
 ; CHECK-V-NEXT:  .LBB48_22: # %entry
 ; CHECK-V-NEXT:    mv s0, a5
 ; CHECK-V-NEXT:    mv a4, a0

 ; CHECK-NOV-NEXT:    bgez s1, .LBB51_18
 ; CHECK-NOV-NEXT:  .LBB51_4: # %entry
 ; CHECK-NOV-NEXT:    bgeu s0, a3, .LBB51_19
 ; CHECK-NOV-NEXT:  .LBB51_5: # %entry
 ; CHECK-NOV-NEXT:    beqz s1, .LBB51_7
 ; CHECK-NOV-NEXT:  .LBB51_6: # %entry
 ; CHECK-NOV-NEXT:    mv s0, a4
 ; CHECK-NOV-NEXT:  .LBB51_7: # %entry
-; CHECK-NOV-NEXT:    slti a6, a1, 0
-; CHECK-NOV-NEXT:    slti a3, s1, 0
-; CHECK-NOV-NEXT:    neg a4, a3
+; CHECK-NOV-NEXT:    srai a4, s1, 63
 ; CHECK-NOV-NEXT:    and a4, a4, s1
 ; CHECK-NOV-NEXT:    slli a3, a0, 63
 ; CHECK-NOV-NEXT:    mv a5, s0
 ; CHECK-NOV-NEXT:    bltz a4, .LBB51_20
 ; CHECK-NOV-NEXT:  # %bb.8: # %entry
-; CHECK-NOV-NEXT:    neg a6, a6
+; CHECK-NOV-NEXT:    srai a6, a1, 63
 ; CHECK-NOV-NEXT:    bgeu a3, s0, .LBB51_21
 ; CHECK-NOV-NEXT:  .LBB51_9: # %entry
 ; CHECK-NOV-NEXT:    and a1, a6, a1
 ; CHECK-NOV-NEXT:    bne a4, a0, .LBB51_22
 ; CHECK-NOV-NEXT:  .LBB51_10: # %entry
 ; CHECK-NOV-NEXT:    mv a4, a2
 ; CHECK-NOV-NEXT:    bltz a1, .LBB51_23
 ; CHECK-NOV-NEXT:  .LBB51_11: # %entry

 ; CHECK-NOV-NEXT:    mv a4, a3
 ; CHECK-NOV-NEXT:    bltu s0, a3, .LBB51_5
 ; CHECK-NOV-NEXT:  .LBB51_19: # %entry
 ; CHECK-NOV-NEXT:    mv s0, a3
 ; CHECK-NOV-NEXT:    bnez s1, .LBB51_6
 ; CHECK-NOV-NEXT:    j .LBB51_7
 ; CHECK-NOV-NEXT:  .LBB51_20: # %entry
 ; CHECK-NOV-NEXT:    mv a5, a3
-; CHECK-NOV-NEXT:    neg a6, a6
+; CHECK-NOV-NEXT:    srai a6, a1, 63
 ; CHECK-NOV-NEXT:    bltu a3, s0, .LBB51_9
 ; CHECK-NOV-NEXT:  .LBB51_21: # %entry
 ; CHECK-NOV-NEXT:    mv s0, a3
 ; CHECK-NOV-NEXT:    and a1, a6, a1
 ; CHECK-NOV-NEXT:    beq a4, a0, .LBB51_10
 ; CHECK-NOV-NEXT:  .LBB51_22: # %entry
 ; CHECK-NOV-NEXT:    mv s0, a5
 ; CHECK-NOV-NEXT:    mv a4, a2

 ; CHECK-V-NEXT:    bgez s1, .LBB51_18
 ; CHECK-V-NEXT:  .LBB51_4: # %entry
 ; CHECK-V-NEXT:    bgeu s0, a3, .LBB51_19
 ; CHECK-V-NEXT:  .LBB51_5: # %entry
 ; CHECK-V-NEXT:    beqz s1, .LBB51_7
 ; CHECK-V-NEXT:  .LBB51_6: # %entry
 ; CHECK-V-NEXT:    mv s0, a4
 ; CHECK-V-NEXT:  .LBB51_7: # %entry
-; CHECK-V-NEXT:    slti a6, a1, 0
-; CHECK-V-NEXT:    slti a3, s1, 0
-; CHECK-V-NEXT:    neg a4, a3
+; CHECK-V-NEXT:    srai a4, s1, 63
 ; CHECK-V-NEXT:    and a4, a4, s1
 ; CHECK-V-NEXT:    slli a3, a2, 63
 ; CHECK-V-NEXT:    mv a5, s0
 ; CHECK-V-NEXT:    bltz a4, .LBB51_20
 ; CHECK-V-NEXT:  # %bb.8: # %entry
-; CHECK-V-NEXT:    neg a6, a6
+; CHECK-V-NEXT:    srai a6, a1, 63
 ; CHECK-V-NEXT:    bgeu a3, s0, .LBB51_21
 ; CHECK-V-NEXT:  .LBB51_9: # %entry
 ; CHECK-V-NEXT:    and a1, a6, a1
 ; CHECK-V-NEXT:    bne a4, a2, .LBB51_22
 ; CHECK-V-NEXT:  .LBB51_10: # %entry
 ; CHECK-V-NEXT:    mv a4, a0
 ; CHECK-V-NEXT:    bltz a1, .LBB51_23
 ; CHECK-V-NEXT:  .LBB51_11: # %entry

 ; CHECK-V-NEXT:    mv a4, a3
 ; CHECK-V-NEXT:    bltu s0, a3, .LBB51_5
 ; CHECK-V-NEXT:  .LBB51_19: # %entry
 ; CHECK-V-NEXT:    mv s0, a3
 ; CHECK-V-NEXT:    bnez s1, .LBB51_6
 ; CHECK-V-NEXT:    j .LBB51_7
 ; CHECK-V-NEXT:  .LBB51_20: # %entry
 ; CHECK-V-NEXT:    mv a5, a3
-; CHECK-V-NEXT:    neg a6, a6
+; CHECK-V-NEXT:    srai a6, a1, 63
 ; CHECK-V-NEXT:    bltu a3, s0, .LBB51_9
 ; CHECK-V-NEXT:  .LBB51_21: # %entry
 ; CHECK-V-NEXT:    mv s0, a3
 ; CHECK-V-NEXT:    and a1, a6, a1
 ; CHECK-V-NEXT:    beq a4, a2, .LBB51_10
 ; CHECK-V-NEXT:  .LBB51_22: # %entry
 ; CHECK-V-NEXT:    mv s0, a5
 ; CHECK-V-NEXT:    mv a4, a0

llvm/test/CodeGen/RISCV/shift-amount-mod.ll

; RV64I-NEXT:    ret
   %b = shl i32 %x, %a
   ret i32 %b
 }
 
 define i64 @shl_by_complemented_64(i64 %x) {
 ; RV32I-LABEL: shl_by_complemented_64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    not a4, a0
-; RV32I-NEXT:    li a3, 31
-; RV32I-NEXT:    sub a3, a3, a0
-; RV32I-NEXT:    sll a2, a0, a4
-; RV32I-NEXT:    bltz a3, .LBB1_2
+; RV32I-NEXT:    li a2, 31
+; RV32I-NEXT:    sub a2, a2, a0
+; RV32I-NEXT:    sll a3, a0, a4
+; RV32I-NEXT:    bltz a2, .LBB1_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv a1, a2
+; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:    j .LBB1_3
 ; RV32I-NEXT:  .LBB1_2:
 ; RV32I-NEXT:    sll a1, a1, a4
 ; RV32I-NEXT:    li a4, 63
 ; RV32I-NEXT:    sub a4, a4, a0
 ; RV32I-NEXT:    not a4, a4
 ; RV32I-NEXT:    srli a0, a0, 1
 ; RV32I-NEXT:    srl a0, a0, a4
 ; RV32I-NEXT:    or a1, a1, a0
 ; RV32I-NEXT:  .LBB1_3:
-; RV32I-NEXT:    slti a0, a3, 0
-; RV32I-NEXT:    neg a0, a0
-; RV32I-NEXT:    and a0, a0, a2
+; RV32I-NEXT:    srai a0, a2, 31
+; RV32I-NEXT:    and a0, a0, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: shl_by_complemented_64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    not a1, a0
 ; RV64I-NEXT:    sll a0, a0, a1
 ; RV64I-NEXT:    ret
   %a = sub i64 63, %x
; RV64I-NEXT:    ret
   %b = lshr i32 %x, %a
   ret i32 %b
 }
 
 define i64 @lshr_by_complemented_64(i64 %x) {
 ; RV32I-LABEL: lshr_by_complemented_64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    not a4, a0
-; RV32I-NEXT:    li a3, 31
-; RV32I-NEXT:    sub a3, a3, a0
-; RV32I-NEXT:    srl a2, a1, a4
-; RV32I-NEXT:    bltz a3, .LBB3_2
+; RV32I-NEXT:    li a2, 31
+; RV32I-NEXT:    sub a2, a2, a0
+; RV32I-NEXT:    srl a3, a1, a4
+; RV32I-NEXT:    bltz a2, .LBB3_2
 ; RV32I-NEXT:  # %bb.1:
-; RV32I-NEXT:    mv a0, a2
+; RV32I-NEXT:    mv a0, a3
 ; RV32I-NEXT:    j .LBB3_3
 ; RV32I-NEXT:  .LBB3_2:
 ; RV32I-NEXT:    srl a4, a0, a4
 ; RV32I-NEXT:    li a5, 63
 ; RV32I-NEXT:    sub a5, a5, a0
 ; RV32I-NEXT:    not a0, a5
 ; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    sll a0, a1, a0
 ; RV32I-NEXT:    or a0, a4, a0
 ; RV32I-NEXT:  .LBB3_3:
-; RV32I-NEXT:    slti a1, a3, 0
-; RV32I-NEXT:    neg a1, a1
-; RV32I-NEXT:    and a1, a1, a2
+; RV32I-NEXT:    srai a1, a2, 31
+; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: lshr_by_complemented_64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    not a1, a0
 ; RV64I-NEXT:    srl a0, a0, a1
 ; RV64I-NEXT:    ret
   %a = sub i64 63, %x

 ; RV32I-NEXT:  .LBB7_2:
 ; RV32I-NEXT:    sll a1, a1, a3
 ; RV32I-NEXT:    not a4, a4
 ; RV32I-NEXT:    srli a5, a0, 1
 ; RV32I-NEXT:    srl a4, a5, a4
 ; RV32I-NEXT:    or a1, a1, a4
 ; RV32I-NEXT:  .LBB7_3:
 ; RV32I-NEXT:    sll a0, a0, a3
-; RV32I-NEXT:    slti a2, a2, 0
-; RV32I-NEXT:    neg a2, a2
+; RV32I-NEXT:    srai a2, a2, 31
 ; RV32I-NEXT:    and a0, a2, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: shl_by_masked_complemented_64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    not a1, a0
 ; RV64I-NEXT:    sll a0, a0, a1
 ; RV64I-NEXT:    ret

 ; RV32I-NEXT:  .LBB8_2:
 ; RV32I-NEXT:    srl a0, a0, a3
 ; RV32I-NEXT:    not a4, a4
 ; RV32I-NEXT:    slli a5, a1, 1
 ; RV32I-NEXT:    sll a4, a5, a4
 ; RV32I-NEXT:    or a0, a0, a4
 ; RV32I-NEXT:  .LBB8_3:
 ; RV32I-NEXT:    srl a1, a1, a3
-; RV32I-NEXT:    slti a2, a2, 0
-; RV32I-NEXT:    neg a2, a2
+; RV32I-NEXT:    srai a2, a2, 31
 ; RV32I-NEXT:    and a1, a2, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: lshr_by_masked_complemented_64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    not a1, a0
 ; RV64I-NEXT:    srl a0, a0, a1
 ; RV64I-NEXT:    ret

llvm/test/CodeGen/RISCV/shift-masked-shamt.ll

 ; RV32I-NEXT:  .LBB9_2:
 ; RV32I-NEXT:    sll a1, a1, a2
 ; RV32I-NEXT:    srli a5, a0, 1
 ; RV32I-NEXT:    not a4, a4
 ; RV32I-NEXT:    srl a4, a5, a4
 ; RV32I-NEXT:    or a1, a1, a4
 ; RV32I-NEXT:  .LBB9_3:
 ; RV32I-NEXT:    sll a0, a0, a2
-; RV32I-NEXT:    slti a2, a3, 0
-; RV32I-NEXT:    neg a2, a2
-; RV32I-NEXT:    and a0, a2, a0
+; RV32I-NEXT:    srai a3, a3, 31
+; RV32I-NEXT:    and a0, a3, a0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: sll_redundant_mask_zeros_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a1, 2
 ; RV64I-NEXT:    sll a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = shl i64 %b, 2

 ; RV32I-NEXT:  .LBB10_2:
 ; RV32I-NEXT:    srl a0, a0, a2
 ; RV32I-NEXT:    slli a5, a1, 1
 ; RV32I-NEXT:    not a4, a4
 ; RV32I-NEXT:    sll a4, a5, a4
 ; RV32I-NEXT:    or a0, a0, a4
 ; RV32I-NEXT:  .LBB10_3:
 ; RV32I-NEXT:    srl a1, a1, a2
-; RV32I-NEXT:    slti a2, a3, 0
-; RV32I-NEXT:    neg a2, a2
-; RV32I-NEXT:    and a1, a2, a1
+; RV32I-NEXT:    srai a3, a3, 31
+; RV32I-NEXT:    and a1, a3, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: srl_redundant_mask_zeros_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a1, 3
 ; RV64I-NEXT:    srl a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = shl i64 %b, 3

llvm/test/CodeGen/RISCV/shifts.ll

 ; RV32I-NEXT:    j .LBB0_3
 ; RV32I-NEXT:  .LBB0_2:
 ; RV32I-NEXT:    srl a0, a0, a2
 ; RV32I-NEXT:    not a2, a2
 ; RV32I-NEXT:    slli a1, a1, 1
 ; RV32I-NEXT:    sll a1, a1, a2
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:  .LBB0_3:
-; RV32I-NEXT:    slti a1, a4, 0
-; RV32I-NEXT:    neg a1, a1
+; RV32I-NEXT:    srai a1, a4, 31
 ; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: lshr64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srl a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = lshr i64 %a, %b

 ; RV32I-NEXT:    j .LBB4_3
 ; RV32I-NEXT:  .LBB4_2:
 ; RV32I-NEXT:    sll a1, a1, a2
 ; RV32I-NEXT:    not a2, a2
 ; RV32I-NEXT:    srli a0, a0, 1
 ; RV32I-NEXT:    srl a0, a0, a2
 ; RV32I-NEXT:    or a1, a1, a0
 ; RV32I-NEXT:  .LBB4_3:
-; RV32I-NEXT:    slti a0, a4, 0
-; RV32I-NEXT:    neg a0, a0
+; RV32I-NEXT:    srai a0, a4, 31
 ; RV32I-NEXT:    and a0, a0, a3
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: shl64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sll a0, a0, a1
 ; RV64I-NEXT:    ret
   %1 = shl i64 %a, %b

 ; RV64I-NEXT:    j .LBB6_3
 ; RV64I-NEXT:  .LBB6_2:
 ; RV64I-NEXT:    srl a0, a0, a2
 ; RV64I-NEXT:    not a2, a2
 ; RV64I-NEXT:    slli a1, a1, 1
 ; RV64I-NEXT:    sll a1, a1, a2
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:  .LBB6_3:
-; RV64I-NEXT:    slti a1, a4, 0
-; RV64I-NEXT:    neg a1, a1
+; RV64I-NEXT:    srai a1, a4, 63
 ; RV64I-NEXT:    and a1, a1, a3
 ; RV64I-NEXT:    ret
   %1 = lshr i128 %a, %b
   ret i128 %1
 }
 
 define i128 @ashr128(i128 %a, i128 %b) nounwind {
 ; RV32I-LABEL: ashr128:

 ; RV64I-NEXT:    j .LBB8_3
 ; RV64I-NEXT:  .LBB8_2:
 ; RV64I-NEXT:    sll a1, a1, a2
 ; RV64I-NEXT:    not a2, a2
 ; RV64I-NEXT:    srli a0, a0, 1
 ; RV64I-NEXT:    srl a0, a0, a2
 ; RV64I-NEXT:    or a1, a1, a0
 ; RV64I-NEXT:  .LBB8_3:
-; RV64I-NEXT:    slti a0, a4, 0
-; RV64I-NEXT:    neg a0, a0
+; RV64I-NEXT:    srai a0, a4, 63
 ; RV64I-NEXT:    and a0, a0, a3
 ; RV64I-NEXT:    ret
   %1 = shl i128 %a, %b
   ret i128 %1
 }
 
 define i64 @fshr64_minsize(i64 %a, i64 %b) minsize nounwind {
 ; RV32I-LABEL: fshr64_minsize:

llvm/test/CodeGen/RISCV/wide-scalar-shift-by-byte-multiple-legalization.ll

 ; RV32I-NEXT:    or a0, a0, t0
 ; RV32I-NEXT:    or a0, a0, a6
 ; RV32I-NEXT:    srl a0, a0, a5
 ; RV32I-NEXT:    slli a3, a3, 1
 ; RV32I-NEXT:    not a5, a5
 ; RV32I-NEXT:    sll a3, a3, a5
 ; RV32I-NEXT:    or a0, a0, a3
 ; RV32I-NEXT:  .LBB3_3:
-; RV32I-NEXT:    slti a3, a4, 0
-; RV32I-NEXT:    neg a3, a3
-; RV32I-NEXT:    and a1, a3, a1
+; RV32I-NEXT:    srai a4, a4, 31
+; RV32I-NEXT:    and a1, a4, a1
 ; RV32I-NEXT:    sb a1, 4(a2)
-; RV32I-NEXT:    sb a0, 0(a2)
 ; RV32I-NEXT:    srli a3, a1, 16
 ; RV32I-NEXT:    sb a3, 6(a2)
 ; RV32I-NEXT:    srli a3, a1, 24
 ; RV32I-NEXT:    sb a3, 7(a2)
 ; RV32I-NEXT:    srli a1, a1, 8
 ; RV32I-NEXT:    sb a1, 5(a2)
+; RV32I-NEXT:    sb a0, 0(a2)
 ; RV32I-NEXT:    srli a1, a0, 16
 ; RV32I-NEXT:    sb a1, 2(a2)
 ; RV32I-NEXT:    srli a1, a0, 24
 ; RV32I-NEXT:    sb a1, 3(a2)
 ; RV32I-NEXT:    srli a0, a0, 8
 ; RV32I-NEXT:    sb a0, 1(a2)
 ; RV32I-NEXT:    ret
   %src = load i64, ptr %src.ptr, align 1

 ; RV32I-NEXT:    or a0, a0, t0
 ; RV32I-NEXT:    or a0, a0, a6
 ; RV32I-NEXT:    sll a0, a0, a5
 ; RV32I-NEXT:    srli a3, a3, 1
 ; RV32I-NEXT:    not a5, a5
 ; RV32I-NEXT:    srl a3, a3, a5
 ; RV32I-NEXT:    or a0, a0, a3
 ; RV32I-NEXT:  .LBB4_3:
-; RV32I-NEXT:    slti a3, a4, 0
-; RV32I-NEXT:    neg a3, a3
-; RV32I-NEXT:    and a1, a3, a1
-; RV32I-NEXT:    sb a0, 4(a2)
+; RV32I-NEXT:    srai a4, a4, 31
+; RV32I-NEXT:    and a1, a4, a1
 ; RV32I-NEXT:    sb a1, 0(a2)
-; RV32I-NEXT:    srli a3, a0, 16
-; RV32I-NEXT:    sb a3, 6(a2)
-; RV32I-NEXT:    srli a3, a0, 24
-; RV32I-NEXT:    sb a3, 7(a2)
-; RV32I-NEXT:    srli a0, a0, 8
-; RV32I-NEXT:    sb a0, 5(a2)
-; RV32I-NEXT:    srli a0, a1, 16
-; RV32I-NEXT:    sb a0, 2(a2)
-; RV32I-NEXT:    srli a0, a1, 24
-; RV32I-NEXT:    sb a0, 3(a2)
+; RV32I-NEXT:    sb a0, 4(a2)
+; RV32I-NEXT:    srli a3, a1, 16
+; RV32I-NEXT:    sb a3, 2(a2)
+; RV32I-NEXT:    srli a3, a1, 24
+; RV32I-NEXT:    sb a3, 3(a2)
 ; RV32I-NEXT:    srli a1, a1, 8
 ; RV32I-NEXT:    sb a1, 1(a2)
+; RV32I-NEXT:    srli a1, a0, 16
+; RV32I-NEXT:    sb a1, 6(a2)
+; RV32I-NEXT:    srli a1, a0, 24
+; RV32I-NEXT:    sb a1, 7(a2)
+; RV32I-NEXT:    srli a0, a0, 8
+; RV32I-NEXT:    sb a0, 5(a2)
 ; RV32I-NEXT:    ret
   %src = load i64, ptr %src.ptr, align 1
   %byteOff = load i64, ptr %byteOff.ptr, align 1
   %bitOff = shl i64 %byteOff, 3
   %res = shl i64 %src, %bitOff
   store i64 %res, ptr %dst, align 1
   ret void
 }

 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    or a0, a0, a6
 ; RV64I-NEXT:    srl a0, a0, a5
 ; RV64I-NEXT:    not a5, a5
 ; RV64I-NEXT:    slli a3, a3, 1
 ; RV64I-NEXT:    sll a3, a3, a5
 ; RV64I-NEXT:    or a0, a0, a3
 ; RV64I-NEXT:  .LBB6_3:
-; RV64I-NEXT:    slti a3, a4, 0
-; RV64I-NEXT:    neg a3, a3
-; RV64I-NEXT:    and a1, a3, a1
+; RV64I-NEXT:    srai a4, a4, 63
+; RV64I-NEXT:    and a1, a4, a1
 ; RV64I-NEXT:    sb a1, 8(a2)
-; RV64I-NEXT:    sb a0, 0(a2)
 ; RV64I-NEXT:    srli a3, a1, 56
 ; RV64I-NEXT:    sb a3, 15(a2)
 ; RV64I-NEXT:    srli a3, a1, 48
 ; RV64I-NEXT:    sb a3, 14(a2)
 ; RV64I-NEXT:    srli a3, a1, 40
 ; RV64I-NEXT:    sb a3, 13(a2)
 ; RV64I-NEXT:    srli a3, a1, 32
 ; RV64I-NEXT:    sb a3, 12(a2)
 ; RV64I-NEXT:    srli a3, a1, 24
 ; RV64I-NEXT:    sb a3, 11(a2)
 ; RV64I-NEXT:    srli a3, a1, 16
 ; RV64I-NEXT:    sb a3, 10(a2)
 ; RV64I-NEXT:    srli a1, a1, 8
 ; RV64I-NEXT:    sb a1, 9(a2)
+; RV64I-NEXT:    sb a0, 0(a2)
 ; RV64I-NEXT:    srli a1, a0, 56
 ; RV64I-NEXT:    sb a1, 7(a2)
 ; RV64I-NEXT:    srli a1, a0, 48
 ; RV64I-NEXT:    sb a1, 6(a2)
 ; RV64I-NEXT:    srli a1, a0, 40
 ; RV64I-NEXT:    sb a1, 5(a2)
 ; RV64I-NEXT:    srli a1, a0, 32
 ; RV64I-NEXT:    sb a1, 4(a2)

 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    or a0, a0, a6
 ; RV64I-NEXT:    sll a0, a0, a5
 ; RV64I-NEXT:    not a5, a5
 ; RV64I-NEXT:    srli a3, a3, 1
 ; RV64I-NEXT:    srl a3, a3, a5
 ; RV64I-NEXT:    or a0, a0, a3
 ; RV64I-NEXT:  .LBB7_3:
-; RV64I-NEXT:    slti a3, a4, 0
-; RV64I-NEXT:    neg a3, a3
-; RV64I-NEXT:    and a1, a3, a1
-; RV64I-NEXT:    sb a0, 8(a2)
+; RV64I-NEXT:    srai a4, a4, 63
+; RV64I-NEXT:    and a1, a4, a1
 ; RV64I-NEXT:    sb a1, 0(a2)
-; RV64I-NEXT:    srli a3, a0, 56
-; RV64I-NEXT:    sb a3, 15(a2)
-; RV64I-NEXT:    srli a3, a0, 48
-; RV64I-NEXT:    sb a3, 14(a2)
-; RV64I-NEXT:    srli a3, a0, 40
-; RV64I-NEXT:    sb a3, 13(a2)
-; RV64I-NEXT:    srli a3, a0, 32
-; RV64I-NEXT:    sb a3, 12(a2)
-; RV64I-NEXT:    srli a3, a0, 24
-; RV64I-NEXT:    sb a3, 11(a2)
-; RV64I-NEXT:    srli a3, a0, 16
-; RV64I-NEXT:    sb a3, 10(a2)
-; RV64I-NEXT:    srli a0, a0, 8
-; RV64I-NEXT:    sb a0, 9(a2)
-; RV64I-NEXT:    srli a0, a1, 56
-; RV64I-NEXT:    sb a0, 7(a2)
-; RV64I-NEXT:    srli a0, a1, 48
-; RV64I-NEXT:    sb a0, 6(a2)
-; RV64I-NEXT:    srli a0, a1, 40
-; RV64I-NEXT:    sb a0, 5(a2)
-; RV64I-NEXT:    srli a0, a1, 32
-; RV64I-NEXT:    sb a0, 4(a2)
-; RV64I-NEXT:    srli a0, a1, 24
-; RV64I-NEXT:    sb a0, 3(a2)
-; RV64I-NEXT:    srli a0, a1, 16
-; RV64I-NEXT:    sb a0, 2(a2)
+; RV64I-NEXT:    sb a0, 8(a2)
+; RV64I-NEXT:    srli a3, a1, 56
+; RV64I-NEXT:    sb a3, 7(a2)
+; RV64I-NEXT:    srli a3, a1, 48
+; RV64I-NEXT:    sb a3, 6(a2)
+; RV64I-NEXT:    srli a3, a1, 40
+; RV64I-NEXT:    sb a3, 5(a2)
+; RV64I-NEXT:    srli a3, a1, 32
+; RV64I-NEXT:    sb a3, 4(a2)
+; RV64I-NEXT:    srli a3, a1, 24
+; RV64I-NEXT:    sb a3, 3(a2)
+; RV64I-NEXT:    srli a3, a1, 16
+; RV64I-NEXT:    sb a3, 2(a2)
 ; RV64I-NEXT:    srli a1, a1, 8
 ; RV64I-NEXT:    sb a1, 1(a2)
+; RV64I-NEXT:    srli a1, a0, 56
+; RV64I-NEXT:    sb a1, 15(a2)
+; RV64I-NEXT:    srli a1, a0, 48
+; RV64I-NEXT:    sb a1, 14(a2)
+; RV64I-NEXT:    srli a1, a0, 40
+; RV64I-NEXT:    sb a1, 13(a2)
+; RV64I-NEXT:    srli a1, a0, 32
+; RV64I-NEXT:    sb a1, 12(a2)
+; RV64I-NEXT:    srli a1, a0, 24
+; RV64I-NEXT:    sb a1, 11(a2)
+; RV64I-NEXT:    srli a1, a0, 16
+; RV64I-NEXT:    sb a1, 10(a2)
+; RV64I-NEXT:    srli a0, a0, 8
+; RV64I-NEXT:    sb a0, 9(a2)
 ; RV64I-NEXT:    ret
 ;
 ; RV32I-LABEL: shl_16bytes:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -48
 ; RV32I-NEXT:    sw s0, 44(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 40(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 36(sp) # 4-byte Folded Spill

llvm/test/CodeGen/RISCV/wide-scalar-shift-legalization.ll

 ; RV32I-NEXT:    or a0, a0, t0
 ; RV32I-NEXT:    or a0, a0, a6
 ; RV32I-NEXT:    srl a0, a0, a5
 ; RV32I-NEXT:    not a5, a5
 ; RV32I-NEXT:    slli a3, a3, 1
 ; RV32I-NEXT:    sll a3, a3, a5
 ; RV32I-NEXT:    or a0, a0, a3
 ; RV32I-NEXT:  .LBB3_3:
-; RV32I-NEXT:    slti a3, a4, 0
-; RV32I-NEXT:    neg a3, a3
-; RV32I-NEXT:    and a1, a3, a1
+; RV32I-NEXT:    srai a4, a4, 31
+; RV32I-NEXT:    and a1, a4, a1
 ; RV32I-NEXT:    sb a1, 4(a2)
-; RV32I-NEXT:    sb a0, 0(a2)
 ; RV32I-NEXT:    srli a3, a1, 16
 ; RV32I-NEXT:    sb a3, 6(a2)
 ; RV32I-NEXT:    srli a3, a1, 24
 ; RV32I-NEXT:    sb a3, 7(a2)
 ; RV32I-NEXT:    srli a1, a1, 8
 ; RV32I-NEXT:    sb a1, 5(a2)
+; RV32I-NEXT:    sb a0, 0(a2)
 ; RV32I-NEXT:    srli a1, a0, 16
 ; RV32I-NEXT:    sb a1, 2(a2)
 ; RV32I-NEXT:    srli a1, a0, 24
 ; RV32I-NEXT:    sb a1, 3(a2)
 ; RV32I-NEXT:    srli a0, a0, 8
 ; RV32I-NEXT:    sb a0, 1(a2)
 ; RV32I-NEXT:    ret
   %src = load i64, ptr %src.ptr, align 1

 ; RV32I-NEXT:    or a0, a0, t0
 ; RV32I-NEXT:    or a0, a0, a6
 ; RV32I-NEXT:    sll a0, a0, a5
 ; RV32I-NEXT:    not a5, a5
 ; RV32I-NEXT:    srli a3, a3, 1
 ; RV32I-NEXT:    srl a3, a3, a5
 ; RV32I-NEXT:    or a0, a0, a3
 ; RV32I-NEXT:  .LBB4_3:
-; RV32I-NEXT:    slti a3, a4, 0
-; RV32I-NEXT:    neg a3, a3
-; RV32I-NEXT:    and a1, a3, a1
-; RV32I-NEXT:    sb a0, 4(a2)
+; RV32I-NEXT:    srai a4, a4, 31
+; RV32I-NEXT:    and a1, a4, a1
 ; RV32I-NEXT:    sb a1, 0(a2)
-; RV32I-NEXT:    srli a3, a0, 16
-; RV32I-NEXT:    sb a3, 6(a2)
-; RV32I-NEXT:    srli a3, a0, 24
-; RV32I-NEXT:    sb a3, 7(a2)
-; RV32I-NEXT:    srli a0, a0, 8
-; RV32I-NEXT:    sb a0, 5(a2)
-; RV32I-NEXT:    srli a0, a1, 16
-; RV32I-NEXT:    sb a0, 2(a2)
-; RV32I-NEXT:    srli a0, a1, 24
-; RV32I-NEXT:    sb a0, 3(a2)
+; RV32I-NEXT:    sb a0, 4(a2)
+; RV32I-NEXT:    srli a3, a1, 16
+; RV32I-NEXT:    sb a3, 2(a2)
+; RV32I-NEXT:    srli a3, a1, 24
+; RV32I-NEXT:    sb a3, 3(a2)
 ; RV32I-NEXT:    srli a1, a1, 8
 ; RV32I-NEXT:    sb a1, 1(a2)
+; RV32I-NEXT:    srli a1, a0, 16
+; RV32I-NEXT:    sb a1, 6(a2)
+; RV32I-NEXT:    srli a1, a0, 24
+; RV32I-NEXT:    sb a1, 7(a2)
+; RV32I-NEXT:    srli a0, a0, 8
+; RV32I-NEXT:    sb a0, 5(a2)
 ; RV32I-NEXT:    ret
   %src = load i64, ptr %src.ptr, align 1
   %bitOff = load i64, ptr %bitOff.ptr, align 1
   %res = shl i64 %src, %bitOff
   store i64 %res, ptr %dst, align 1
   ret void
 }
 define void @ashr_8bytes(ptr %src.ptr, ptr %bitOff.ptr, ptr %dst) nounwind {

 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    or a0, a0, a6
 ; RV64I-NEXT:    srl a0, a0, a5
 ; RV64I-NEXT:    not a5, a5
 ; RV64I-NEXT:    slli a3, a3, 1
 ; RV64I-NEXT:    sll a3, a3, a5
 ; RV64I-NEXT:    or a0, a0, a3
 ; RV64I-NEXT:  .LBB6_3:
-; RV64I-NEXT:    slti a3, a4, 0
-; RV64I-NEXT:    neg a3, a3
-; RV64I-NEXT:    and a1, a3, a1
+; RV64I-NEXT:    srai a4, a4, 63
+; RV64I-NEXT:    and a1, a4, a1
 ; RV64I-NEXT:    sb a1, 8(a2)
-; RV64I-NEXT:    sb a0, 0(a2)
 ; RV64I-NEXT:    srli a3, a1, 56
 ; RV64I-NEXT:    sb a3, 15(a2)
 ; RV64I-NEXT:    srli a3, a1, 48
 ; RV64I-NEXT:    sb a3, 14(a2)
 ; RV64I-NEXT:    srli a3, a1, 40
 ; RV64I-NEXT:    sb a3, 13(a2)
 ; RV64I-NEXT:    srli a3, a1, 32
 ; RV64I-NEXT:    sb a3, 12(a2)
 ; RV64I-NEXT:    srli a3, a1, 24
 ; RV64I-NEXT:    sb a3, 11(a2)
 ; RV64I-NEXT:    srli a3, a1, 16
 ; RV64I-NEXT:    sb a3, 10(a2)
 ; RV64I-NEXT:    srli a1, a1, 8
 ; RV64I-NEXT:    sb a1, 9(a2)
+; RV64I-NEXT:    sb a0, 0(a2)
 ; RV64I-NEXT:    srli a1, a0, 56
 ; RV64I-NEXT:    sb a1, 7(a2)
 ; RV64I-NEXT:    srli a1, a0, 48
 ; RV64I-NEXT:    sb a1, 6(a2)
 ; RV64I-NEXT:    srli a1, a0, 40
 ; RV64I-NEXT:    sb a1, 5(a2)
 ; RV64I-NEXT:    srli a1, a0, 32
 ; RV64I-NEXT:    sb a1, 4(a2)

 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    or a0, a0, a6
 ; RV64I-NEXT:    sll a0, a0, a5
 ; RV64I-NEXT:    not a5, a5
 ; RV64I-NEXT:    srli a3, a3, 1
 ; RV64I-NEXT:    srl a3, a3, a5
 ; RV64I-NEXT:    or a0, a0, a3
 ; RV64I-NEXT:  .LBB7_3:
-; RV64I-NEXT:    slti a3, a4, 0
-; RV64I-NEXT:    neg a3, a3
-; RV64I-NEXT:    and a1, a3, a1
-; RV64I-NEXT:    sb a0, 8(a2)
+; RV64I-NEXT:    srai a4, a4, 63
+; RV64I-NEXT:    and a1, a4, a1
 ; RV64I-NEXT:    sb a1, 0(a2)
-; RV64I-NEXT:    srli a3, a0, 56
-; RV64I-NEXT:    sb a3, 15(a2)
-; RV64I-NEXT:    srli a3, a0, 48
-; RV64I-NEXT:    sb a3, 14(a2)
-; RV64I-NEXT:    srli a3, a0, 40
-; RV64I-NEXT:    sb a3, 13(a2)
-; RV64I-NEXT:    srli a3, a0, 32
-; RV64I-NEXT:    sb a3, 12(a2)
-; RV64I-NEXT:    srli a3, a0, 24
-; RV64I-NEXT:    sb a3, 11(a2)
-; RV64I-NEXT:    srli a3, a0, 16
-; RV64I-NEXT:    sb a3, 10(a2)
-; RV64I-NEXT:    srli a0, a0, 8
-; RV64I-NEXT:    sb a0, 9(a2)
-; RV64I-NEXT:    srli a0, a1, 56
-; RV64I-NEXT:    sb a0, 7(a2)
-; RV64I-NEXT:    srli a0, a1, 48
-; RV64I-NEXT:    sb a0, 6(a2)
-; RV64I-NEXT:    srli a0, a1, 40
-; RV64I-NEXT:    sb a0, 5(a2)
-; RV64I-NEXT:    srli a0, a1, 32
-; RV64I-NEXT:    sb a0, 4(a2)
-; RV64I-NEXT:    srli a0, a1, 24
-; RV64I-NEXT:    sb a0, 3(a2)
-; RV64I-NEXT:    srli a0, a1, 16
-; RV64I-NEXT:    sb a0, 2(a2)
+; RV64I-NEXT:    sb a0, 8(a2)
+; RV64I-NEXT:    srli a3, a1, 56
+; RV64I-NEXT:    sb a3, 7(a2)
+; RV64I-NEXT:    srli a3, a1, 48
+; RV64I-NEXT:    sb a3, 6(a2)
+; RV64I-NEXT:    srli a3, a1, 40
+; RV64I-NEXT:    sb a3, 5(a2)
+; RV64I-NEXT:    srli a3, a1, 32
+; RV64I-NEXT:    sb a3, 4(a2)
+; RV64I-NEXT:    srli a3, a1, 24
+; RV64I-NEXT:    sb a3, 3(a2)
+; RV64I-NEXT:    srli a3, a1, 16
+; RV64I-NEXT:    sb a3, 2(a2)
 ; RV64I-NEXT:    srli a1, a1, 8
 ; RV64I-NEXT:    sb a1, 1(a2)
+; RV64I-NEXT:    srli a1, a0, 56
+; RV64I-NEXT:    sb a1, 15(a2)
+; RV64I-NEXT:    srli a1, a0, 48
+; RV64I-NEXT:    sb a1, 14(a2)
+; RV64I-NEXT:    srli a1, a0, 40
+; RV64I-NEXT:    sb a1, 13(a2)
+; RV64I-NEXT:    srli a1, a0, 32
+; RV64I-NEXT:    sb a1, 12(a2)
+; RV64I-NEXT:    srli a1, a0, 24
+; RV64I-NEXT:    sb a1, 11(a2)
+; RV64I-NEXT:    srli a1, a0, 16
+; RV64I-NEXT:    sb a1, 10(a2)
+; RV64I-NEXT:    srli a0, a0, 8
+; RV64I-NEXT:    sb a0, 9(a2)
 ; RV64I-NEXT:    ret
 ;
 ; RV32I-LABEL: shl_16bytes:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -64
 ; RV32I-NEXT:    sw s0, 60(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 56(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 52(sp) # 4-byte Folded Spill