[RISCV]Combine (select(seteq (and X, 1 << C), 0) to select_cc

[liaolucy]

Summary

Sometimes (select(seteq (and X, 1 << C), 0) is converted to select + (srl X, C),
this patch will prevent generating srl instructions and
better use of the optimization in translateSetCCForBranch(D130203).

If we enable shouldAvoidTransformToShift, it will have the same effect, but many tests
will have regressions, so if we enable shouldAvoidTransformToShift in the future,
this patch can be removed.

[craig.topper]

The test cases here only test the most significant bit, but your patch checks any power of 2. Can you add more test?

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

10656

This looks like we're using ISD::SELECT_CC to hide from other transforms. We don't normally use ISD::SELECT_CC on RISC-V. Can we detect the srl form as an additional case in translateSetCCForBranch instead?

[liaolucy]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

10656

Optimized type-legalized selection DAG: %bb.0 'bit_31_nz_select_i32:'
SelectionDAG has 13 nodes:
  t0: ch,glue = EntryToken
        t2: i32,ch = CopyFromReg t0, Register:i32 %0
      t21: i32 = srl t2, Constant:i32<31>
      t4: i32,ch = CopyFromReg t0, Register:i32 %1
      t6: i32,ch = CopyFromReg t0, Register:i32 %2
    t12: i32 = select t21, t4, t6
  t14: ch,glue = CopyToReg t0, Register:i32 $x10, t12
  t15: ch = RISCVISD::RET_FLAG t14, Register:i32 $x10, t14:1

The test is not executed by translateSetCCForBranch. It is returned earlier in lowerSELECT.

// If the condition is not an integer SETCC which operates on XLenVT, we need
// to emit a RISCVISD::SELECT_CC comparing the condition to zero. i.e.:
// (select condv, truev, falsev)
// -> (riscvisd::select_cc condv, zero, setne, truev, falsev)
if (CondV.getOpcode() != ISD::SETCC ||
    CondV.getOperand(0).getSimpleValueType() != XLenVT) {
  SDValue Zero = DAG.getConstant(0, DL, XLenVT);
  SDValue SetNE = DAG.getCondCode(ISD::SETNE);

  SDValue Ops[] = {CondV, Zero, SetNE, TrueV, FalseV};

  return DAG.getNode(RISCVISD::SELECT_CC, DL, VT, Ops);
}

Maybe the code for LowerSelect needs to be refactored, I'll try it.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
                                     const RISCVSubtarget &Subtarget) {
   if (Subtarget.hasShortForwardBranchOpt())
     return SDValue();
 
   // Only support XLenVT.
   if (N->getValueType(0) != Subtarget.getXLenVT())
     return SDValue();
 
-  SDValue TrueVal = N->getOperand(1);
-  SDValue FalseVal = N->getOperand(2);
-  if (SDValue V = tryFoldSelectIntoOp(N, DAG, TrueVal, FalseVal, /*Swapped*/false))
+  SDValue TrueV = N->getOperand(1);
+  SDValue FalseV = N->getOperand(2);
+  if (SDValue V = tryFoldSelectIntoOp(N, DAG, TrueV, FalseV, /*Swapped*/ false))
     return V;
-  return tryFoldSelectIntoOp(N, DAG, FalseVal, TrueVal, /*Swapped*/true);
+  if (SDValue V = tryFoldSelectIntoOp(N, DAG, FalseV, TrueV, /*Swapped*/ true))
+    return V;
+
+  SDValue CondV = N->getOperand(0);
+  if ((!Subtarget.hasVendorXVentanaCondOps() &&
+       !Subtarget.hasVendorXTHeadCondMov()) &&
+      CondV->hasOneUse() && CondV->getOpcode() == ISD::SETCC) {
+    SDValue CondL = CondV->getOperand(0);
+    SDValue CondR = CondV->getOperand(1);
+    ISD::CondCode CC = cast<CondCodeSDNode>(CondV.getOperand(2))->get();
+    if (CondL->getOpcode() == ISD::AND && isNullConstant(CondR) &&
+        isIntEqualitySetCC(CC)) {
+      uint64_t Mask = CondL.getConstantOperandVal(1);
+      if (isPowerOf2_64(Mask) && !isInt<12>(Mask)) {
+        SDLoc DL(N);
+        SDValue Ops[] = {CondL, CondR, N->getOperand(1) /*TrueV*/,
+                         N->getOperand(2) /*FalseV*/, CondV->getOperand(2)};
+        return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0), Ops);
+      }
+    }
+  }
+
+  return SDValue();
 }
 
 SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
                                                DAGCombinerInfo &DCI) const {
   SelectionDAG &DAG = DCI.DAG;
 
   // Helper to call SimplifyDemandedBits on an operand of N where only some low
   // bits are demanded. N will be added to the Worklist if it was not deleted.

llvm/test/CodeGen/RISCV/bittest.ll

; RV64-NEXT:    ret
   %2 = icmp eq i32 %1, 0
   %3 = select i1 %2, i32 %b, i32 %c
   ret i32 %3
 }
 
 define signext i32 @bit_31_nz_select_i32(i32 signext %a, i32 signext %b, i32 signext %c) {
 ; RV32-LABEL: bit_31_nz_select_i32:
 ; RV32:       # %bb.0:
-; RV32-NEXT:    srli a3, a0, 31
-; RV32-NEXT:    mv a0, a1
-; RV32-NEXT:    bnez a3, .LBB22_2
+; RV32-NEXT:    bltz a0, .LBB22_2
 ; RV32-NEXT:  # %bb.1:
-; RV32-NEXT:    mv a0, a2
+; RV32-NEXT:    mv a1, a2
 ; RV32-NEXT:  .LBB22_2:
+; RV32-NEXT:    mv a0, a1
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bit_31_nz_select_i32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    lui a3, 524288
 ; RV64-NEXT:    and a3, a0, a3
 ; RV64-NEXT:    mv a0, a1
 ; RV64-NEXT:    bnez a3, .LBB22_2

 ; RV32-NEXT:  # %bb.1:
 ; RV32-NEXT:    mv a0, a4
 ; RV32-NEXT:    mv a1, a5
 ; RV32-NEXT:  .LBB36_2:
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: bit_63_nz_select_i64:
 ; RV64:       # %bb.0:
-; RV64-NEXT:    srli a3, a0, 63
-; RV64-NEXT:    mv a0, a1
-; RV64-NEXT:    bnez a3, .LBB36_2
+; RV64-NEXT:    bltz a0, .LBB36_2
 ; RV64-NEXT:  # %bb.1:
-; RV64-NEXT:    mv a0, a2
+; RV64-NEXT:    mv a1, a2
 ; RV64-NEXT:  .LBB36_2:
+; RV64-NEXT:    mv a0, a1
 ; RV64-NEXT:    ret
   %1 = and i64 %a, 9223372036854775808
   %2 = icmp ne i64 %1, 0
   %3 = select i1 %2, i64 %b, i64 %c
   ret i64 %3
 }
 
 define void @bit_10_z_branch_i32(i32 signext %0) {