[RISCV] Merge getLoadFP*Imm into a single function.

[craig.topper]

Summary

We currently have 3 functions and 3 lookup tables. This was the
most expediant and obvious way to fix several bugs.

This patch uses a single function and single lookup
table. It uses APFloat::convert to convert from the half or double
to single precision. If the conversion doesn't have any errors or
lose any information we use the f32 table to finish the lookup.

[joshua-arch1]

LGTM.

[asb]

Posting for early feedback as to whether this makes sense to do.

I think it makes sense to do it.

[craig.topper]

Add more tests for half and double.
Code cleanup

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

1547

I used if/else because switch on EVT requires VT.isSimple() first.

[asb]

LGTM. Could you precommit the tests though, as it's a bit confusing to add new tests when I think these pass even without the change.

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

public:
   bool isRTZArg() const { return isFRMArg() && FRM.FRM == RISCVFPRndMode::RTZ; }
 
   /// Return true if the operand is a valid fli.s floating-point immediate.
   bool isLoadFPImm() const {
     if (isImm())
       return isUImm5();
     if (Kind != KindTy::FPImmediate)
       return false;
-    int Idx = RISCVLoadFPImm::getLoadFP64Imm(
+    int Idx = RISCVLoadFPImm::getLoadFPImm(
         APFloat(APFloat::IEEEdouble(), APInt(64, getFPConst())));
     // Don't allow decimal version of the minimum value. It is a different value
     // for each supported data type.
     return Idx >= 0 && Idx != 1;
   }
 
   bool isImmXLenLI() const {
     int64_t Imm;
public:
 
   void addFPImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     if (isImm()) {
       addExpr(Inst, getImm(), isRV64Imm());
       return;
     }
 
-    int Imm = RISCVLoadFPImm::getLoadFP64Imm(
+    int Imm = RISCVLoadFPImm::getLoadFPImm(
         APFloat(APFloat::IEEEdouble(), APInt(64, getFPConst())));
     Inst.addOperand(MCOperand::createImm(Imm));
   }
 
   void addFenceArgOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createImm(Fence.Val));
   }

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

 
 //===----------------------------------------------------------------------===//
 // Floating-point Immediates
 //
 
 namespace RISCVLoadFPImm {
 float getFPImm(unsigned Imm);
 
-/// getLoadFP32Imm - Return a 5-bit binary encoding of the 32-bit
-/// floating-point immediate value. If the value cannot be represented as a
-/// 5-bit binary encoding, then return -1.
-int getLoadFP32Imm(const APFloat &FPImm);
-
-/// getLoadFP64Imm - Return a 5-bit binary encoding of the 64-bit
-/// floating-point immediate value. If the value cannot be represented as a
-/// 5-bit binary encoding, then return -1.
-int getLoadFP64Imm(const APFloat &FPImm);
-
-/// getLoadFP16Imm - Return a 5-bit binary encoding of the 16-bit
-/// floating-point immediate value. If the value cannot be represented as a
-/// 5-bit binary encoding, then return -1.
-int getLoadFP16Imm(const APFloat &FPImm);
+/// getLoadFPImm - Return a 5-bit binary encoding of the floating-point
+/// immediate value. If the value cannot be represented as a 5-bit binary
+/// encoding, then return -1.
+int getLoadFPImm(APFloat FPImm);
 } // namespace RISCVLoadFPImm
 
 namespace RISCVSysReg {
 struct SysReg {
   const char *Name;
   const char *AltName;
   const char *DeprecatedName;
   unsigned Encoding;

llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp

bool RISCVRVC::compress(MCInst &OutInst, const MCInst &MI,
   return compressInst(OutInst, MI, STI);
 }
 
 bool RISCVRVC::uncompress(MCInst &OutInst, const MCInst &MI,
                           const MCSubtargetInfo &STI) {
   return uncompressInst(OutInst, MI, STI);
 }
 
-// Lookup table for fli.h for entries 1-31. Entry 0(-1.0) is handled separately.
-// NOTE: The exponent for entry 1 is larger than entry 2 and 3 because they
-// are denormals.
-static constexpr std::pair<uint8_t, uint8_t> LoadFP16ImmArr[] = {
-    {0b00001, 0b00}, {0b00000, 0b01}, {0b00000, 0b10}, {0b00111, 0b00},
-    {0b01000, 0b00}, {0b01011, 0b00}, {0b01100, 0b00}, {0b01101, 0b00},
-    {0b01101, 0b01}, {0b01101, 0b10}, {0b01101, 0b11}, {0b01110, 0b00},
-    {0b01110, 0b01}, {0b01110, 0b10}, {0b01110, 0b11}, {0b01111, 0b00},
-    {0b01111, 0b01}, {0b01111, 0b10}, {0b01111, 0b11}, {0b10000, 0b00},
-    {0b10000, 0b01}, {0b10000, 0b10}, {0b10001, 0b00}, {0b10010, 0b00},
-    {0b10011, 0b00}, {0b10110, 0b00}, {0b10111, 0b00}, {0b11110, 0b00},
-    {0b11111, 0b00}, {0b11111, 0b00}, {0b11111, 0b10},
-};
-
-// Lookup table for fli.s for entries 1-31.
+// Lookup table for fli.s for entries 2-31.
 static constexpr std::pair<uint8_t, uint8_t> LoadFP32ImmArr[] = {
-    {0b00000001, 0b00}, {0b01101111, 0b00}, {0b01110000, 0b00},
-    {0b01110111, 0b00}, {0b01111000, 0b00}, {0b01111011, 0b00},
-    {0b01111100, 0b00}, {0b01111101, 0b00}, {0b01111101, 0b01},
-    {0b01111101, 0b10}, {0b01111101, 0b11}, {0b01111110, 0b00},
-    {0b01111110, 0b01}, {0b01111110, 0b10}, {0b01111110, 0b11},
-    {0b01111111, 0b00}, {0b01111111, 0b01}, {0b01111111, 0b10},
-    {0b01111111, 0b11}, {0b10000000, 0b00}, {0b10000000, 0b01},
-    {0b10000000, 0b10}, {0b10000001, 0b00}, {0b10000010, 0b00},
-    {0b10000011, 0b00}, {0b10000110, 0b00}, {0b10000111, 0b00},
-    {0b10001110, 0b00}, {0b10001111, 0b00}, {0b11111111, 0b00},
-    {0b11111111, 0b10},
-};
-
-// Lookup table for fli.d for entries 1-31.
-static constexpr std::pair<uint16_t, uint8_t> LoadFP64ImmArr[] = {
-    {0b00000000001, 0b00}, {0b01111101111, 0b00}, {0b01111110000, 0b00},
-    {0b01111110111, 0b00}, {0b01111111000, 0b00}, {0b01111111011, 0b00},
-    {0b01111111100, 0b00}, {0b01111111101, 0b00}, {0b01111111101, 0b01},
-    {0b01111111101, 0b10}, {0b01111111101, 0b11}, {0b01111111110, 0b00},
-    {0b01111111110, 0b01}, {0b01111111110, 0b10}, {0b01111111110, 0b11},
-    {0b01111111111, 0b00}, {0b01111111111, 0b01}, {0b01111111111, 0b10},
-    {0b01111111111, 0b11}, {0b10000000000, 0b00}, {0b10000000000, 0b01},
-    {0b10000000000, 0b10}, {0b10000000001, 0b00}, {0b10000000010, 0b00},
-    {0b10000000011, 0b00}, {0b10000000110, 0b00}, {0b10000000111, 0b00},
-    {0b10000001110, 0b00}, {0b10000001111, 0b00}, {0b11111111111, 0b00},
-    {0b11111111111, 0b10},
+    {0b01101111, 0b00}, {0b01110000, 0b00}, {0b01110111, 0b00},
+    {0b01111000, 0b00}, {0b01111011, 0b00}, {0b01111100, 0b00},
+    {0b01111101, 0b00}, {0b01111101, 0b01}, {0b01111101, 0b10},
+    {0b01111101, 0b11}, {0b01111110, 0b00}, {0b01111110, 0b01},
+    {0b01111110, 0b10}, {0b01111110, 0b11}, {0b01111111, 0b00},
+    {0b01111111, 0b01}, {0b01111111, 0b10}, {0b01111111, 0b11},
+    {0b10000000, 0b00}, {0b10000000, 0b01}, {0b10000000, 0b10},
+    {0b10000001, 0b00}, {0b10000010, 0b00}, {0b10000011, 0b00},
+    {0b10000110, 0b00}, {0b10000111, 0b00}, {0b10001110, 0b00},
+    {0b10001111, 0b00}, {0b11111111, 0b00}, {0b11111111, 0b10},
 };
 
-int RISCVLoadFPImm::getLoadFP16Imm(const APFloat &FPImm) {
-  assert(&FPImm.getSemantics() == &APFloat::IEEEhalf());
-
-  APInt Imm = FPImm.bitcastToAPInt();
-
-  if (Imm.extractBitsAsZExtValue(8, 0) != 0)
-    return -1;
-
-  bool Sign = Imm.extractBitsAsZExtValue(1, 15);
-  uint8_t Mantissa = Imm.extractBitsAsZExtValue(2, 8);
-  uint8_t Exp = Imm.extractBitsAsZExtValue(5, 10);
-
-  // The array isn't sorted so we must use std::find unlike fp32 and fp64.
-  auto EMI = llvm::find(LoadFP16ImmArr, std::make_pair(Exp, Mantissa));
-  if (EMI == std::end(LoadFP16ImmArr))
+int RISCVLoadFPImm::getLoadFPImm(APFloat FPImm) {
+  assert((&FPImm.getSemantics() == &APFloat::IEEEsingle() ||
+          &FPImm.getSemantics() == &APFloat::IEEEdouble() ||
+          &FPImm.getSemantics() == &APFloat::IEEEhalf()) &&
+         "Unexpected semantics");
+
+  // Handle the minimum normalized value which is different for each type.
+  if (FPImm.isSmallestNormalized())
+    return 1;
+
+  // Convert to single precision to use its lookup table.
+  bool LosesInfo;
+  APFloat::opStatus Status = FPImm.convert(
+      APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, &LosesInfo);
+  if (Status != APFloat::opOK || LosesInfo)
     return -1;
 
-  // Table doesn't have entry 0.
-  int Entry = std::distance(std::begin(LoadFP16ImmArr), EMI) + 1;
-
-  // The only legal negative value is -1.0(entry 0). 1.0 is entry 16.
-  if (Sign) {
-    if (Entry == 16)
-      return 0;
-    return false;
-  }
-
-  // Entry 29 and 30 are both infinity, but 30 is the real infinity.
-  if (Entry == 29)
-    ++Entry;
-
-  return Entry;
-}
-
-int RISCVLoadFPImm::getLoadFP32Imm(const APFloat &FPImm) {
-  assert(&FPImm.getSemantics() == &APFloat::IEEEsingle());
-
   APInt Imm = FPImm.bitcastToAPInt();
 
   if (Imm.extractBitsAsZExtValue(21, 0) != 0)
     return -1;
 
   bool Sign = Imm.extractBitsAsZExtValue(1, 31);
   uint8_t Mantissa = Imm.extractBitsAsZExtValue(2, 21);
   uint8_t Exp = Imm.extractBitsAsZExtValue(8, 23);
 
   auto EMI = llvm::lower_bound(LoadFP32ImmArr, std::make_pair(Exp, Mantissa));
   if (EMI == std::end(LoadFP32ImmArr) || EMI->first != Exp ||
       EMI->second != Mantissa)
     return -1;
 
-  // Table doesn't have entry 0.
-  int Entry = std::distance(std::begin(LoadFP32ImmArr), EMI) + 1;
-
-  // The only legal negative value is -1.0(entry 0). 1.0 is entry 16.
-  if (Sign) {
-    if (Entry == 16)
-      return 0;
-    return false;
-  }
-
-  return Entry;
-}
-
-int RISCVLoadFPImm::getLoadFP64Imm(const APFloat &FPImm) {
-  assert(&FPImm.getSemantics() == &APFloat::IEEEdouble());
-
-  APInt Imm = FPImm.bitcastToAPInt();
-
-  if (Imm.extractBitsAsZExtValue(50, 0) != 0)
-    return -1;
-
-  bool Sign = Imm.extractBitsAsZExtValue(1, 63);
-  uint8_t Mantissa = Imm.extractBitsAsZExtValue(2, 50);
-  uint16_t Exp = Imm.extractBitsAsZExtValue(11, 52);
-
-  auto EMI = llvm::lower_bound(LoadFP64ImmArr, std::make_pair(Exp, Mantissa));
-  if (EMI == std::end(LoadFP64ImmArr) || EMI->first != Exp ||
-      EMI->second != Mantissa)
-    return -1;
-
-  // Table doesn't have entry 0.
-  int Entry = std::distance(std::begin(LoadFP64ImmArr), EMI) + 1;
+  // Table doesn't have entry 0 or 1.
+  int Entry = std::distance(std::begin(LoadFP32ImmArr), EMI) + 2;
 
   // The only legal negative value is -1.0(entry 0). 1.0 is entry 16.
   if (Sign) {
     if (Entry == 16)
       return 0;
     return false;
   }
 
   return Entry;
 }
 
 float RISCVLoadFPImm::getFPImm(unsigned Imm) {
   assert(Imm != 1 && Imm != 30 && Imm != 31 && "Unsupported immediate");
 
   // Entry 0 is -1.0, the only negative value. Entry 16 is 1.0.
   uint32_t Sign = 0;
   if (Imm == 0) {
     Sign = 0b1;
     Imm = 16;
   }
 
-  uint32_t Exp = LoadFP32ImmArr[Imm - 1].first;
-  uint32_t Mantissa = LoadFP32ImmArr[Imm - 1].second;
+  uint32_t Exp = LoadFP32ImmArr[Imm - 2].first;
+  uint32_t Mantissa = LoadFP32ImmArr[Imm - 2].second;
 
   uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21;
   return bit_cast<float>(I);
 }
 
 } // namespace llvm

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

bool RISCVTargetLowering::isOffsetFoldingLegal(
   // In order to maximise the opportunity for common subexpression elimination,
   // keep a separate ADD node for the global address offset instead of folding
   // it in the global address node. Later peephole optimisations may choose to
   // fold it back in when profitable.
   return false;
 }
 
 bool RISCVTargetLowering::isLegalZfaFPImm(const APFloat &Imm, EVT VT) const {
-  if (!Subtarget.hasStdExtZfa() || !VT.isSimple())
+  if (!Subtarget.hasStdExtZfa())
     return false;
 
-  switch (VT.getSimpleVT().SimpleTy) {
-  default:
-    return false;
-  case MVT::f16:
-    return (Subtarget.hasStdExtZfh() || Subtarget.hasStdExtZvfh()) &&
-           RISCVLoadFPImm::getLoadFP16Imm(Imm) != -1;
-  case MVT::f32:
-    return RISCVLoadFPImm::getLoadFP32Imm(Imm) != -1;
-  case MVT::f64:
+  bool IsSupportedVT = false;
+  if (VT == MVT::f16) {
+    IsSupportedVT = Subtarget.hasStdExtZfh() || Subtarget.hasStdExtZvfh();
+  } else if (VT == MVT::f32) {
+    IsSupportedVT = true;
+  } else if (VT == MVT::f64) {
     assert(Subtarget.hasStdExtD() && "Expect D extension");
-    return RISCVLoadFPImm::getLoadFP64Imm(Imm) != -1;
+    IsSupportedVT = true;
   }
+
+  return IsSupportedVT && RISCVLoadFPImm::getLoadFPImm(Imm) != -1;
 }
 
 bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
                                        bool ForCodeSize) const {
   bool IsLegalVT = false;
   if (VT == MVT::f16)
     IsLegalVT = Subtarget.hasStdExtZfhOrZfhmin();
   else if (VT == MVT::f32)

llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td

 def : InstAlias<"fgeq.h $rd, $rs, $rt",
                 (FLEQ_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 }
 
 //===----------------------------------------------------------------------===//
 // Codegen patterns
 //===----------------------------------------------------------------------===//
 
-def fp32imm_to_loadfpimm : SDNodeXForm<fpimm, [{
-  return CurDAG->getTargetConstant(RISCVLoadFPImm::getLoadFP32Imm(N->getValueAPF()),
+def fpimm_to_loadfpimm : SDNodeXForm<fpimm, [{
+  return CurDAG->getTargetConstant(RISCVLoadFPImm::getLoadFPImm(N->getValueAPF()),
                                    SDLoc(N), Subtarget->getXLenVT());}]>;
 
-def fp64imm_to_loadfpimm : SDNodeXForm<fpimm, [{
-  return CurDAG->getTargetConstant(RISCVLoadFPImm::getLoadFP64Imm(N->getValueAPF()),
-                                   SDLoc(N), Subtarget->getXLenVT());}]>;
-
-def fp16imm_to_loadfpimm : SDNodeXForm<fpimm, [{
-  return CurDAG->getTargetConstant(RISCVLoadFPImm::getLoadFP16Imm(N->getValueAPF()),
-                                   SDLoc(N), Subtarget->getXLenVT());}]>;
 
 let Predicates = [HasStdExtZfa] in {
-def : Pat<(f32 fpimm:$imm), (FLI_S (fp32imm_to_loadfpimm fpimm:$imm))>;
+def : Pat<(f32 fpimm:$imm), (FLI_S (fpimm_to_loadfpimm fpimm:$imm))>;
 
 def: PatFprFpr<fminimum, FMINM_S, FPR32>;
 def: PatFprFpr<fmaximum, FMAXM_S, FPR32>;
 
 // frint rounds according to the current rounding mode and detects
 // inexact conditions.
 def: Pat<(any_frint FPR32 : $rs1), (FROUNDNX_S FPR32 : $rs1, 0b111)>;
 
 // fnearbyint is like frint but does not detect inexact conditions.
 def: Pat<(any_fnearbyint FPR32 : $rs1), (FROUND_S FPR32 : $rs1, 0b111)>;
 
 def: Pat<(any_fround FPR32 : $rs1), (FROUND_S FPR32 : $rs1, 0b100)>;
 def: Pat<(any_ffloor FPR32 : $rs1), (FROUND_S FPR32 : $rs1, 0b011)>;
 def: Pat<(any_fceil FPR32 : $rs1), (FROUND_S FPR32 : $rs1, 0b010)>;
 def: Pat<(any_ftrunc FPR32 : $rs1), (FROUND_S FPR32 : $rs1, 0b001)>;
 
 def: PatSetCC<FPR32, strict_fsetcc, SETLT, FLTQ_S>;
 def: PatSetCC<FPR32, strict_fsetcc, SETOLT, FLTQ_S>;
 def: PatSetCC<FPR32, strict_fsetcc, SETLE, FLEQ_S>;
 def: PatSetCC<FPR32, strict_fsetcc, SETOLE, FLEQ_S>;
 } // Predicates = [HasStdExtZfa]
 
 let Predicates = [HasStdExtZfa, HasStdExtD] in {
-def : Pat<(f64 fpimm:$imm), (FLI_D (fp64imm_to_loadfpimm fpimm:$imm))>;
+def : Pat<(f64 fpimm:$imm), (FLI_D (fpimm_to_loadfpimm fpimm:$imm))>;
 
 def: PatFprFpr<fminimum, FMINM_D, FPR64>;
 def: PatFprFpr<fmaximum, FMAXM_D, FPR64>;
 
 // frint rounds according to the current rounding mode and detects
 // inexact conditions.
 def: Pat<(any_frint FPR64 : $rs1), (FROUNDNX_D FPR64 : $rs1, 0b111)>;
 

 } // Predicates = [HasStdExtZfa, HasStdExtD]
 
 let Predicates = [HasStdExtZfa, HasStdExtD, IsRV32] in {
 def : Pat<(RISCVBuildPairF64 GPR:$rs1, GPR:$rs2),
           (FMVP_D_X GPR:$rs1, GPR:$rs2)>;
 }
 
 let Predicates = [HasStdExtZfa, HasStdExtZfh] in {
-def : Pat<(f16 fpimm:$imm), (FLI_H (fp16imm_to_loadfpimm fpimm:$imm))>;
+def : Pat<(f16 fpimm:$imm), (FLI_H (fpimm_to_loadfpimm fpimm:$imm))>;
 
 def: PatFprFpr<fminimum, FMINM_H, FPR16>;
 def: PatFprFpr<fmaximum, FMAXM_H, FPR16>;
 
 // frint rounds according to the current rounding mode and detects
 // inexact conditions.
 def: Pat<(any_frint FPR16 : $rs1), (FROUNDNX_H FPR16 : $rs1, 0b111)>;