[RISCV][NFC] Reuse getDeinterleaveViaVNSRL to lower deinterleave intrinsics

[luke]

Summary

This modifies it to work on both scalable and fixed vectors

[luke]

Label as NFC

[reames]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2953

Personally, I'd leave this duplicated in each caller. Keeping the helper as an unconditionally successful routine seems worth the very minor code duplication.

[craig.topper]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

3163

Can this nest in the if (ContainerVT.isFixedLengthVector()) earlier. The source and destination should alway be both fixed or both scalable.

3167

To do my above suggestion, this would need to use ContainerVT to keep SrcContainerVT isolated to the body of the if (ContainerVT.isFixedLengthVector())

[luke]

Address comments

[reames]

LGTM w/comment applied.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

3478

There's no point in moving this check to the caller as the isDeinterleaveShuffle routine is only being used here. (Unless maybe you have another patch in mind, but if so, the change should probably be it's own NFC with that explained.)

[luke]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

3478

Yeah, IMO checking if the type is widenable is orthogonal to checking if a vector shuffle is a deinterleave. Splitting it out lets us reuse it for combining deinterleaves of loads of fixed vectors

[reames]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

3478

Please revert to the old form of the check, and we can discuss this change in the DAG combine change which uses it.

[luke]

Leave isDeinterleaveShuffle intact

[luke]

Update commit message

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 // t34: v8i8 = extract_subvector t11, Constant:i64<0>
 // t33: v8i8 = extract_subvector t11, Constant:i64<8>
 // a) t35: v8i8 = vector_shuffle<0,2,4,6,8,10,12,14> t34, t33
 // b) t35: v8i8 = vector_shuffle<1,3,5,7,9,11,13,15> t34, t33
 // Returns {Src Vector, Even Elements} om success
 static bool isDeinterleaveShuffle(MVT VT, MVT ContainerVT, SDValue V1,
                                   SDValue V2, ArrayRef<int> Mask,
                                   const RISCVSubtarget &Subtarget) {
-  // Need to be able to widen the vector.
-  if (VT.getScalarSizeInBits() >= Subtarget.getELEN())
-    return false;
-
   // Both input must be extracts.
   if (V1.getOpcode() != ISD::EXTRACT_SUBVECTOR ||
       V2.getOpcode() != ISD::EXTRACT_SUBVECTOR)
     return false;
 
   // Extracting from the same source.
   SDValue Src = V1.getOperand(0);
   if (Src != V2.getOperand(0))
static int isElementRotate(int &LoSrc, int &HiSrc, ArrayRef<int> Mask) {
   assert(Rotation != 0 && "Failed to locate a viable rotation!");
   assert((LoSrc >= 0 || HiSrc >= 0) &&
          "Failed to find a rotated input vector!");
 
   return Rotation;
 }
 
 // Lower a deinterleave shuffle to vnsrl.
-static SDValue getDeinterleaveViaVNSRL(const SDLoc &DL, MVT VT,
-                                       MVT ContainerVT,
-                                       SDValue Src, bool EvenElts,
-                                       SDValue TrueMask, SDValue VL,
+// [a, p, b, q, c, r, d, s] -> [a, b, c, d] (EvenElts == true)
+//                          -> [p, q, r, s] (EvenElts == false)
+// VT is the type of the vector to return, <[vscale x ]n x ty>
+// Src is the vector to deinterleave of type <[vscale x ]n*2 x ty>
+static SDValue getDeinterleaveViaVNSRL(const SDLoc &DL, MVT VT, SDValue Src,
+                                       bool EvenElts,
                                        const RISCVSubtarget &Subtarget,
                                        SelectionDAG &DAG) {
-  // Convert the source using a container type with twice the elements. Since
-  // source VT is legal and twice this VT, we know VT isn't LMUL=8 so it is
-  // safe to double.
-  MVT DoubleContainerVT =
+
+  // The result is a vector of type <m x n x ty>
+  MVT ContainerVT = VT;
+  // Convert fixed vectors to scalable if needed
+  if (ContainerVT.isFixedLengthVector()) {
+    assert(Src.getSimpleValueType().isFixedLengthVector());
+    ContainerVT = getContainerForFixedLengthVector(DAG, ContainerVT, Subtarget);
+
+    // The source is a vector of type <m x n*2 x ty>
+    MVT SrcContainerVT =
         MVT::getVectorVT(ContainerVT.getVectorElementType(),
                          ContainerVT.getVectorElementCount() * 2);
-  Src = convertToScalableVector(DoubleContainerVT, Src, DAG, Subtarget);
+    Src = convertToScalableVector(SrcContainerVT, Src, DAG, Subtarget);
+  }
+
+  auto [TrueMask, VL] = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
 
-  // Convert the vector to a wider integer type with the original element
-  // count. This also converts FP to int.
+  // Bitcast the source vector from <m x n*2 x ty> -> <m x n x ty*2>
+  // This also converts FP to int.
   unsigned EltBits = ContainerVT.getScalarSizeInBits();
-  MVT WideIntContainerVT =
-    MVT::getVectorVT(MVT::getIntegerVT(EltBits * 2),
-                     ContainerVT.getVectorElementCount());
-  Src = DAG.getBitcast(WideIntContainerVT, Src);
+  MVT WideSrcContainerVT = MVT::getVectorVT(
+      MVT::getIntegerVT(EltBits * 2), ContainerVT.getVectorElementCount());
+  Src = DAG.getBitcast(WideSrcContainerVT, Src);
 
   // The integer version of the container type.
   MVT IntContainerVT = ContainerVT.changeVectorElementTypeToInteger();
 
   // If we want even elements, then the shift amount is 0. Otherwise, shift by
   // the original element size.
   unsigned Shift = EvenElts ? 0 : EltBits;
   SDValue SplatShift = DAG.getNode(
       RISCVISD::VMV_V_X_VL, DL, IntContainerVT, DAG.getUNDEF(ContainerVT),
       DAG.getConstant(Shift, DL, Subtarget.getXLenVT()), VL);
   SDValue Res =
       DAG.getNode(RISCVISD::VNSRL_VL, DL, IntContainerVT, Src, SplatShift,
                   DAG.getUNDEF(IntContainerVT), TrueMask, VL);
   // Cast back to FP if needed.
   Res = DAG.getBitcast(ContainerVT, Res);
 
-  return convertFromScalableVector(VT, Res, DAG, Subtarget);
+  if (VT.isFixedLengthVector())
+    Res = convertFromScalableVector(VT, Res, DAG, Subtarget);
+  return Res;
 }
 
 static SDValue
 getVSlidedown(SelectionDAG &DAG, const RISCVSubtarget &Subtarget, SDLoc DL,
               EVT VT, SDValue Merge, SDValue Op, SDValue Offset, SDValue Mask,
               SDValue VL,
               unsigned Policy = RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED) {
   if (Merge.isUndef())
     Policy = RISCVII::TAIL_AGNOSTIC | RISCVII::MASK_AGNOSTIC;
   SDValue PolicyOp = DAG.getTargetConstant(Policy, DL, Subtarget.getXLenVT());
   SDValue Ops[] = {Merge, Op, Offset, Mask, VL, PolicyOp};
if (Rotation > 0) {
     if (LoV)
       Res = getVSlideup(DAG, Subtarget, DL, ContainerVT, Res, LoV,
                         DAG.getConstant(InvRotate, DL, XLenVT), TrueMask, VL,
                         RISCVII::TAIL_AGNOSTIC);
 
     return convertFromScalableVector(VT, Res, DAG, Subtarget);
   }
 
-  if (isDeinterleaveShuffle(VT, ContainerVT, V1, V2, Mask, Subtarget))
-    return getDeinterleaveViaVNSRL(DL, VT, ContainerVT, V1.getOperand(0),
-                                   Mask[0] == 0, TrueMask, VL, Subtarget, DAG);
+  // If this is a deinterleave and we can widen the vector, then we can use
+  // vnsrl to deinterleave.
+  if (isDeinterleaveShuffle(VT, ContainerVT, V1, V2, Mask, Subtarget) &&
+      VT.getScalarSizeInBits() < Subtarget.getELEN()) {
+    return getDeinterleaveViaVNSRL(DL, VT, V1.getOperand(0), Mask[0] == 0,
+                                   Subtarget, DAG);
+  }
 
   // Detect an interleave shuffle and lower to
   // (vmaccu.vx (vwaddu.vx lohalf(V1), lohalf(V2)), lohalf(V2), (2^eltbits - 1))
   int EvenSrc, OddSrc;
   if (isInterleaveShuffle(Mask, VT, EvenSrc, OddSrc, Subtarget)) {
     // Extract the halves of the vectors.
     MVT HalfVT = VT.getHalfNumVectorElementsVT();
 
MVT ConcatVT =
                        VecVT.getVectorElementCount().multiplyCoefficientBy(2));
   SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, DL, ConcatVT,
                                Op.getOperand(0), Op.getOperand(1));
 
   // We want to operate on all lanes, so get the mask and VL and mask for it
   auto [Mask, VL] = getDefaultScalableVLOps(ConcatVT, DL, DAG, Subtarget);
   SDValue Passthru = DAG.getUNDEF(ConcatVT);
 
-  // If the element type is smaller than ELEN, then we can deinterleave
-  // through vnsrl.wi
+  // We can deinterleave through vnsrl.wi if the element type is smaller than
+  // ELEN
   if (VecVT.getScalarSizeInBits() < Subtarget.getELEN()) {
-    // Bitcast the concatenated vector from <n x m x ty> -> <n x m / 2 x ty * 2>
-    // This is also casts FPs to ints
-    MVT WideVT = MVT::getVectorVT(
-        MVT::getIntegerVT(ConcatVT.getScalarSizeInBits() * 2),
-        ConcatVT.getVectorElementCount().divideCoefficientBy(2));
-    SDValue Wide = DAG.getBitcast(WideVT, Concat);
-
-    MVT NarrowVT = VecVT.changeVectorElementTypeToInteger();
-    SDValue Passthru = DAG.getUNDEF(VecVT);
-
-    SDValue Even = DAG.getNode(
-        RISCVISD::VNSRL_VL, DL, NarrowVT, Wide,
-        DAG.getSplatVector(NarrowVT, DL, DAG.getConstant(0, DL, XLenVT)),
-        Passthru, Mask, VL);
-    SDValue Odd = DAG.getNode(
-        RISCVISD::VNSRL_VL, DL, NarrowVT, Wide,
-        DAG.getSplatVector(
-            NarrowVT, DL,
-            DAG.getConstant(VecVT.getScalarSizeInBits(), DL, XLenVT)),
-        Passthru, Mask, VL);
-
-    // Bitcast the results back in case it was casted from an FP vector
-    return DAG.getMergeValues(
-        {DAG.getBitcast(VecVT, Even), DAG.getBitcast(VecVT, Odd)}, DL);
+    SDValue Even =
+        getDeinterleaveViaVNSRL(DL, VecVT, Concat, true, Subtarget, DAG);
+    SDValue Odd =
+        getDeinterleaveViaVNSRL(DL, VecVT, Concat, false, Subtarget, DAG);
+    return DAG.getMergeValues({Even, Odd}, DL);
   }
 
   // For the indices, use the same SEW to avoid an extra vsetvli
   MVT IdxVT = ConcatVT.changeVectorElementTypeToInteger();
   // Create a vector of even indices {0, 2, 4, ...}
   SDValue EvenIdx =
       DAG.getStepVector(DL, IdxVT, APInt(IdxVT.getScalarSizeInBits(), 2));
   // Create a vector of odd indices {1, 3, 5, ... }